]>
Commit | Line | Data |
---|---|---|
b8eb71dc CYT |
1 | /* |
2 | * Copyright 2016 Chen-Yu Tsai | |
3 | * | |
4 | * Chen-Yu Tsai <wens@csie.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #ifndef _CCU_SUN9I_A80_H_ | |
18 | #define _CCU_SUN9I_A80_H_ | |
19 | ||
20 | #include <dt-bindings/clock/sun9i-a80-ccu.h> | |
21 | #include <dt-bindings/reset/sun9i-a80-ccu.h> | |
22 | ||
23 | #define CLK_PLL_C0CPUX 0 | |
24 | #define CLK_PLL_C1CPUX 1 | |
25 | ||
26 | /* pll-audio and pll-periph0 are exported to the PRCM block */ | |
27 | ||
28 | #define CLK_PLL_VE 4 | |
29 | #define CLK_PLL_DDR 5 | |
30 | #define CLK_PLL_VIDEO0 6 | |
31 | #define CLK_PLL_VIDEO1 7 | |
32 | #define CLK_PLL_GPU 8 | |
33 | #define CLK_PLL_DE 9 | |
34 | #define CLK_PLL_ISP 10 | |
35 | #define CLK_PLL_PERIPH1 11 | |
36 | ||
37 | /* The CPUX clocks are exported */ | |
38 | ||
39 | #define CLK_ATB0 14 | |
40 | #define CLK_AXI0 15 | |
41 | #define CLK_ATB1 16 | |
42 | #define CLK_AXI1 17 | |
43 | #define CLK_GTBUS 18 | |
44 | #define CLK_AHB0 19 | |
45 | #define CLK_AHB1 20 | |
46 | #define CLK_AHB2 21 | |
47 | #define CLK_APB0 22 | |
48 | #define CLK_APB1 23 | |
49 | #define CLK_CCI400 24 | |
50 | #define CLK_ATS 25 | |
51 | #define CLK_TRACE 26 | |
52 | ||
53 | /* module clocks and bus gates exported */ | |
54 | ||
55 | #define CLK_NUMBER (CLK_BUS_UART5 + 1) | |
56 | ||
57 | #endif /* _CCU_SUN9I_A80_H_ */ |