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1d80c142 MR |
1 | /* |
2 | * Copyright (c) 2016 Maxime Ripard. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #ifndef _COMMON_H_ | |
15 | #define _COMMON_H_ | |
16 | ||
17 | #include <linux/compiler.h> | |
18 | #include <linux/clk-provider.h> | |
19 | ||
20 | #define CCU_FEATURE_FRACTIONAL BIT(0) | |
21 | #define CCU_FEATURE_VARIABLE_PREDIV BIT(1) | |
22 | #define CCU_FEATURE_FIXED_PREDIV BIT(2) | |
23 | #define CCU_FEATURE_FIXED_POSTDIV BIT(3) | |
7c09b858 | 24 | #define CCU_FEATURE_ALL_PREDIV BIT(4) |
3de64bf1 | 25 | #define CCU_FEATURE_LOCK_REG BIT(5) |
f6f64ed8 | 26 | #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) |
05d2eaac | 27 | #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7) |
f6f64ed8 CYT |
28 | |
29 | /* MMC timing mode switch bit */ | |
30 | #define CCU_MMC_NEW_TIMING_MODE BIT(30) | |
1d80c142 MR |
31 | |
32 | struct device_node; | |
33 | ||
34 | #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ | |
35 | &(struct clk_init_data) { \ | |
36 | .flags = _flags, \ | |
37 | .name = _name, \ | |
38 | .parent_names = (const char *[]) { _parent }, \ | |
39 | .num_parents = 1, \ | |
40 | .ops = _ops, \ | |
41 | } | |
42 | ||
43 | #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ | |
44 | &(struct clk_init_data) { \ | |
45 | .flags = _flags, \ | |
46 | .name = _name, \ | |
47 | .parent_names = _parents, \ | |
48 | .num_parents = ARRAY_SIZE(_parents), \ | |
49 | .ops = _ops, \ | |
50 | } | |
51 | ||
52 | #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ | |
53 | _div, _mult, _flags) \ | |
54 | struct clk_fixed_factor _struct = { \ | |
55 | .div = _div, \ | |
56 | .mult = _mult, \ | |
57 | .hw.init = CLK_HW_INIT(_name, \ | |
58 | _parent, \ | |
59 | &clk_fixed_factor_ops, \ | |
60 | _flags), \ | |
61 | } | |
62 | ||
63 | struct ccu_common { | |
64 | void __iomem *base; | |
65 | u16 reg; | |
3de64bf1 | 66 | u16 lock_reg; |
7c09b858 | 67 | u32 prediv; |
1d80c142 MR |
68 | |
69 | unsigned long features; | |
70 | spinlock_t *lock; | |
71 | struct clk_hw hw; | |
72 | }; | |
73 | ||
74 | static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) | |
75 | { | |
76 | return container_of(hw, struct ccu_common, hw); | |
77 | } | |
78 | ||
79 | struct sunxi_ccu_desc { | |
80 | struct ccu_common **ccu_clks; | |
81 | unsigned long num_ccu_clks; | |
82 | ||
83 | struct clk_hw_onecell_data *hw_clks; | |
84 | ||
85 | struct ccu_reset_map *resets; | |
86 | unsigned long num_resets; | |
87 | }; | |
88 | ||
89 | void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock); | |
90 | ||
02ae2bc6 CYT |
91 | struct ccu_pll_nb { |
92 | struct notifier_block clk_nb; | |
93 | struct ccu_common *common; | |
94 | ||
95 | u32 enable; | |
96 | u32 lock; | |
97 | }; | |
98 | ||
99 | #define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb) | |
100 | ||
101 | int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb); | |
102 | ||
1d80c142 MR |
103 | int sunxi_ccu_probe(struct device_node *node, void __iomem *reg, |
104 | const struct sunxi_ccu_desc *desc); | |
105 | ||
106 | #endif /* _COMMON_H_ */ |