[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / tegra / clk-emc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drivers/clk/tegra/clk-emc.c
 *
 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * Author:
 *	Mikko Perttunen <mperttunen@nvidia.com>
 */

#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sort.h>
#include <linux/string.h>

#include <soc/tegra/fuse.h>
#include <soc/tegra/emc.h>

#include "clk.h"

#define CLK_SOURCE_EMC 0x19c

#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
					      CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)

#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
					  CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)

static const char * const emc_parent_clk_names[] = {
	"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
	"pll_c2", "pll_c3", "pll_c_ud"
};

/*
 * List of clock sources for various parents the EMC clock can have.
 * When we change the timing to a timing with a parent that has the same
 * clock source as the current parent, we must first change to a backup
 * timing that has a different clock source.
 */

#define EMC_SRC_PLL_M 0
#define EMC_SRC_PLL_C 1
#define EMC_SRC_PLL_P 2
#define EMC_SRC_CLK_M 3
#define EMC_SRC_PLL_C2 4
#define EMC_SRC_PLL_C3 5

static const char emc_parent_clk_sources[] = {
	EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
	EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
};

struct emc_timing {
	unsigned long rate, parent_rate;
	u8 parent_index;
	struct clk *parent;
	u32 ram_code;
};

struct tegra_clk_emc {
	struct clk_hw hw;
	void __iomem *clk_regs;
	struct clk *prev_parent;
	bool changing_timing;

	struct device_node *emc_node;
	struct tegra_emc *emc;

	int num_timings;
	struct emc_timing *timings;
	spinlock_t *lock;
};

/* Common clock framework callback implementations */

static unsigned long emc_recalc_rate(struct clk_hw *hw,
				     unsigned long parent_rate)
{
	struct tegra_clk_emc *tegra;
	u32 val, div;

	tegra = container_of(hw, struct tegra_clk_emc, hw);

	/*
	 * CCF wrongly assumes that the parent won't change during set_rate,
	 * so get the parent rate explicitly.
	 */
	parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));

	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
	div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;

	return parent_rate / (div + 2) * 2;
}

/*
 * Rounds up unless no higher rate exists, in which case down. This way is
 * safer since things have EMC rate floors. Also don't touch parent_rate
 * since we don't want the CCF to play with our parent clocks.
 */
static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
	struct tegra_clk_emc *tegra;
	u8 ram_code = tegra_read_ram_code();
	struct emc_timing *timing = NULL;
	int i, k, t;

	tegra = container_of(hw, struct tegra_clk_emc, hw);

	for (k = 0; k < tegra->num_timings; k++) {
		if (tegra->timings[k].ram_code == ram_code)
			break;
	}

	for (t = k; t < tegra->num_timings; t++) {
		if (tegra->timings[t].ram_code != ram_code)
			break;
	}

	for (i = k; i < t; i++) {
		timing = tegra->timings + i;

		if (timing->rate < req->rate && i != t - 1)
			continue;

		if (timing->rate > req->max_rate) {
			i = max(i, k + 1);
			req->rate = tegra->timings[i - 1].rate;
			return 0;
		}

		if (timing->rate < req->min_rate)
			continue;

		req->rate = timing->rate;
		return 0;
	}

	if (timing) {
		req->rate = timing->rate;
		return 0;
	}

	req->rate = clk_hw_get_rate(hw);
	return 0;
}

static u8 emc_get_parent(struct clk_hw *hw)
{
	struct tegra_clk_emc *tegra;
	u32 val;

	tegra = container_of(hw, struct tegra_clk_emc, hw);

	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);

	return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
		& CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
}

static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
{
	struct platform_device *pdev;

	if (tegra->emc)
		return tegra->emc;

	if (!tegra->emc_node)
		return NULL;

	pdev = of_find_device_by_node(tegra->emc_node);
	if (!pdev) {
		pr_err("%s: could not get external memory controller\n",
		       __func__);
		return NULL;
	}

	of_node_put(tegra->emc_node);
	tegra->emc_node = NULL;

	tegra->emc = platform_get_drvdata(pdev);
	if (!tegra->emc) {
		pr_err("%s: cannot find EMC driver\n", __func__);
		return NULL;
	}

	return tegra->emc;
}

static int emc_set_timing(struct tegra_clk_emc *tegra,
			  struct emc_timing *timing)
{
	int err;
	u8 div;
	u32 car_value;
	unsigned long flags = 0;
	struct tegra_emc *emc = emc_ensure_emc_driver(tegra);

	if (!emc)
		return -ENOENT;

	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
		 timing->parent_rate, __clk_get_name(timing->parent));

	if (emc_get_parent(&tegra->hw) == timing->parent_index &&
	    clk_get_rate(timing->parent) != timing->parent_rate) {
		WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n",
			  __clk_get_name(timing->parent),
			  clk_get_rate(timing->parent),
			  timing->parent_rate);
		return -EINVAL;
	}

	tegra->changing_timing = true;

	err = clk_set_rate(timing->parent, timing->parent_rate);
	if (err) {
		pr_err("cannot change parent %s rate to %ld: %d\n",
		       __clk_get_name(timing->parent), timing->parent_rate,
		       err);

		return err;
	}

	err = clk_prepare_enable(timing->parent);
	if (err) {
		pr_err("cannot enable parent clock: %d\n", err);
		return err;
	}

	div = timing->parent_rate / (timing->rate / 2) - 2;

	err = tegra_emc_prepare_timing_change(emc, timing->rate);
	if (err)
		return err;

	spin_lock_irqsave(tegra->lock, flags);

	car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);

	car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);

	car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);

	writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);

	spin_unlock_irqrestore(tegra->lock, flags);

	tegra_emc_complete_timing_change(emc, timing->rate);

	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
	clk_disable_unprepare(tegra->prev_parent);

	tegra->prev_parent = timing->parent;
	tegra->changing_timing = false;

	return 0;
}

/*
 * Get backup timing to use as an intermediate step when a change between
 * two timings with the same clock source has been requested. First try to
 * find a timing with a higher clock rate to avoid a rate below any set rate
 * floors. If that is not possible, find a lower rate.
 */
static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
					    int timing_index)
{
	int i;
	u32 ram_code = tegra_read_ram_code();
	struct emc_timing *timing;

	for (i = timing_index+1; i < tegra->num_timings; i++) {
		timing = tegra->timings + i;
		if (timing->ram_code != ram_code)
			break;

		if (emc_parent_clk_sources[timing->parent_index] !=
		    emc_parent_clk_sources[
		      tegra->timings[timing_index].parent_index])
			return timing;
	}

	for (i = timing_index-1; i >= 0; --i) {
		timing = tegra->timings + i;
		if (timing->ram_code != ram_code)
			break;

		if (emc_parent_clk_sources[timing->parent_index] !=
		    emc_parent_clk_sources[
		      tegra->timings[timing_index].parent_index])
			return timing;
	}

	return NULL;
}

static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
			unsigned long parent_rate)
{
	struct tegra_clk_emc *tegra;
	struct emc_timing *timing = NULL;
	int i, err;
	u32 ram_code = tegra_read_ram_code();

	tegra = container_of(hw, struct tegra_clk_emc, hw);

	if (clk_hw_get_rate(hw) == rate)
		return 0;

	/*
	 * When emc_set_timing changes the parent rate, CCF will propagate
	 * that downward to us, so ignore any set_rate calls while a rate
	 * change is already going on.
	 */
	if (tegra->changing_timing)
		return 0;

	for (i = 0; i < tegra->num_timings; i++) {
		if (tegra->timings[i].rate == rate &&
		    tegra->timings[i].ram_code == ram_code) {
			timing = tegra->timings + i;
			break;
		}
	}

	if (!timing) {
		pr_err("cannot switch to rate %ld without emc table\n", rate);
		return -EINVAL;
	}

	if (emc_parent_clk_sources[emc_get_parent(hw)] ==
	    emc_parent_clk_sources[timing->parent_index] &&
	    clk_get_rate(timing->parent) != timing->parent_rate) {
		/*
		 * Parent clock source not changed but parent rate has changed,
		 * need to temporarily switch to another parent
		 */

		struct emc_timing *backup_timing;

		backup_timing = get_backup_timing(tegra, i);
		if (!backup_timing) {
			pr_err("cannot find backup timing\n");
			return -EINVAL;
		}

		pr_debug("using %ld as backup rate when going to %ld\n",
			 backup_timing->rate, rate);

		err = emc_set_timing(tegra, backup_timing);
		if (err) {
			pr_err("cannot set backup timing: %d\n", err);
			return err;
		}
	}

	return emc_set_timing(tegra, timing);
}

/* Initialization and deinitialization */

static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
				   struct emc_timing *timing,
				   struct device_node *node)
{
	int err, i;
	u32 tmp;

	err = of_property_read_u32(node, "clock-frequency", &tmp);
	if (err) {
		pr_err("timing %pOF: failed to read rate\n", node);
		return err;
	}

	timing->rate = tmp;

	err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
	if (err) {
		pr_err("timing %pOF: failed to read parent rate\n", node);
		return err;
	}

	timing->parent_rate = tmp;

	timing->parent = of_clk_get_by_name(node, "emc-parent");
	if (IS_ERR(timing->parent)) {
		pr_err("timing %pOF: failed to get parent clock\n", node);
		return PTR_ERR(timing->parent);
	}

	timing->parent_index = 0xff;
	for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
		if (!strcmp(emc_parent_clk_names[i],
			    __clk_get_name(timing->parent))) {
			timing->parent_index = i;
			break;
		}
	}
	if (timing->parent_index == 0xff) {
		pr_err("timing %pOF: %s is not a valid parent\n",
		       node, __clk_get_name(timing->parent));
		clk_put(timing->parent);
		return -EINVAL;
	}

	return 0;
}

static int cmp_timings(const void *_a, const void *_b)
{
	const struct emc_timing *a = _a;
	const struct emc_timing *b = _b;

	if (a->rate < b->rate)
		return -1;
	else if (a->rate == b->rate)
		return 0;
	else
		return 1;
}

static int load_timings_from_dt(struct tegra_clk_emc *tegra,
				struct device_node *node,
				u32 ram_code)
{
	struct emc_timing *timings_ptr;
	struct device_node *child;
	int child_count = of_get_child_count(node);
	int i = 0, err;
	size_t size;

	size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);

	tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
	if (!tegra->timings)
		return -ENOMEM;

	timings_ptr = tegra->timings + tegra->num_timings;
	tegra->num_timings += child_count;

	for_each_child_of_node(node, child) {
		struct emc_timing *timing = timings_ptr + (i++);

		err = load_one_timing_from_dt(tegra, timing, child);
		if (err) {
			of_node_put(child);
			return err;
		}

		timing->ram_code = ram_code;
	}

	sort(timings_ptr, child_count, sizeof(struct emc_timing),
	     cmp_timings, NULL);

	return 0;
}

static const struct clk_ops tegra_clk_emc_ops = {
	.recalc_rate = emc_recalc_rate,
	.determine_rate = emc_determine_rate,
	.set_rate = emc_set_rate,
	.get_parent = emc_get_parent,
};

struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
				   spinlock_t *lock)
{
	struct tegra_clk_emc *tegra;
	struct clk_init_data init;
	struct device_node *node;
	u32 node_ram_code;
	struct clk *clk;
	int err;

	tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
	if (!tegra)
		return ERR_PTR(-ENOMEM);

	tegra->clk_regs = base;
	tegra->lock = lock;

	tegra->num_timings = 0;

	for_each_child_of_node(np, node) {
		err = of_property_read_u32(node, "nvidia,ram-code",
					   &node_ram_code);
		if (err)
			continue;

		/*
		 * Store timings for all ram codes as we cannot read the
		 * fuses until the apbmisc driver is loaded.
		 */
		err = load_timings_from_dt(tegra, node, node_ram_code);
		if (err) {
			of_node_put(node);
			return ERR_PTR(err);
		}
	}

	if (tegra->num_timings == 0)
		pr_warn("%s: no memory timings registered\n", __func__);

	tegra->emc_node = of_parse_phandle(np,
			"nvidia,external-memory-controller", 0);
	if (!tegra->emc_node)
		pr_warn("%s: couldn't find node for EMC driver\n", __func__);

	init.name = "emc";
	init.ops = &tegra_clk_emc_ops;
	init.flags = CLK_IS_CRITICAL;
	init.parent_names = emc_parent_clk_names;
	init.num_parents = ARRAY_SIZE(emc_parent_clk_names);

	tegra->hw.init = &init;

	clk = clk_register(NULL, &tegra->hw);
	if (IS_ERR(clk))
		return clk;

	tegra->prev_parent = clk_hw_get_parent_by_index(
		&tegra->hw, emc_get_parent(&tegra->hw))->clk;
	tegra->changing_timing = false;

	/* Allow debugging tools to see the EMC clock */
	clk_register_clkdev(clk, "emc", "tegra-clk-debug");

	return clk;
};
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
2db04f16 MP	2	/*
	3	* drivers/clk/tegra/clk-emc.c
	4	*
	5	* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
	6	*
	7	* Author:
	8	* Mikko Perttunen <mperttunen@nvidia.com>
2db04f16 MP	9	*/
	10
	11	#include <linux/clk-provider.h>
	12	#include <linux/clk.h>
	13	#include <linux/clkdev.h>
	14	#include <linux/delay.h>
62e59c4e	15	#include <linux/io.h>
2db04f16 MP	16	#include <linux/module.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_platform.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/sort.h>
	21	#include <linux/string.h>
	22
	23	#include <soc/tegra/fuse.h>
	24	#include <soc/tegra/emc.h>
	25
	26	#include "clk.h"
	27
	28	#define CLK_SOURCE_EMC 0x19c
	29
	30	#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
	31	#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
	32	#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
	33	CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
	34
	35	#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
	36	#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
	37	#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
	38	CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
	39
	40	static const char * const emc_parent_clk_names[] = {
	41	"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
	42	"pll_c2", "pll_c3", "pll_c_ud"
	43	};
	44
	45	/*
	46	* List of clock sources for various parents the EMC clock can have.
	47	* When we change the timing to a timing with a parent that has the same
	48	* clock source as the current parent, we must first change to a backup
	49	* timing that has a different clock source.
	50	*/
	51
	52	#define EMC_SRC_PLL_M 0
	53	#define EMC_SRC_PLL_C 1
	54	#define EMC_SRC_PLL_P 2
	55	#define EMC_SRC_CLK_M 3
	56	#define EMC_SRC_PLL_C2 4
	57	#define EMC_SRC_PLL_C3 5
	58
	59	static const char emc_parent_clk_sources[] = {
	60	EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
	61	EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
	62	};
	63
	64	struct emc_timing {
	65	unsigned long rate, parent_rate;
	66	u8 parent_index;
	67	struct clk *parent;
	68	u32 ram_code;
	69	};
	70
	71	struct tegra_clk_emc {
	72	struct clk_hw hw;
	73	void __iomem *clk_regs;
	74	struct clk *prev_parent;
	75	bool changing_timing;
	76
	77	struct device_node *emc_node;
	78	struct tegra_emc *emc;
	79
80	int num_timings;
81	struct emc_timing *timings;
82	spinlock_t *lock;
83	};
84
85	/* Common clock framework callback implementations */
86
87	static unsigned long emc_recalc_rate(struct clk_hw *hw,
88	unsigned long parent_rate)
89	{
90	struct tegra_clk_emc *tegra;
91	u32 val, div;
92
93	tegra = container_of(hw, struct tegra_clk_emc, hw);
94
95	/*
96	* CCF wrongly assumes that the parent won't change during set_rate,
97	* so get the parent rate explicitly.
98	*/
5cdb1dc5	99	parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2db04f16 MP	100
	101	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
	102	div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
	103
	104	return parent_rate / (div + 2) * 2;
	105	}
	106
	107	/*
	108	* Rounds up unless no higher rate exists, in which case down. This way is
	109	* safer since things have EMC rate floors. Also don't touch parent_rate
	110	* since we don't want the CCF to play with our parent clocks.
	111	*/
0817b62c	112	static int emc_determine_rate(struct clk_hw hw, struct clk_rate_request req)
2db04f16 MP	113	{
	114	struct tegra_clk_emc *tegra;
	115	u8 ram_code = tegra_read_ram_code();
	116	struct emc_timing *timing = NULL;
913c3072	117	int i, k, t;
2db04f16 MP	118
	119	tegra = container_of(hw, struct tegra_clk_emc, hw);
	120
888ca40e DO	121	for (k = 0; k < tegra->num_timings; k++) {
	122	if (tegra->timings[k].ram_code == ram_code)
	123	break;
	124	}
	125
913c3072 DO	126	for (t = k; t < tegra->num_timings; t++) {
913c3072 DO	127	if (tegra->timings[t].ram_code != ram_code)
888ca40e	128	break;
913c3072	129	}
890d6a54	130
913c3072	131	for (i = k; i < t; i++) {
890d6a54	132	timing = tegra->timings + i;
2db04f16	133
913c3072 DO	134	if (timing->rate < req->rate && i != t - 1)
	135	continue;
	136
0817b62c	137	if (timing->rate > req->max_rate) {
888ca40e	138	i = max(i, k + 1);
0817b62c BB	139	req->rate = tegra->timings[i - 1].rate;
0817b62c BB	140	return 0;
890d6a54 TV	141	}
890d6a54 TV	142
0817b62c	143	if (timing->rate < req->min_rate)
890d6a54	144	continue;
2db04f16	145
913c3072 DO	146	req->rate = timing->rate;
913c3072 DO	147	return 0;
890d6a54	148	}
2db04f16	149
0817b62c BB	150	if (timing) {
	151	req->rate = timing->rate;
	152	return 0;
	153	}
2db04f16	154
5cdb1dc5	155	req->rate = clk_hw_get_rate(hw);
0817b62c	156	return 0;
2db04f16 MP	157	}
	158
	159	static u8 emc_get_parent(struct clk_hw *hw)
	160	{
	161	struct tegra_clk_emc *tegra;
	162	u32 val;
	163
	164	tegra = container_of(hw, struct tegra_clk_emc, hw);
	165
	166	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
	167
	168	return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
	169	& CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
	170	}
	171
	172	static struct tegra_emc emc_ensure_emc_driver(struct tegra_clk_emc tegra)
	173	{
	174	struct platform_device *pdev;
	175
	176	if (tegra->emc)
	177	return tegra->emc;
	178
	179	if (!tegra->emc_node)
	180	return NULL;
	181
	182	pdev = of_find_device_by_node(tegra->emc_node);
	183	if (!pdev) {
	184	pr_err("%s: could not get external memory controller\n",
	185	__func__);
	186	return NULL;
	187	}
	188
	189	of_node_put(tegra->emc_node);
	190	tegra->emc_node = NULL;
	191
	192	tegra->emc = platform_get_drvdata(pdev);
	193	if (!tegra->emc) {
	194	pr_err("%s: cannot find EMC driver\n", __func__);
	195	return NULL;
	196	}
	197
	198	return tegra->emc;
	199	}
	200
	201	static int emc_set_timing(struct tegra_clk_emc *tegra,
	202	struct emc_timing *timing)
	203	{
	204	int err;
	205	u8 div;
	206	u32 car_value;
	207	unsigned long flags = 0;
	208	struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
	209
	210	if (!emc)
	211	return -ENOENT;
	212
	213	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
	214	timing->parent_rate, __clk_get_name(timing->parent));
	215
	216	if (emc_get_parent(&tegra->hw) == timing->parent_index &&
	217	clk_get_rate(timing->parent) != timing->parent_rate) {
f4037654 DO	218	WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n",
	219	__clk_get_name(timing->parent),
	220	clk_get_rate(timing->parent),
	221	timing->parent_rate);
2db04f16 MP	222	return -EINVAL;
	223	}
	224
	225	tegra->changing_timing = true;
	226
	227	err = clk_set_rate(timing->parent, timing->parent_rate);
	228	if (err) {
	229	pr_err("cannot change parent %s rate to %ld: %d\n",
	230	__clk_get_name(timing->parent), timing->parent_rate,
	231	err);
	232
	233	return err;
	234	}
	235
	236	err = clk_prepare_enable(timing->parent);
	237	if (err) {
	238	pr_err("cannot enable parent clock: %d\n", err);
	239	return err;
	240	}
	241
	242	div = timing->parent_rate / (timing->rate / 2) - 2;
	243
	244	err = tegra_emc_prepare_timing_change(emc, timing->rate);
	245	if (err)
	246	return err;
	247
	248	spin_lock_irqsave(tegra->lock, flags);
	249
	250	car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
	251
	252	car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
	253	car_value \|= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
	254
	255	car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
	256	car_value \|= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
	257
	258	writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
	259
	260	spin_unlock_irqrestore(tegra->lock, flags);
	261
	262	tegra_emc_complete_timing_change(emc, timing->rate);
	263
	264	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
	265	clk_disable_unprepare(tegra->prev_parent);
	266
	267	tegra->prev_parent = timing->parent;
	268	tegra->changing_timing = false;
	269
	270	return 0;
	271	}
	272
	273	/*
	274	* Get backup timing to use as an intermediate step when a change between
	275	* two timings with the same clock source has been requested. First try to
	276	* find a timing with a higher clock rate to avoid a rate below any set rate
	277	* floors. If that is not possible, find a lower rate.
	278	*/
	279	static struct emc_timing get_backup_timing(struct tegra_clk_emc tegra,
	280	int timing_index)
	281	{
	282	int i;
	283	u32 ram_code = tegra_read_ram_code();
	284	struct emc_timing *timing;
	285
286	for (i = timing_index+1; i < tegra->num_timings; i++) {
287	timing = tegra->timings + i;
288	if (timing->ram_code != ram_code)
888ca40e	289	break;
2db04f16 MP	290
	291	if (emc_parent_clk_sources[timing->parent_index] !=
	292	emc_parent_clk_sources[
	293	tegra->timings[timing_index].parent_index])
	294	return timing;
	295	}
	296
	297	for (i = timing_index-1; i >= 0; --i) {
	298	timing = tegra->timings + i;
	299	if (timing->ram_code != ram_code)
888ca40e	300	break;
2db04f16 MP	301
	302	if (emc_parent_clk_sources[timing->parent_index] !=
	303	emc_parent_clk_sources[
	304	tegra->timings[timing_index].parent_index])
	305	return timing;
	306	}
	307
	308	return NULL;
	309	}
	310
	311	static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
	312	unsigned long parent_rate)
	313	{
	314	struct tegra_clk_emc *tegra;
	315	struct emc_timing *timing = NULL;
	316	int i, err;
	317	u32 ram_code = tegra_read_ram_code();
	318
	319	tegra = container_of(hw, struct tegra_clk_emc, hw);
	320
5cdb1dc5	321	if (clk_hw_get_rate(hw) == rate)
2db04f16 MP	322	return 0;
	323
	324	/*
	325	* When emc_set_timing changes the parent rate, CCF will propagate
	326	* that downward to us, so ignore any set_rate calls while a rate
	327	* change is already going on.
	328	*/
	329	if (tegra->changing_timing)
	330	return 0;
	331
	332	for (i = 0; i < tegra->num_timings; i++) {
	333	if (tegra->timings[i].rate == rate &&
	334	tegra->timings[i].ram_code == ram_code) {
	335	timing = tegra->timings + i;
	336	break;
	337	}
	338	}
	339
	340	if (!timing) {
	341	pr_err("cannot switch to rate %ld without emc table\n", rate);
	342	return -EINVAL;
	343	}
	344
	345	if (emc_parent_clk_sources[emc_get_parent(hw)] ==
	346	emc_parent_clk_sources[timing->parent_index] &&
	347	clk_get_rate(timing->parent) != timing->parent_rate) {
	348	/*
	349	* Parent clock source not changed but parent rate has changed,
	350	* need to temporarily switch to another parent
	351	*/
	352
	353	struct emc_timing *backup_timing;
	354
	355	backup_timing = get_backup_timing(tegra, i);
	356	if (!backup_timing) {
	357	pr_err("cannot find backup timing\n");
	358	return -EINVAL;
	359	}
	360
	361	pr_debug("using %ld as backup rate when going to %ld\n",
	362	backup_timing->rate, rate);
	363
	364	err = emc_set_timing(tegra, backup_timing);
	365	if (err) {
	366	pr_err("cannot set backup timing: %d\n", err);
	367	return err;
	368	}
	369	}
	370
	371	return emc_set_timing(tegra, timing);
	372	}
	373
	374	/* Initialization and deinitialization */
	375
	376	static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
	377	struct emc_timing *timing,
	378	struct device_node *node)
	379	{
	380	int err, i;
	381	u32 tmp;
	382
	383	err = of_property_read_u32(node, "clock-frequency", &tmp);
	384	if (err) {
16673931	385	pr_err("timing %pOF: failed to read rate\n", node);
2db04f16 MP	386	return err;
	387	}
	388
	389	timing->rate = tmp;
	390
	391	err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
	392	if (err) {
16673931	393	pr_err("timing %pOF: failed to read parent rate\n", node);
2db04f16 MP	394	return err;
	395	}
	396
	397	timing->parent_rate = tmp;
	398
	399	timing->parent = of_clk_get_by_name(node, "emc-parent");
	400	if (IS_ERR(timing->parent)) {
16673931	401	pr_err("timing %pOF: failed to get parent clock\n", node);
2db04f16 MP	402	return PTR_ERR(timing->parent);
	403	}
	404
	405	timing->parent_index = 0xff;
	406	for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
	407	if (!strcmp(emc_parent_clk_names[i],
	408	__clk_get_name(timing->parent))) {
	409	timing->parent_index = i;
	410	break;
	411	}
	412	}
	413	if (timing->parent_index == 0xff) {
16673931 RH	414	pr_err("timing %pOF: %s is not a valid parent\n",
16673931 RH	415	node, __clk_get_name(timing->parent));
2db04f16 MP	416	clk_put(timing->parent);
	417	return -EINVAL;
	418	}
	419
	420	return 0;
	421	}
	422
	423	static int cmp_timings(const void _a, const void _b)
	424	{
	425	const struct emc_timing *a = _a;
	426	const struct emc_timing *b = _b;
	427
	428	if (a->rate < b->rate)
	429	return -1;
	430	else if (a->rate == b->rate)
	431	return 0;
	432	else
	433	return 1;
	434	}
	435
	436	static int load_timings_from_dt(struct tegra_clk_emc *tegra,
	437	struct device_node *node,
	438	u32 ram_code)
	439	{
888ca40e	440	struct emc_timing *timings_ptr;
2db04f16 MP	441	struct device_node *child;
	442	int child_count = of_get_child_count(node);
	443	int i = 0, err;
888ca40e DO	444	size_t size;
	445
	446	size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);
2db04f16	447
888ca40e	448	tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
2db04f16 MP	449	if (!tegra->timings)
	450	return -ENOMEM;
	451
888ca40e DO	452	timings_ptr = tegra->timings + tegra->num_timings;
888ca40e DO	453	tegra->num_timings += child_count;
2db04f16 MP	454
2db04f16 MP	455	for_each_child_of_node(node, child) {
888ca40e	456	struct emc_timing *timing = timings_ptr + (i++);
2db04f16 MP	457
2db04f16 MP	458	err = load_one_timing_from_dt(tegra, timing, child);
047d6d84 AKC	459	if (err) {
047d6d84 AKC	460	of_node_put(child);
2db04f16	461	return err;
047d6d84	462	}
2db04f16 MP	463
	464	timing->ram_code = ram_code;
	465	}
	466
888ca40e	467	sort(timings_ptr, child_count, sizeof(struct emc_timing),
2db04f16 MP	468	cmp_timings, NULL);
	469
	470	return 0;
	471	}
	472
	473	static const struct clk_ops tegra_clk_emc_ops = {
	474	.recalc_rate = emc_recalc_rate,
890d6a54	475	.determine_rate = emc_determine_rate,
2db04f16 MP	476	.set_rate = emc_set_rate,
	477	.get_parent = emc_get_parent,
	478	};
	479
	480	struct clk tegra_clk_register_emc(void __iomem base, struct device_node *np,
	481	spinlock_t *lock)
	482	{
	483	struct tegra_clk_emc *tegra;
	484	struct clk_init_data init;
	485	struct device_node *node;
	486	u32 node_ram_code;
	487	struct clk *clk;
	488	int err;
	489
	490	tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
	491	if (!tegra)
	492	return ERR_PTR(-ENOMEM);
	493
	494	tegra->clk_regs = base;
	495	tegra->lock = lock;
	496
	497	tegra->num_timings = 0;
	498
	499	for_each_child_of_node(np, node) {
	500	err = of_property_read_u32(node, "nvidia,ram-code",
	501	&node_ram_code);
4e4f485c	502	if (err)
2db04f16	503	continue;
2db04f16 MP	504
	505	/*
	506	* Store timings for all ram codes as we cannot read the
	507	* fuses until the apbmisc driver is loaded.
	508	*/
	509	err = load_timings_from_dt(tegra, node, node_ram_code);
888ca40e DO	510	if (err) {
888ca40e DO	511	of_node_put(node);
2db04f16	512	return ERR_PTR(err);
888ca40e	513	}
2db04f16 MP	514	}
	515
	516	if (tegra->num_timings == 0)
	517	pr_warn("%s: no memory timings registered\n", __func__);
	518
	519	tegra->emc_node = of_parse_phandle(np,
	520	"nvidia,external-memory-controller", 0);
	521	if (!tegra->emc_node)
	522	pr_warn("%s: couldn't find node for EMC driver\n", __func__);
	523
	524	init.name = "emc";
	525	init.ops = &tegra_clk_emc_ops;
2dcabf05	526	init.flags = CLK_IS_CRITICAL;
2db04f16 MP	527	init.parent_names = emc_parent_clk_names;
	528	init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
	529
	530	tegra->hw.init = &init;
	531
	532	clk = clk_register(NULL, &tegra->hw);
	533	if (IS_ERR(clk))
	534	return clk;
	535
5cdb1dc5 SB	536	tegra->prev_parent = clk_hw_get_parent_by_index(
5cdb1dc5 SB	537	&tegra->hw, emc_get_parent(&tegra->hw))->clk;
2db04f16 MP	538	tegra->changing_timing = false;
	539
	540	/* Allow debugging tools to see the EMC clock */
	541	clk_register_clkdev(clk, "emc", "tegra-clk-debug");
	542
2db04f16 MP	543	return clk;
2db04f16 MP	544	};