]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/clk/tegra/clk-tegra-periph.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[mirror_ubuntu-focal-kernel.git] / drivers / clk / tegra / clk-tegra-periph.c
CommitLineData
76ebc134
PDS		 1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
76ebc134
PDS		 18#include <linux/clk-provider.h>
19#include <linux/clkdev.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define CLK_SOURCE_I2S0 0x1d8
30#define CLK_SOURCE_I2S1 0x100
31#define CLK_SOURCE_I2S2 0x104
32#define CLK_SOURCE_NDFLASH 0x160
33#define CLK_SOURCE_I2S3 0x3bc
34#define CLK_SOURCE_I2S4 0x3c0
35#define CLK_SOURCE_SPDIF_OUT 0x108
36#define CLK_SOURCE_SPDIF_IN 0x10c
37#define CLK_SOURCE_PWM 0x110
38#define CLK_SOURCE_ADX 0x638
3b34d821 39#define CLK_SOURCE_ADX1 0x670
76ebc134 40#define CLK_SOURCE_AMX 0x63c
3b34d821 41#define CLK_SOURCE_AMX1 0x674
76ebc134
PDS		 42#define CLK_SOURCE_HDA 0x428
43#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
44#define CLK_SOURCE_SBC1 0x134
45#define CLK_SOURCE_SBC2 0x118
46#define CLK_SOURCE_SBC3 0x11c
47#define CLK_SOURCE_SBC4 0x1b4
48#define CLK_SOURCE_SBC5 0x3c8
49#define CLK_SOURCE_SBC6 0x3cc
50#define CLK_SOURCE_SATA_OOB 0x420
51#define CLK_SOURCE_SATA 0x424
52#define CLK_SOURCE_NDSPEED 0x3f8
53#define CLK_SOURCE_VFIR 0x168
54#define CLK_SOURCE_SDMMC1 0x150
55#define CLK_SOURCE_SDMMC2 0x154
56#define CLK_SOURCE_SDMMC3 0x1bc
57#define CLK_SOURCE_SDMMC4 0x164
58#define CLK_SOURCE_CVE 0x140
59#define CLK_SOURCE_TVO 0x188
60#define CLK_SOURCE_TVDAC 0x194
61#define CLK_SOURCE_VDE 0x1c8
62#define CLK_SOURCE_CSITE 0x1d4
63#define CLK_SOURCE_LA 0x1f8
64#define CLK_SOURCE_TRACE 0x634
65#define CLK_SOURCE_OWR 0x1cc
66#define CLK_SOURCE_NOR 0x1d0
67#define CLK_SOURCE_MIPI 0x174
68#define CLK_SOURCE_I2C1 0x124
69#define CLK_SOURCE_I2C2 0x198
70#define CLK_SOURCE_I2C3 0x1b8
71#define CLK_SOURCE_I2C4 0x3c4
72#define CLK_SOURCE_I2C5 0x128
3b34d821 73#define CLK_SOURCE_I2C6 0x65c
76ebc134
PDS		 74#define CLK_SOURCE_UARTA 0x178
75#define CLK_SOURCE_UARTB 0x17c
76#define CLK_SOURCE_UARTC 0x1a0
77#define CLK_SOURCE_UARTD 0x1c0
78#define CLK_SOURCE_UARTE 0x1c4
79#define CLK_SOURCE_3D 0x158
80#define CLK_SOURCE_2D 0x15c
81#define CLK_SOURCE_MPE 0x170
3b34d821 82#define CLK_SOURCE_UARTE 0x1c4
76ebc134
PDS		 83#define CLK_SOURCE_VI_SENSOR 0x1a8
84#define CLK_SOURCE_VI 0x148
85#define CLK_SOURCE_EPP 0x16c
86#define CLK_SOURCE_MSENC 0x1f0
87#define CLK_SOURCE_TSEC 0x1f4
88#define CLK_SOURCE_HOST1X 0x180
89#define CLK_SOURCE_HDMI 0x18c
90#define CLK_SOURCE_DISP1 0x138
91#define CLK_SOURCE_DISP2 0x13c
92#define CLK_SOURCE_CILAB 0x614
93#define CLK_SOURCE_CILCD 0x618
94#define CLK_SOURCE_CILE 0x61c
95#define CLK_SOURCE_DSIALP 0x620
96#define CLK_SOURCE_DSIBLP 0x624
97#define CLK_SOURCE_TSENSOR 0x3b8
98#define CLK_SOURCE_D_AUDIO 0x3d0
99#define CLK_SOURCE_DAM0 0x3d8
100#define CLK_SOURCE_DAM1 0x3dc
101#define CLK_SOURCE_DAM2 0x3e0
102#define CLK_SOURCE_ACTMON 0x3e8
103#define CLK_SOURCE_EXTERN1 0x3ec
104#define CLK_SOURCE_EXTERN2 0x3f0
105#define CLK_SOURCE_EXTERN3 0x3f4
106#define CLK_SOURCE_I2CSLOW 0x3fc
107#define CLK_SOURCE_SE 0x42c
108#define CLK_SOURCE_MSELECT 0x3b4
109#define CLK_SOURCE_DFLL_REF 0x62c
110#define CLK_SOURCE_DFLL_SOC 0x630
111#define CLK_SOURCE_SOC_THERM 0x644
112#define CLK_SOURCE_XUSB_HOST_SRC 0x600
113#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
114#define CLK_SOURCE_XUSB_FS_SRC 0x608
115#define CLK_SOURCE_XUSB_SS_SRC 0x610
116#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
3b34d821
PDS		 117#define CLK_SOURCE_ISP 0x144
118#define CLK_SOURCE_SOR0 0x414
119#define CLK_SOURCE_DPAUX 0x418
120#define CLK_SOURCE_SATA_OOB 0x420
121#define CLK_SOURCE_SATA 0x424
122#define CLK_SOURCE_ENTROPY 0x628
123#define CLK_SOURCE_VI_SENSOR2 0x658
124#define CLK_SOURCE_HDMI_AUDIO 0x668
125#define CLK_SOURCE_VIC03 0x678
126#define CLK_SOURCE_CLK72MHZ 0x66c
dc37fec4
RK		 127#define CLK_SOURCE_DBGAPB 0x718
128#define CLK_SOURCE_NVENC 0x6a0
129#define CLK_SOURCE_NVDEC 0x698
130#define CLK_SOURCE_NVJPG 0x69c
131#define CLK_SOURCE_APE 0x6c0
132#define CLK_SOURCE_SOR1 0x410
133#define CLK_SOURCE_SDMMC_LEGACY 0x694
134#define CLK_SOURCE_QSPI 0x6c4
135#define CLK_SOURCE_VI_I2C 0x6c8
136#define CLK_SOURCE_MIPIBIF 0x660
137#define CLK_SOURCE_UARTAPE 0x710
138#define CLK_SOURCE_TSECB 0x6d8
139#define CLK_SOURCE_MAUD 0x6d4
140#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
6cfc8bc9
PDS		 141#define CLK_SOURCE_DMIC1 0x64c
142#define CLK_SOURCE_DMIC2 0x650
143#define CLK_SOURCE_DMIC3 0x6bc
76ebc134
PDS		 144
145#define MASK(x) (BIT(x) - 1)
146
147#define MUX(_name, _parents, _offset, \
148 _clk_num, _gate_flags, _clk_id) \
149 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
150 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
bc44275b
PDS		 151 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
152 NULL)
76ebc134
PDS		 153
154#define MUX_FLAGS(_name, _parents, _offset,\
155 _clk_num, _gate_flags, _clk_id, flags)\
156 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
157 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
bc44275b
PDS		 158 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
159 NULL)
76ebc134
PDS		 160
161#define MUX8(_name, _parents, _offset, \
162 _clk_num, _gate_flags, _clk_id) \
163 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
164 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
bc44275b
PDS		 165 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
166 NULL)
76ebc134 167
b29f9e92
PDS		 168#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \
169 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
170 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
171 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
172 _parents##_idx, 0, _lock)
173
34ac2c27
PDS		 174#define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \
175 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
176 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
177 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
178 _parents##_idx, 0, NULL)
179
76ebc134
PDS		 180#define INT(_name, _parents, _offset, \
181 _clk_num, _gate_flags, _clk_id) \
182 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
183 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
184 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 185 _clk_id, _parents##_idx, 0, NULL)
76ebc134
PDS		 186
187#define INT_FLAGS(_name, _parents, _offset,\
188 _clk_num, _gate_flags, _clk_id, flags)\
189 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
190 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
191 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 192 _clk_id, _parents##_idx, flags, NULL)
76ebc134
PDS		 193
194#define INT8(_name, _parents, _offset,\
195 _clk_num, _gate_flags, _clk_id) \
196 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
197 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
198 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 199 _clk_id, _parents##_idx, 0, NULL)
76ebc134
PDS		 200
201#define UART(_name, _parents, _offset,\
202 _clk_num, _clk_id) \
203 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
204 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
205 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
bc44275b 206 _parents##_idx, 0, NULL)
76ebc134 207
dc37fec4
RK		 208#define UART8(_name, _parents, _offset,\
209 _clk_num, _clk_id) \
210 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
211 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
212 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
213 _parents##_idx, 0, NULL)
214
76ebc134
PDS		 215#define I2C(_name, _parents, _offset,\
216 _clk_num, _clk_id) \
217 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
218 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
82c875ca
AF		 219 _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
220 _parents##_idx, 0, NULL)
76ebc134
PDS		 221
222#define XUSB(_name, _parents, _offset, \
223 _clk_num, _gate_flags, _clk_id) \
224 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
225 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
226 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
bc44275b 227 _clk_id, _parents##_idx, 0, NULL)
76ebc134
PDS		 228
229#define AUDIO(_name, _offset, _clk_num,\
230 _gate_flags, _clk_id) \
231 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
232 _offset, 16, 0xE01F, 0, 0, 8, 1, \
233 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
bc44275b 234 _clk_id, mux_d_audio_clk_idx, 0, NULL)
76ebc134
PDS		 235
236#define NODIV(_name, _parents, _offset, \
237 _mux_shift, _mux_mask, _clk_num, \
bc44275b 238 _gate_flags, _clk_id, _lock) \
76ebc134
PDS		 239 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
240 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
241 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
bc44275b 242 _clk_id, _parents##_idx, 0, _lock)
76ebc134
PDS		 243
244#define GATE(_name, _parent_name, \
245 _clk_num, _gate_flags, _clk_id, _flags) \
246 { \
247 .name = _name, \
248 .clk_id = _clk_id, \
249 .p.parent_name = _parent_name, \
250 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
f081c896 251 _clk_num, _gate_flags, NULL, NULL), \
76ebc134
PDS		 252 .flags = _flags \
253 }
254
dc37fec4
RK		 255#define DIV8(_name, _parent_name, _offset, _clk_id, _flags) \
256 { \
257 .name = _name, \
258 .clk_id = _clk_id, \
259 .p.parent_name = _parent_name, \
260 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1, \
261 TEGRA_DIVIDER_ROUND_UP, 0, 0, \
262 NULL, NULL), \
263 .offset = _offset, \
264 .flags = _flags, \
265 }
266
76ebc134
PDS		 267#define PLLP_BASE 0xa0
268#define PLLP_MISC 0xac
dc37fec4 269#define PLLP_MISC1 0x680
76ebc134
PDS		 270#define PLLP_OUTA 0xa4
271#define PLLP_OUTB 0xa8
3b34d821 272#define PLLP_OUTC 0x67c
76ebc134
PDS		 273
274#define PLL_BASE_LOCK BIT(27)
275#define PLL_MISC_LOCK_ENABLE 18
276
277static DEFINE_SPINLOCK(PLLP_OUTA_lock);
278static DEFINE_SPINLOCK(PLLP_OUTB_lock);
3b34d821
PDS		 279static DEFINE_SPINLOCK(PLLP_OUTC_lock);
280static DEFINE_SPINLOCK(sor0_lock);
dc37fec4 281static DEFINE_SPINLOCK(sor1_lock);
76ebc134
PDS		 282
283#define MUX_I2S_SPDIF(_id) \
284static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
285 #_id, "pll_p",\
286 "clk_m"};
287MUX_I2S_SPDIF(audio0)
288MUX_I2S_SPDIF(audio1)
289MUX_I2S_SPDIF(audio2)
290MUX_I2S_SPDIF(audio3)
291MUX_I2S_SPDIF(audio4)
292MUX_I2S_SPDIF(audio)
293
294#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
295#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
296#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
297#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
298#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
299#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
300
301static const char *mux_pllp_pllc_pllm_clkm[] = {
302 "pll_p", "pll_c", "pll_m", "clk_m"
303};
304#define mux_pllp_pllc_pllm_clkm_idx NULL
305
306static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
307#define mux_pllp_pllc_pllm_idx NULL
308
309static const char *mux_pllp_pllc_clk32_clkm[] = {
310 "pll_p", "pll_c", "clk_32k", "clk_m"
311};
312#define mux_pllp_pllc_clk32_clkm_idx NULL
313
314static const char *mux_plla_pllc_pllp_clkm[] = {
315 "pll_a_out0", "pll_c", "pll_p", "clk_m"
316};
317#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
318
319static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
320 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
321};
322static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
323 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
324};
325
326static const char *mux_pllp_clkm[] = {
327 "pll_p", "clk_m"
328};
329static u32 mux_pllp_clkm_idx[] = {
330 [0] = 0, [1] = 3,
331};
332
dc37fec4
RK		 333static const char *mux_pllp_clkm_2[] = {
334 "pll_p", "clk_m"
335};
336static u32 mux_pllp_clkm_2_idx[] = {
337 [0] = 2, [1] = 6,
338};
339
340static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
341 "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
342};
343static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
344 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
345};
346
347static const char *
348mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
349 "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
350 "pll_a_out0", "pll_c4_out0"
351};
352static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
353 [0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
354};
355
356static const char *mux_pllc_pllp_plla[] = {
357 "pll_c", "pll_p", "pll_a_out0"
358};
359static u32 mux_pllc_pllp_plla_idx[] = {
360 [0] = 1, [1] = 2, [2] = 3,
361};
362
363static const char *mux_clkm_pllc_pllp_plla[] = {
364 "clk_m", "pll_c", "pll_p", "pll_a_out0"
365};
366#define mux_clkm_pllc_pllp_plla_idx NULL
367
368static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
369 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
370};
371static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
372 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
373};
374
375static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
376 "pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
377};
378static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
379 [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
380};
381
382static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
383 "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
384};
385#define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
386 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
387
388static const char *
389mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
390 "pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
391 "pll_c4_out2", "clk_m"
392};
393#define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
394
76ebc134
PDS		 395static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
396 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
397};
398#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
399
400static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
401 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
402 "pll_d2_out0", "clk_m"
403};
404#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
405
406static const char *mux_pllm_pllc_pllp_plla[] = {
407 "pll_m", "pll_c", "pll_p", "pll_a_out0"
408};
409#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
410
411static const char *mux_pllp_pllc_clkm[] = {
dc37fec4 412 "pll_p", "pll_c", "clk_m"
76ebc134
PDS		 413};
414static u32 mux_pllp_pllc_clkm_idx[] = {
415 [0] = 0, [1] = 1, [2] = 3,
416};
417
dc37fec4
RK		 418static const char *mux_pllp_pllc_clkm_1[] = {
419 "pll_p", "pll_c", "clk_m"
420};
421static u32 mux_pllp_pllc_clkm_1_idx[] = {
422 [0] = 0, [1] = 2, [2] = 5,
423};
424
425static const char *mux_pllp_pllc_plla_clkm[] = {
426 "pll_p", "pll_c", "pll_a_out0", "clk_m"
427};
428static u32 mux_pllp_pllc_plla_clkm_idx[] = {
429 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
430};
431
432static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
433 "pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
434};
435static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
436 [0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
437};
438
439static const char *
440mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
441 "pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
442 "clk_m", "pll_c4_out0"
443};
444static u32
445mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
446 [0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
447};
448
449static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
450 "pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
451};
452static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
453 [0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
454};
455
456static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
457 "pll_p",
458 "pll_c4_out2", "pll_c4_out0", /* LJ input */
459 "pll_c4_out2", "pll_c4_out1",
460 "pll_c4_out1", /* LJ input */
461 "clk_m", "pll_c4_out0"
462};
463#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
464
465static const char *mux_pllp_pllc2_c_c3_clkm[] = {
466 "pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
467};
468static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
469 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
470};
471
472static const char *mux_pllp_clkm_clk32_plle[] = {
473 "pll_p", "clk_m", "clk_32k", "pll_e"
474};
475static u32 mux_pllp_clkm_clk32_plle_idx[] = {
476 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
477};
478
479static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
480 "pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
481};
482#define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
483
484static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
485 "pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
486 "pll_c4_out2"
487};
488static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
489 [0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
490};
491
492static const char *mux_clkm_pllp_pllre[] = {
493 "clk_m", "pll_p_out_xusb", "pll_re_out"
494};
495static u32 mux_clkm_pllp_pllre_idx[] = {
496 [0] = 0, [1] = 1, [2] = 5,
497};
498
76ebc134
PDS		 499static const char *mux_pllp_pllc_clkm_clk32[] = {
500 "pll_p", "pll_c", "clk_m", "clk_32k"
501};
502#define mux_pllp_pllc_clkm_clk32_idx NULL
503
504static const char *mux_plla_clk32_pllp_clkm_plle[] = {
505 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
506};
507#define mux_plla_clk32_pllp_clkm_plle_idx NULL
508
509static const char *mux_clkm_pllp_pllc_pllre[] = {
510 "clk_m", "pll_p", "pll_c", "pll_re_out"
511};
512static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
513 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
514};
515
516static const char *mux_clkm_48M_pllp_480M[] = {
517 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
518};
9d61707b
JL		 519static u32 mux_clkm_48M_pllp_480M_idx[] = {
520 [0] = 0, [1] = 2, [2] = 4, [3] = 6,
521};
76ebc134 522
dc37fec4
RK		 523static const char *mux_clkm_pllre_clk32_480M[] = {
524 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
525};
526#define mux_clkm_pllre_clk32_480M_idx NULL
527
76ebc134
PDS		 528static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
529 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
530};
531static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
532 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
533};
534
dc37fec4
RK		 535static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
536 "pll_p_out3", "pll_p", "pll_c", "clk_m"
537};
538static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
539 [0] = 0, [1] = 1, [2] = 2, [3] = 6,
540};
541
542static const char *mux_ss_div2_60M[] = {
5c992afc
AB		 543 "xusb_ss_div2", "pll_u_60M"
544};
dc37fec4
RK		 545#define mux_ss_div2_60M_idx NULL
546
547static const char *mux_ss_div2_60M_ss[] = {
548 "xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
549};
550#define mux_ss_div2_60M_ss_idx NULL
551
552static const char *mux_ss_clkm[] = {
553 "xusb_ss_src", "clk_m"
554};
555#define mux_ss_clkm_idx NULL
5c992afc 556
76ebc134
PDS		 557static const char *mux_d_audio_clk[] = {
558 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
559 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
560};
561static u32 mux_d_audio_clk_idx[] = {
562 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
563 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
564};
565
566static const char *mux_pllp_plld_pllc_clkm[] = {
567 "pll_p", "pll_d_out0", "pll_c", "clk_m"
568};
569#define mux_pllp_plld_pllc_clkm_idx NULL
3b34d821
PDS		 570static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
571 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
572};
573static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
574 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
575};
576
577static const char *mux_pllp_clkm1[] = {
578 "pll_p", "clk_m",
579};
580#define mux_pllp_clkm1_idx NULL
581
582static const char *mux_pllp3_pllc_clkm[] = {
583 "pll_p_out3", "pll_c", "pll_c2", "clk_m",
584};
585#define mux_pllp3_pllc_clkm_idx NULL
586
587static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
588 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
589};
a9952a76 590#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
3b34d821
PDS		 591
592static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
593 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
594};
595static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
596 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
597};
598
dc37fec4
RK		 599/* SOR1 mux'es */
600static const char *mux_pllp_plld_plld2_clkm[] = {
601 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
602};
603static u32 mux_pllp_plld_plld2_clkm_idx[] = {
604 [0] = 0, [1] = 2, [2] = 5, [3] = 6
605};
606
c1273af4
TR		 607static const char *mux_sor_safe_sor1_brick_sor1_src[] = {
608 /*
609 * Bit 0 of the mux selects sor1_brick, irrespective of bit 1, so the
610 * sor1_brick parent appears twice in the list below. This is merely
611 * to support clk_get_parent() if firmware happened to set these bits
612 * to 0b11. While not an invalid setting, code should always set the
613 * bits to 0b01 to select sor1_brick.
614 */
615 "sor_safe", "sor1_brick", "sor1_src", "sor1_brick"
616};
617#define mux_sor_safe_sor1_brick_sor1_src_idx NULL
dc37fec4
RK		 618
619static const char *mux_pllp_pllre_clkm[] = {
620 "pll_p", "pll_re_out1", "clk_m"
621};
622
623static u32 mux_pllp_pllre_clkm_idx[] = {
624 [0] = 0, [1] = 2, [2] = 3,
625};
626
3b34d821
PDS		 627static const char *mux_clkm_plldp_sor0lvds[] = {
628 "clk_m", "pll_dp", "sor0_lvds",
629};
630#define mux_clkm_plldp_sor0lvds_idx NULL
76ebc134 631
6cfc8bc9
PDS		 632static const char * const mux_dmic1[] = {
633 "pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m"
634};
635#define mux_dmic1_idx NULL
636
637static const char * const mux_dmic2[] = {
638 "pll_a_out0", "dmic2_sync_clk", "pll_p", "clk_m"
639};
640#define mux_dmic2_idx NULL
641
642static const char * const mux_dmic3[] = {
643 "pll_a_out0", "dmic3_sync_clk", "pll_p", "clk_m"
644};
645#define mux_dmic3_idx NULL
646
76ebc134
PDS		 647static struct tegra_periph_init_data periph_clks[] = {
648 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
649 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
650 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
651 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
652 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
653 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
654 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
655 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
656 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
dc37fec4 657 I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
76ebc134
PDS		 658 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
659 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
660 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
661 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
662 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
663 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
664 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
665 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
666 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
3b34d821 667 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
dc37fec4 668 INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
76ebc134
PDS		 669 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
670 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
671 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
dc37fec4 672 INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
76ebc134 673 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
dc37fec4 674 INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
76ebc134 675 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
dc37fec4 676 INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
76ebc134
PDS		 677 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
678 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
3b34d821 679 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
dc37fec4 680 INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
76ebc134
PDS		 681 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
682 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
683 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
684 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
685 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
686 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
687 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
688 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
dc37fec4 689 MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
76ebc134
PDS		 690 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
691 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
692 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
693 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
dc37fec4 694 MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
76ebc134 695 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
dc37fec4 696 MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
76ebc134 697 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
18abd163
AB		 698 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
699 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
700 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
701 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
dc37fec4
RK		 702 MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
703 MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
704 MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
705 MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
76ebc134
PDS		 706 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
707 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
708 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
dc37fec4 709 MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
76ebc134
PDS		 710 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
711 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
712 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
dc37fec4 713 MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
76ebc134
PDS		 714 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
715 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
716 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
717 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
718 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
719 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
720 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
721 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
722 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
723 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
724 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
725 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
726 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
727 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
728 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
729 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
730 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
731 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
732 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
733 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
734 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
735 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
dc37fec4 736 MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
76ebc134 737 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
dc37fec4 738 MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
3b34d821
PDS		 739 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
740 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
167d5366 741 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
dc37fec4 742 MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
18abd163
AB		 743 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
744 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
745 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
746 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
76ebc134
PDS		 747 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
748 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
749 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
750 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
751 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
752 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
dc37fec4
RK		 753 MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
754 MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
755 MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
756 MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
76ebc134
PDS		 757 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
758 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
759 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
760 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
761 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
762 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
763 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
dc37fec4 764 MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
167d5366 765 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
3b34d821 766 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
34ac2c27 767 MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9),
3b34d821 768 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
dc37fec4 769 MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
3b34d821
PDS		 770 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
771 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
dc37fec4 772 MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
3b34d821 773 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
76ebc134 774 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
dc37fec4 775 MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
bc44275b 776 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
dc37fec4 777 NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
bc44275b 778 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
dc37fec4 779 NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
3b34d821 780 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
76ebc134
PDS		 781 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
782 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
783 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
784 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
2edf3e03 785 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
dc37fec4
RK		 786 UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
787 UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
788 UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
789 UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
76ebc134 790 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
dc37fec4 791 XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
76ebc134 792 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
dc37fec4 793 XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
76ebc134
PDS		 794 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
795 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
dc37fec4
RK		 796 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
797 NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
798 NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
799 NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
76ebc134 800 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
dc37fec4
RK		 801 XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
802 MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
736971be 803 MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
dc37fec4
RK		 804 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
805 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
806 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
807 MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
c1273af4 808 NODIV("sor1", mux_sor_safe_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 14, MASK(2), 183, 0, tegra_clk_sor1, &sor1_lock),
dc37fec4
RK		 809 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
810 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
21e49032 811 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
dc37fec4
RK		 812 MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
813 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
814 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
815 MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
6cfc8bc9
PDS		 816 MUX8("dmic1", mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1),
817 MUX8("dmic2", mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2),
818 MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3),
76ebc134
PDS		 819};
820
821static struct tegra_periph_init_data gate_clks[] = {
822 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
28580386 823 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
76ebc134
PDS		 824 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
825 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
826 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
827 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
828 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
829 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
830 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
831 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
832 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
833 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
834 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
07314fc1 835 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
76ebc134
PDS		 836 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
837 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
838 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
839 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
e7a49675 840 GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
76ebc134
PDS		 841 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
842 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
843 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
844 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
845 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
846 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
847 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
76ebc134
PDS		 848 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
849 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
34ac2c27
PDS		 850 GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
851 GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
3b34d821
PDS		 852 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
853 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
3b34d821 854 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
dc37fec4
RK		 855 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
856 GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
857 GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
858 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
859 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
860 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
29569941 861 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
bfa34832 862 GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
88da44c5
PDS		 863 GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
864 GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
865 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
866 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
867 GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
868 GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
dc37fec4
RK		 869};
870
871static struct tegra_periph_init_data div_clks[] = {
872 DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
76ebc134
PDS		 873};
874
875struct pll_out_data {
876 char *div_name;
877 char *pll_out_name;
878 u32 offset;
879 int clk_id;
880 u8 div_shift;
881 u8 div_flags;
882 u8 rst_shift;
883 spinlock_t *lock;
884};
885
886#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
887 {\
888 .div_name = "pll_p_out" #_num "_div",\
889 .pll_out_name = "pll_p_out" #_num,\
890 .offset = _offset,\
891 .div_shift = _div_shift,\
892 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
893 TEGRA_DIVIDER_ROUND_UP,\
894 .rst_shift = _rst_shift,\
895 .clk_id = tegra_clk_ ## _id,\
896 .lock = &_offset ##_lock,\
897 }
898
899static struct pll_out_data pllp_out_clks[] = {
900 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
901 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
902 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
903 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
904 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
3b34d821 905 PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
76ebc134
PDS		 906};
907
908static void __init periph_clk_init(void __iomem *clk_base,
909 struct tegra_clk *tegra_clks)
910{
911 int i;
912 struct clk *clk;
913 struct clk **dt_clk;
914
915 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
7e14f223 916 const struct tegra_clk_periph_regs *bank;
76ebc134
PDS		 917 struct tegra_periph_init_data *data;
918
919 data = periph_clks + i;
920
921 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
922 if (!dt_clk)
923 continue;
924
925 bank = get_reg_bank(data->periph.gate.clk_num);
926 if (!bank)
927 continue;
928
929 data->periph.gate.regs = bank;
930 clk = tegra_clk_register_periph(data->name,
931 data->p.parent_names, data->num_parents,
932 &data->periph, clk_base, data->offset,
933 data->flags);
934 *dt_clk = clk;
935 }
936}
937
938static void __init gate_clk_init(void __iomem *clk_base,
939 struct tegra_clk *tegra_clks)
940{
941 int i;
942 struct clk *clk;
943 struct clk **dt_clk;
944
945 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
946 struct tegra_periph_init_data *data;
947
948 data = gate_clks + i;
949
950 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
951 if (!dt_clk)
952 continue;
953
954 clk = tegra_clk_register_periph_gate(data->name,
955 data->p.parent_name, data->periph.gate.flags,
956 clk_base, data->flags,
957 data->periph.gate.clk_num,
958 periph_clk_enb_refcnt);
959 *dt_clk = clk;
960 }
961}
962
dc37fec4
RK		 963static void __init div_clk_init(void __iomem *clk_base,
964 struct tegra_clk *tegra_clks)
965{
966 int i;
967 struct clk *clk;
968 struct clk **dt_clk;
969
970 for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
971 struct tegra_periph_init_data *data;
972
973 data = div_clks + i;
974
975 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
976 if (!dt_clk)
977 continue;
978
979 clk = tegra_clk_register_divider(data->name,
980 data->p.parent_name, clk_base + data->offset,
981 data->flags, data->periph.divider.flags,
982 data->periph.divider.shift,
983 data->periph.divider.width,
984 data->periph.divider.frac_width,
985 data->periph.divider.lock);
986 *dt_clk = clk;
987 }
988}
989
76ebc134
PDS		 990static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
991 struct tegra_clk *tegra_clks,
992 struct tegra_clk_pll_params *pll_params)
993{
994 struct clk *clk;
995 struct clk **dt_clk;
996 int i;
997
998 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
999 if (dt_clk) {
1000 /* PLLP */
1001 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
1002 pmc_base, 0, pll_params, NULL);
1003 clk_register_clkdev(clk, "pll_p", NULL);
1004 *dt_clk = clk;
1005 }
1006
1007 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
1008 struct pll_out_data *data;
1009
1010 data = pllp_out_clks + i;
1011
1012 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
1013 if (!dt_clk)
1014 continue;
1015
1016 clk = tegra_clk_register_divider(data->div_name, "pll_p",
1017 clk_base + data->offset, 0, data->div_flags,
1018 data->div_shift, 8, 1, data->lock);
1019 clk = tegra_clk_register_pll_out(data->pll_out_name,
1020 data->div_name, clk_base + data->offset,
1021 data->rst_shift + 1, data->rst_shift,
1022 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1023 data->lock);
1024 *dt_clk = clk;
1025 }
dc37fec4
RK		 1026
1027 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
1028 tegra_clks);
1029 if (dt_clk) {
1030 /*
1031 * Tegra210 has control on enabling/disabling PLLP branches to
1032 * CPU, register a gate clock "pll_p_out_cpu" for this gating
1033 * function and parent "pll_p_out4" to it, so when we are
1034 * re-parenting CPU off from "pll_p_out4" the PLLP branching to
1035 * CPU can be disabled automatically.
1036 */
1037 clk = tegra_clk_register_divider("pll_p_out4_div",
1038 "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
1039 8, 1, &PLLP_OUTB_lock);
1040
1041 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
1042 if (dt_clk) {
1043 clk = tegra_clk_register_pll_out("pll_p_out4",
1044 "pll_p_out4_div", clk_base + PLLP_OUTB,
1045 17, 16, CLK_IGNORE_UNUSED |
1046 CLK_SET_RATE_PARENT, 0,
1047 &PLLP_OUTB_lock);
1048 *dt_clk = clk;
1049 }
1050 }
1051
1052 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
1053 if (dt_clk) {
1054 /* PLLP_OUT_HSIO */
1055 clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
1056 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1057 clk_base + PLLP_MISC1, 29, 0, NULL);
1058 *dt_clk = clk;
1059 }
1060
1061 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
1062 if (dt_clk) {
1063 /* PLLP_OUT_XUSB */
1064 clk = clk_register_gate(NULL, "pll_p_out_xusb",
1065 "pll_p_out_hsio", CLK_SET_RATE_PARENT |
1066 CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
1067 NULL);
1068 clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
1069 *dt_clk = clk;
1070 }
76ebc134
PDS		 1071}
1072
1073void __init tegra_periph_clk_init(void __iomem *clk_base,
1074 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
1075 struct tegra_clk_pll_params *pll_params)
1076{
1077 init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
1078 periph_clk_init(clk_base, tegra_clks);
1079 gate_clk_init(clk_base, tegra_clks);
dc37fec4 1080 div_clk_init(clk_base, tegra_clks);
76ebc134 1081}
Ubuntu Focal Linux kernel mirror