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37c26a90 PG |
1 | /* |
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/clk-provider.h> | |
20 | #include <linux/clkdev.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/clk/tegra.h> | |
4a2e3279 | 24 | #include <linux/delay.h> |
37c26a90 PG |
25 | |
26 | #include "clk.h" | |
27 | ||
37c26a90 PG |
28 | #define OSC_CTRL 0x50 |
29 | #define OSC_CTRL_OSC_FREQ_MASK (3<<30) | |
30 | #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) | |
31 | #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) | |
32 | #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) | |
33 | #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) | |
34 | #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) | |
35 | ||
36 | #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) | |
37 | #define OSC_CTRL_PLL_REF_DIV_1 (0<<28) | |
38 | #define OSC_CTRL_PLL_REF_DIV_2 (1<<28) | |
39 | #define OSC_CTRL_PLL_REF_DIV_4 (2<<28) | |
40 | ||
41 | #define OSC_FREQ_DET 0x58 | |
42 | #define OSC_FREQ_DET_TRIG (1<<31) | |
43 | ||
44 | #define OSC_FREQ_DET_STATUS 0x5c | |
45 | #define OSC_FREQ_DET_BUSY (1<<31) | |
46 | #define OSC_FREQ_DET_CNT_MASK 0xFFFF | |
47 | ||
d5ff89a8 PDS |
48 | #define TEGRA20_CLK_PERIPH_BANKS 3 |
49 | ||
37c26a90 PG |
50 | #define PLLS_BASE 0xf0 |
51 | #define PLLS_MISC 0xf4 | |
52 | #define PLLC_BASE 0x80 | |
53 | #define PLLC_MISC 0x8c | |
54 | #define PLLM_BASE 0x90 | |
55 | #define PLLM_MISC 0x9c | |
56 | #define PLLP_BASE 0xa0 | |
57 | #define PLLP_MISC 0xac | |
58 | #define PLLA_BASE 0xb0 | |
59 | #define PLLA_MISC 0xbc | |
60 | #define PLLU_BASE 0xc0 | |
61 | #define PLLU_MISC 0xcc | |
62 | #define PLLD_BASE 0xd0 | |
63 | #define PLLD_MISC 0xdc | |
64 | #define PLLX_BASE 0xe0 | |
65 | #define PLLX_MISC 0xe4 | |
66 | #define PLLE_BASE 0xe8 | |
67 | #define PLLE_MISC 0xec | |
68 | ||
3e72771e PDS |
69 | #define PLL_BASE_LOCK BIT(27) |
70 | #define PLLE_MISC_LOCK BIT(11) | |
37c26a90 PG |
71 | |
72 | #define PLL_MISC_LOCK_ENABLE 18 | |
73 | #define PLLDU_MISC_LOCK_ENABLE 22 | |
74 | #define PLLE_MISC_LOCK_ENABLE 9 | |
75 | ||
76 | #define PLLC_OUT 0x84 | |
77 | #define PLLM_OUT 0x94 | |
78 | #define PLLP_OUTA 0xa4 | |
79 | #define PLLP_OUTB 0xa8 | |
80 | #define PLLA_OUT 0xb4 | |
81 | ||
82 | #define CCLK_BURST_POLICY 0x20 | |
83 | #define SUPER_CCLK_DIVIDER 0x24 | |
84 | #define SCLK_BURST_POLICY 0x28 | |
85 | #define SUPER_SCLK_DIVIDER 0x2c | |
86 | #define CLK_SYSTEM_RATE 0x30 | |
87 | ||
4a2e3279 JL |
88 | #define CCLK_BURST_POLICY_SHIFT 28 |
89 | #define CCLK_RUN_POLICY_SHIFT 4 | |
90 | #define CCLK_IDLE_POLICY_SHIFT 0 | |
91 | #define CCLK_IDLE_POLICY 1 | |
92 | #define CCLK_RUN_POLICY 2 | |
93 | #define CCLK_BURST_POLICY_PLLX 8 | |
94 | ||
37c26a90 PG |
95 | #define CLK_SOURCE_I2S1 0x100 |
96 | #define CLK_SOURCE_I2S2 0x104 | |
97 | #define CLK_SOURCE_SPDIF_OUT 0x108 | |
98 | #define CLK_SOURCE_SPDIF_IN 0x10c | |
99 | #define CLK_SOURCE_PWM 0x110 | |
100 | #define CLK_SOURCE_SPI 0x114 | |
101 | #define CLK_SOURCE_SBC1 0x134 | |
102 | #define CLK_SOURCE_SBC2 0x118 | |
103 | #define CLK_SOURCE_SBC3 0x11c | |
104 | #define CLK_SOURCE_SBC4 0x1b4 | |
105 | #define CLK_SOURCE_XIO 0x120 | |
106 | #define CLK_SOURCE_TWC 0x12c | |
107 | #define CLK_SOURCE_IDE 0x144 | |
108 | #define CLK_SOURCE_NDFLASH 0x160 | |
109 | #define CLK_SOURCE_VFIR 0x168 | |
110 | #define CLK_SOURCE_SDMMC1 0x150 | |
111 | #define CLK_SOURCE_SDMMC2 0x154 | |
112 | #define CLK_SOURCE_SDMMC3 0x1bc | |
113 | #define CLK_SOURCE_SDMMC4 0x164 | |
114 | #define CLK_SOURCE_CVE 0x140 | |
115 | #define CLK_SOURCE_TVO 0x188 | |
116 | #define CLK_SOURCE_TVDAC 0x194 | |
117 | #define CLK_SOURCE_HDMI 0x18c | |
118 | #define CLK_SOURCE_DISP1 0x138 | |
119 | #define CLK_SOURCE_DISP2 0x13c | |
120 | #define CLK_SOURCE_CSITE 0x1d4 | |
121 | #define CLK_SOURCE_LA 0x1f8 | |
122 | #define CLK_SOURCE_OWR 0x1cc | |
123 | #define CLK_SOURCE_NOR 0x1d0 | |
124 | #define CLK_SOURCE_MIPI 0x174 | |
125 | #define CLK_SOURCE_I2C1 0x124 | |
126 | #define CLK_SOURCE_I2C2 0x198 | |
127 | #define CLK_SOURCE_I2C3 0x1b8 | |
128 | #define CLK_SOURCE_DVC 0x128 | |
129 | #define CLK_SOURCE_UARTA 0x178 | |
130 | #define CLK_SOURCE_UARTB 0x17c | |
131 | #define CLK_SOURCE_UARTC 0x1a0 | |
132 | #define CLK_SOURCE_UARTD 0x1c0 | |
133 | #define CLK_SOURCE_UARTE 0x1c4 | |
134 | #define CLK_SOURCE_3D 0x158 | |
135 | #define CLK_SOURCE_2D 0x15c | |
136 | #define CLK_SOURCE_MPE 0x170 | |
137 | #define CLK_SOURCE_EPP 0x16c | |
138 | #define CLK_SOURCE_HOST1X 0x180 | |
139 | #define CLK_SOURCE_VDE 0x1c8 | |
140 | #define CLK_SOURCE_VI 0x148 | |
141 | #define CLK_SOURCE_VI_SENSOR 0x1a8 | |
142 | #define CLK_SOURCE_EMC 0x19c | |
143 | ||
144 | #define AUDIO_SYNC_CLK 0x38 | |
145 | ||
146 | #define PMC_CTRL 0x0 | |
147 | #define PMC_CTRL_BLINK_ENB 7 | |
148 | #define PMC_DPD_PADS_ORIDE 0x1c | |
149 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 | |
150 | #define PMC_BLINK_TIMER 0x40 | |
151 | ||
152 | /* Tegra CPU clock and reset control regs */ | |
153 | #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c | |
154 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 | |
155 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 | |
156 | ||
157 | #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) | |
158 | #define CPU_RESET(cpu) (0x1111ul << (cpu)) | |
159 | ||
4a2e3279 JL |
160 | #ifdef CONFIG_PM_SLEEP |
161 | static struct cpu_clk_suspend_context { | |
162 | u32 pllx_misc; | |
163 | u32 pllx_base; | |
164 | ||
165 | u32 cpu_burst; | |
166 | u32 clk_csite_src; | |
167 | u32 cclk_divider; | |
168 | } tegra20_cpu_clk_sctx; | |
169 | #endif | |
170 | ||
37c26a90 PG |
171 | static void __iomem *clk_base; |
172 | static void __iomem *pmc_base; | |
173 | ||
174 | static DEFINE_SPINLOCK(pll_div_lock); | |
d076a206 | 175 | static DEFINE_SPINLOCK(sysrate_lock); |
37c26a90 PG |
176 | |
177 | #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ | |
d5ff89a8 | 178 | _clk_num, _gate_flags, _clk_id) \ |
37c26a90 PG |
179 | TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ |
180 | 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ | |
343a607c | 181 | _clk_num, \ |
37c26a90 PG |
182 | _gate_flags, _clk_id) |
183 | ||
184 | #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ | |
d5ff89a8 | 185 | _clk_num, _gate_flags, _clk_id) \ |
37c26a90 | 186 | TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ |
d5ff89a8 | 187 | 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, \ |
343a607c | 188 | _clk_num, _gate_flags, \ |
37c26a90 PG |
189 | _clk_id) |
190 | ||
191 | #define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ | |
d5ff89a8 | 192 | _clk_num, _gate_flags, _clk_id) \ |
37c26a90 | 193 | TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ |
d5ff89a8 | 194 | 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ |
343a607c | 195 | _clk_num, _gate_flags, \ |
37c26a90 PG |
196 | _clk_id) |
197 | ||
198 | #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ | |
d5ff89a8 | 199 | _mux_shift, _mux_width, _clk_num, \ |
37c26a90 PG |
200 | _gate_flags, _clk_id) \ |
201 | TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ | |
d5ff89a8 | 202 | _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ |
343a607c | 203 | _clk_num, _gate_flags, \ |
37c26a90 PG |
204 | _clk_id) |
205 | ||
206 | /* IDs assigned here must be in sync with DT bindings definition | |
207 | * for Tegra20 clocks . | |
208 | */ | |
209 | enum tegra20_clk { | |
210 | cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, | |
211 | ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp, | |
212 | gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma, | |
213 | kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3, | |
214 | dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, | |
215 | usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, | |
216 | pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb, | |
82ce7421 | 217 | iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1, |
37c26a90 PG |
218 | uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve, |
219 | osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0, | |
220 | pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1, | |
0203d912 SW |
221 | pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u, |
222 | pll_x, cop, audio, pll_ref, twd, clk_max, | |
37c26a90 PG |
223 | }; |
224 | ||
343a607c | 225 | static struct clk **clks; |
37c26a90 PG |
226 | |
227 | static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { | |
dba4072a PDS |
228 | { 12000000, 600000000, 600, 12, 0, 8 }, |
229 | { 13000000, 600000000, 600, 13, 0, 8 }, | |
230 | { 19200000, 600000000, 500, 16, 0, 6 }, | |
231 | { 26000000, 600000000, 600, 26, 0, 8 }, | |
37c26a90 PG |
232 | { 0, 0, 0, 0, 0, 0 }, |
233 | }; | |
234 | ||
235 | static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { | |
dba4072a PDS |
236 | { 12000000, 666000000, 666, 12, 0, 8}, |
237 | { 13000000, 666000000, 666, 13, 0, 8}, | |
238 | { 19200000, 666000000, 555, 16, 0, 8}, | |
239 | { 26000000, 666000000, 666, 26, 0, 8}, | |
240 | { 12000000, 600000000, 600, 12, 0, 8}, | |
241 | { 13000000, 600000000, 600, 13, 0, 8}, | |
242 | { 19200000, 600000000, 375, 12, 0, 6}, | |
243 | { 26000000, 600000000, 600, 26, 0, 8}, | |
37c26a90 PG |
244 | { 0, 0, 0, 0, 0, 0 }, |
245 | }; | |
246 | ||
247 | static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { | |
dba4072a PDS |
248 | { 12000000, 216000000, 432, 12, 1, 8}, |
249 | { 13000000, 216000000, 432, 13, 1, 8}, | |
250 | { 19200000, 216000000, 90, 4, 1, 1}, | |
251 | { 26000000, 216000000, 432, 26, 1, 8}, | |
252 | { 12000000, 432000000, 432, 12, 0, 8}, | |
253 | { 13000000, 432000000, 432, 13, 0, 8}, | |
254 | { 19200000, 432000000, 90, 4, 0, 1}, | |
255 | { 26000000, 432000000, 432, 26, 0, 8}, | |
37c26a90 PG |
256 | { 0, 0, 0, 0, 0, 0 }, |
257 | }; | |
258 | ||
259 | static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { | |
dba4072a PDS |
260 | { 28800000, 56448000, 49, 25, 0, 1}, |
261 | { 28800000, 73728000, 64, 25, 0, 1}, | |
262 | { 28800000, 24000000, 5, 6, 0, 1}, | |
37c26a90 PG |
263 | { 0, 0, 0, 0, 0, 0 }, |
264 | }; | |
265 | ||
266 | static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { | |
dba4072a PDS |
267 | { 12000000, 216000000, 216, 12, 0, 4}, |
268 | { 13000000, 216000000, 216, 13, 0, 4}, | |
269 | { 19200000, 216000000, 135, 12, 0, 3}, | |
270 | { 26000000, 216000000, 216, 26, 0, 4}, | |
37c26a90 | 271 | |
dba4072a PDS |
272 | { 12000000, 594000000, 594, 12, 0, 8}, |
273 | { 13000000, 594000000, 594, 13, 0, 8}, | |
274 | { 19200000, 594000000, 495, 16, 0, 8}, | |
275 | { 26000000, 594000000, 594, 26, 0, 8}, | |
37c26a90 | 276 | |
dba4072a PDS |
277 | { 12000000, 1000000000, 1000, 12, 0, 12}, |
278 | { 13000000, 1000000000, 1000, 13, 0, 12}, | |
279 | { 19200000, 1000000000, 625, 12, 0, 8}, | |
280 | { 26000000, 1000000000, 1000, 26, 0, 12}, | |
37c26a90 PG |
281 | |
282 | { 0, 0, 0, 0, 0, 0 }, | |
283 | }; | |
284 | ||
285 | static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { | |
dba4072a PDS |
286 | { 12000000, 480000000, 960, 12, 0, 0}, |
287 | { 13000000, 480000000, 960, 13, 0, 0}, | |
288 | { 19200000, 480000000, 200, 4, 0, 0}, | |
289 | { 26000000, 480000000, 960, 26, 0, 0}, | |
37c26a90 PG |
290 | { 0, 0, 0, 0, 0, 0 }, |
291 | }; | |
292 | ||
293 | static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { | |
294 | /* 1 GHz */ | |
dba4072a PDS |
295 | { 12000000, 1000000000, 1000, 12, 0, 12}, |
296 | { 13000000, 1000000000, 1000, 13, 0, 12}, | |
297 | { 19200000, 1000000000, 625, 12, 0, 8}, | |
298 | { 26000000, 1000000000, 1000, 26, 0, 12}, | |
37c26a90 PG |
299 | |
300 | /* 912 MHz */ | |
dba4072a PDS |
301 | { 12000000, 912000000, 912, 12, 0, 12}, |
302 | { 13000000, 912000000, 912, 13, 0, 12}, | |
303 | { 19200000, 912000000, 760, 16, 0, 8}, | |
304 | { 26000000, 912000000, 912, 26, 0, 12}, | |
37c26a90 PG |
305 | |
306 | /* 816 MHz */ | |
dba4072a PDS |
307 | { 12000000, 816000000, 816, 12, 0, 12}, |
308 | { 13000000, 816000000, 816, 13, 0, 12}, | |
309 | { 19200000, 816000000, 680, 16, 0, 8}, | |
310 | { 26000000, 816000000, 816, 26, 0, 12}, | |
37c26a90 PG |
311 | |
312 | /* 760 MHz */ | |
dba4072a PDS |
313 | { 12000000, 760000000, 760, 12, 0, 12}, |
314 | { 13000000, 760000000, 760, 13, 0, 12}, | |
315 | { 19200000, 760000000, 950, 24, 0, 8}, | |
316 | { 26000000, 760000000, 760, 26, 0, 12}, | |
37c26a90 PG |
317 | |
318 | /* 750 MHz */ | |
dba4072a PDS |
319 | { 12000000, 750000000, 750, 12, 0, 12}, |
320 | { 13000000, 750000000, 750, 13, 0, 12}, | |
321 | { 19200000, 750000000, 625, 16, 0, 8}, | |
322 | { 26000000, 750000000, 750, 26, 0, 12}, | |
37c26a90 PG |
323 | |
324 | /* 608 MHz */ | |
dba4072a PDS |
325 | { 12000000, 608000000, 608, 12, 0, 12}, |
326 | { 13000000, 608000000, 608, 13, 0, 12}, | |
327 | { 19200000, 608000000, 380, 12, 0, 8}, | |
328 | { 26000000, 608000000, 608, 26, 0, 12}, | |
37c26a90 PG |
329 | |
330 | /* 456 MHz */ | |
dba4072a PDS |
331 | { 12000000, 456000000, 456, 12, 0, 12}, |
332 | { 13000000, 456000000, 456, 13, 0, 12}, | |
333 | { 19200000, 456000000, 380, 16, 0, 8}, | |
334 | { 26000000, 456000000, 456, 26, 0, 12}, | |
37c26a90 PG |
335 | |
336 | /* 312 MHz */ | |
dba4072a PDS |
337 | { 12000000, 312000000, 312, 12, 0, 12}, |
338 | { 13000000, 312000000, 312, 13, 0, 12}, | |
339 | { 19200000, 312000000, 260, 16, 0, 8}, | |
340 | { 26000000, 312000000, 312, 26, 0, 12}, | |
37c26a90 PG |
341 | |
342 | { 0, 0, 0, 0, 0, 0 }, | |
343 | }; | |
344 | ||
345 | static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { | |
dba4072a | 346 | { 12000000, 100000000, 200, 24, 0, 0 }, |
37c26a90 PG |
347 | { 0, 0, 0, 0, 0, 0 }, |
348 | }; | |
349 | ||
350 | /* PLL parameters */ | |
351 | static struct tegra_clk_pll_params pll_c_params = { | |
352 | .input_min = 2000000, | |
353 | .input_max = 31000000, | |
354 | .cf_min = 1000000, | |
355 | .cf_max = 6000000, | |
356 | .vco_min = 20000000, | |
357 | .vco_max = 1400000000, | |
358 | .base_reg = PLLC_BASE, | |
359 | .misc_reg = PLLC_MISC, | |
3e72771e | 360 | .lock_mask = PLL_BASE_LOCK, |
37c26a90 PG |
361 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
362 | .lock_delay = 300, | |
ebe142b2 PDS |
363 | .freq_table = pll_c_freq_table, |
364 | .flags = TEGRA_PLL_HAS_CPCON, | |
37c26a90 PG |
365 | }; |
366 | ||
367 | static struct tegra_clk_pll_params pll_m_params = { | |
368 | .input_min = 2000000, | |
369 | .input_max = 31000000, | |
370 | .cf_min = 1000000, | |
371 | .cf_max = 6000000, | |
372 | .vco_min = 20000000, | |
373 | .vco_max = 1200000000, | |
374 | .base_reg = PLLM_BASE, | |
375 | .misc_reg = PLLM_MISC, | |
3e72771e | 376 | .lock_mask = PLL_BASE_LOCK, |
37c26a90 PG |
377 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
378 | .lock_delay = 300, | |
ebe142b2 PDS |
379 | .freq_table = pll_m_freq_table, |
380 | .flags = TEGRA_PLL_HAS_CPCON, | |
37c26a90 PG |
381 | }; |
382 | ||
383 | static struct tegra_clk_pll_params pll_p_params = { | |
384 | .input_min = 2000000, | |
385 | .input_max = 31000000, | |
386 | .cf_min = 1000000, | |
387 | .cf_max = 6000000, | |
388 | .vco_min = 20000000, | |
389 | .vco_max = 1400000000, | |
390 | .base_reg = PLLP_BASE, | |
391 | .misc_reg = PLLP_MISC, | |
3e72771e | 392 | .lock_mask = PLL_BASE_LOCK, |
37c26a90 PG |
393 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
394 | .lock_delay = 300, | |
ebe142b2 PDS |
395 | .freq_table = pll_p_freq_table, |
396 | .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON, | |
397 | .fixed_rate = 216000000, | |
37c26a90 PG |
398 | }; |
399 | ||
400 | static struct tegra_clk_pll_params pll_a_params = { | |
401 | .input_min = 2000000, | |
402 | .input_max = 31000000, | |
403 | .cf_min = 1000000, | |
404 | .cf_max = 6000000, | |
405 | .vco_min = 20000000, | |
406 | .vco_max = 1400000000, | |
407 | .base_reg = PLLA_BASE, | |
408 | .misc_reg = PLLA_MISC, | |
3e72771e | 409 | .lock_mask = PLL_BASE_LOCK, |
37c26a90 PG |
410 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
411 | .lock_delay = 300, | |
ebe142b2 PDS |
412 | .freq_table = pll_a_freq_table, |
413 | .flags = TEGRA_PLL_HAS_CPCON, | |
37c26a90 PG |
414 | }; |
415 | ||
416 | static struct tegra_clk_pll_params pll_d_params = { | |
417 | .input_min = 2000000, | |
418 | .input_max = 40000000, | |
419 | .cf_min = 1000000, | |
420 | .cf_max = 6000000, | |
421 | .vco_min = 40000000, | |
422 | .vco_max = 1000000000, | |
423 | .base_reg = PLLD_BASE, | |
424 | .misc_reg = PLLD_MISC, | |
3e72771e | 425 | .lock_mask = PLL_BASE_LOCK, |
37c26a90 PG |
426 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, |
427 | .lock_delay = 1000, | |
ebe142b2 PDS |
428 | .freq_table = pll_d_freq_table, |
429 | .flags = TEGRA_PLL_HAS_CPCON, | |
37c26a90 PG |
430 | }; |
431 | ||
0b6525ac PDS |
432 | static struct pdiv_map pllu_p[] = { |
433 | { .pdiv = 1, .hw_val = 1 }, | |
434 | { .pdiv = 2, .hw_val = 0 }, | |
435 | { .pdiv = 0, .hw_val = 0 }, | |
436 | }; | |
437 | ||
37c26a90 PG |
438 | static struct tegra_clk_pll_params pll_u_params = { |
439 | .input_min = 2000000, | |
440 | .input_max = 40000000, | |
441 | .cf_min = 1000000, | |
442 | .cf_max = 6000000, | |
443 | .vco_min = 48000000, | |
444 | .vco_max = 960000000, | |
445 | .base_reg = PLLU_BASE, | |
446 | .misc_reg = PLLU_MISC, | |
3e72771e | 447 | .lock_mask = PLL_BASE_LOCK, |
37c26a90 PG |
448 | .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, |
449 | .lock_delay = 1000, | |
0b6525ac | 450 | .pdiv_tohw = pllu_p, |
ebe142b2 PDS |
451 | .freq_table = pll_u_freq_table, |
452 | .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, | |
37c26a90 PG |
453 | }; |
454 | ||
455 | static struct tegra_clk_pll_params pll_x_params = { | |
456 | .input_min = 2000000, | |
457 | .input_max = 31000000, | |
458 | .cf_min = 1000000, | |
459 | .cf_max = 6000000, | |
460 | .vco_min = 20000000, | |
461 | .vco_max = 1200000000, | |
462 | .base_reg = PLLX_BASE, | |
463 | .misc_reg = PLLX_MISC, | |
3e72771e | 464 | .lock_mask = PLL_BASE_LOCK, |
37c26a90 PG |
465 | .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, |
466 | .lock_delay = 300, | |
ebe142b2 PDS |
467 | .freq_table = pll_x_freq_table, |
468 | .flags = TEGRA_PLL_HAS_CPCON, | |
37c26a90 PG |
469 | }; |
470 | ||
471 | static struct tegra_clk_pll_params pll_e_params = { | |
472 | .input_min = 12000000, | |
473 | .input_max = 12000000, | |
474 | .cf_min = 0, | |
475 | .cf_max = 0, | |
476 | .vco_min = 0, | |
477 | .vco_max = 0, | |
478 | .base_reg = PLLE_BASE, | |
479 | .misc_reg = PLLE_MISC, | |
3e72771e | 480 | .lock_mask = PLLE_MISC_LOCK, |
37c26a90 PG |
481 | .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, |
482 | .lock_delay = 0, | |
ebe142b2 PDS |
483 | .freq_table = pll_e_freq_table, |
484 | .flags = TEGRA_PLL_FIXED, | |
485 | .fixed_rate = 100000000, | |
37c26a90 PG |
486 | }; |
487 | ||
37c26a90 PG |
488 | static unsigned long tegra20_clk_measure_input_freq(void) |
489 | { | |
490 | u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); | |
491 | u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; | |
492 | u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; | |
493 | unsigned long input_freq; | |
494 | ||
495 | switch (auto_clk_control) { | |
496 | case OSC_CTRL_OSC_FREQ_12MHZ: | |
497 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
498 | input_freq = 12000000; | |
499 | break; | |
500 | case OSC_CTRL_OSC_FREQ_13MHZ: | |
501 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
502 | input_freq = 13000000; | |
503 | break; | |
504 | case OSC_CTRL_OSC_FREQ_19_2MHZ: | |
505 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
506 | input_freq = 19200000; | |
507 | break; | |
508 | case OSC_CTRL_OSC_FREQ_26MHZ: | |
509 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
510 | input_freq = 26000000; | |
511 | break; | |
512 | default: | |
513 | pr_err("Unexpected clock autodetect value %d", | |
514 | auto_clk_control); | |
515 | BUG(); | |
516 | return 0; | |
517 | } | |
518 | ||
519 | return input_freq; | |
520 | } | |
521 | ||
522 | static unsigned int tegra20_get_pll_ref_div(void) | |
523 | { | |
524 | u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & | |
525 | OSC_CTRL_PLL_REF_DIV_MASK; | |
526 | ||
527 | switch (pll_ref_div) { | |
528 | case OSC_CTRL_PLL_REF_DIV_1: | |
529 | return 1; | |
530 | case OSC_CTRL_PLL_REF_DIV_2: | |
531 | return 2; | |
532 | case OSC_CTRL_PLL_REF_DIV_4: | |
533 | return 4; | |
534 | default: | |
535 | pr_err("Invalied pll ref divider %d\n", pll_ref_div); | |
536 | BUG(); | |
537 | } | |
538 | return 0; | |
539 | } | |
540 | ||
541 | static void tegra20_pll_init(void) | |
542 | { | |
543 | struct clk *clk; | |
544 | ||
545 | /* PLLC */ | |
546 | clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, | |
ebe142b2 | 547 | &pll_c_params, NULL); |
37c26a90 PG |
548 | clk_register_clkdev(clk, "pll_c", NULL); |
549 | clks[pll_c] = clk; | |
550 | ||
551 | /* PLLC_OUT1 */ | |
552 | clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", | |
553 | clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
554 | 8, 8, 1, NULL); | |
555 | clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", | |
556 | clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, | |
557 | 0, NULL); | |
558 | clk_register_clkdev(clk, "pll_c_out1", NULL); | |
559 | clks[pll_c_out1] = clk; | |
560 | ||
561 | /* PLLP */ | |
562 | clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0, | |
ebe142b2 | 563 | &pll_p_params, NULL); |
37c26a90 PG |
564 | clk_register_clkdev(clk, "pll_p", NULL); |
565 | clks[pll_p] = clk; | |
566 | ||
567 | /* PLLP_OUT1 */ | |
568 | clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", | |
569 | clk_base + PLLP_OUTA, 0, | |
570 | TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, | |
571 | 8, 8, 1, &pll_div_lock); | |
572 | clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", | |
573 | clk_base + PLLP_OUTA, 1, 0, | |
574 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
575 | &pll_div_lock); | |
576 | clk_register_clkdev(clk, "pll_p_out1", NULL); | |
577 | clks[pll_p_out1] = clk; | |
578 | ||
579 | /* PLLP_OUT2 */ | |
580 | clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", | |
581 | clk_base + PLLP_OUTA, 0, | |
582 | TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, | |
583 | 24, 8, 1, &pll_div_lock); | |
584 | clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", | |
585 | clk_base + PLLP_OUTA, 17, 16, | |
586 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
587 | &pll_div_lock); | |
588 | clk_register_clkdev(clk, "pll_p_out2", NULL); | |
589 | clks[pll_p_out2] = clk; | |
590 | ||
591 | /* PLLP_OUT3 */ | |
592 | clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", | |
593 | clk_base + PLLP_OUTB, 0, | |
594 | TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, | |
595 | 8, 8, 1, &pll_div_lock); | |
596 | clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", | |
597 | clk_base + PLLP_OUTB, 1, 0, | |
598 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
599 | &pll_div_lock); | |
600 | clk_register_clkdev(clk, "pll_p_out3", NULL); | |
601 | clks[pll_p_out3] = clk; | |
602 | ||
603 | /* PLLP_OUT4 */ | |
604 | clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", | |
605 | clk_base + PLLP_OUTB, 0, | |
606 | TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP, | |
607 | 24, 8, 1, &pll_div_lock); | |
608 | clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", | |
609 | clk_base + PLLP_OUTB, 17, 16, | |
610 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, | |
611 | &pll_div_lock); | |
612 | clk_register_clkdev(clk, "pll_p_out4", NULL); | |
613 | clks[pll_p_out4] = clk; | |
614 | ||
615 | /* PLLM */ | |
616 | clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, | |
ebe142b2 PDS |
617 | CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, |
618 | &pll_m_params, NULL); | |
37c26a90 PG |
619 | clk_register_clkdev(clk, "pll_m", NULL); |
620 | clks[pll_m] = clk; | |
621 | ||
622 | /* PLLM_OUT1 */ | |
623 | clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", | |
624 | clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
625 | 8, 8, 1, NULL); | |
626 | clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", | |
627 | clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | | |
628 | CLK_SET_RATE_PARENT, 0, NULL); | |
629 | clk_register_clkdev(clk, "pll_m_out1", NULL); | |
630 | clks[pll_m_out1] = clk; | |
631 | ||
632 | /* PLLX */ | |
633 | clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, | |
ebe142b2 | 634 | &pll_x_params, NULL); |
37c26a90 PG |
635 | clk_register_clkdev(clk, "pll_x", NULL); |
636 | clks[pll_x] = clk; | |
637 | ||
638 | /* PLLU */ | |
639 | clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, | |
ebe142b2 | 640 | &pll_u_params, NULL); |
37c26a90 PG |
641 | clk_register_clkdev(clk, "pll_u", NULL); |
642 | clks[pll_u] = clk; | |
643 | ||
644 | /* PLLD */ | |
645 | clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, | |
ebe142b2 | 646 | &pll_d_params, NULL); |
37c26a90 PG |
647 | clk_register_clkdev(clk, "pll_d", NULL); |
648 | clks[pll_d] = clk; | |
649 | ||
650 | /* PLLD_OUT0 */ | |
651 | clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", | |
652 | CLK_SET_RATE_PARENT, 1, 2); | |
653 | clk_register_clkdev(clk, "pll_d_out0", NULL); | |
654 | clks[pll_d_out0] = clk; | |
655 | ||
656 | /* PLLA */ | |
657 | clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, | |
ebe142b2 | 658 | &pll_a_params, NULL); |
37c26a90 PG |
659 | clk_register_clkdev(clk, "pll_a", NULL); |
660 | clks[pll_a] = clk; | |
661 | ||
662 | /* PLLA_OUT0 */ | |
663 | clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", | |
664 | clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, | |
665 | 8, 8, 1, NULL); | |
666 | clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", | |
667 | clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | | |
668 | CLK_SET_RATE_PARENT, 0, NULL); | |
669 | clk_register_clkdev(clk, "pll_a_out0", NULL); | |
670 | clks[pll_a_out0] = clk; | |
671 | ||
672 | /* PLLE */ | |
0f1bc12e | 673 | clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, |
ebe142b2 | 674 | 0, &pll_e_params, NULL); |
37c26a90 PG |
675 | clk_register_clkdev(clk, "pll_e", NULL); |
676 | clks[pll_e] = clk; | |
677 | } | |
678 | ||
679 | static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", | |
bf161d21 PDS |
680 | "pll_p", "pll_p_out4", |
681 | "pll_p_out3", "clk_d", "pll_x" }; | |
37c26a90 PG |
682 | static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", |
683 | "pll_p_out3", "pll_p_out2", "clk_d", | |
684 | "clk_32k", "pll_m_out1" }; | |
685 | ||
686 | static void tegra20_super_clk_init(void) | |
687 | { | |
688 | struct clk *clk; | |
689 | ||
37c26a90 PG |
690 | /* CCLK */ |
691 | clk = tegra_clk_register_super_mux("cclk", cclk_parents, | |
692 | ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, | |
693 | clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); | |
694 | clk_register_clkdev(clk, "cclk", NULL); | |
695 | clks[cclk] = clk; | |
696 | ||
697 | /* SCLK */ | |
698 | clk = tegra_clk_register_super_mux("sclk", sclk_parents, | |
699 | ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, | |
700 | clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); | |
701 | clk_register_clkdev(clk, "sclk", NULL); | |
702 | clks[sclk] = clk; | |
703 | ||
704 | /* HCLK */ | |
705 | clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, | |
d076a206 PDS |
706 | clk_base + CLK_SYSTEM_RATE, 4, 2, 0, |
707 | &sysrate_lock); | |
37c26a90 PG |
708 | clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, |
709 | clk_base + CLK_SYSTEM_RATE, 7, | |
d076a206 | 710 | CLK_GATE_SET_TO_DISABLE, &sysrate_lock); |
37c26a90 PG |
711 | clk_register_clkdev(clk, "hclk", NULL); |
712 | clks[hclk] = clk; | |
713 | ||
714 | /* PCLK */ | |
715 | clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, | |
d076a206 PDS |
716 | clk_base + CLK_SYSTEM_RATE, 0, 2, 0, |
717 | &sysrate_lock); | |
37c26a90 PG |
718 | clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, |
719 | clk_base + CLK_SYSTEM_RATE, 3, | |
d076a206 | 720 | CLK_GATE_SET_TO_DISABLE, &sysrate_lock); |
37c26a90 PG |
721 | clk_register_clkdev(clk, "pclk", NULL); |
722 | clks[pclk] = clk; | |
723 | ||
724 | /* twd */ | |
725 | clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); | |
726 | clk_register_clkdev(clk, "twd", NULL); | |
727 | clks[twd] = clk; | |
728 | } | |
729 | ||
730 | static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", | |
731 | "pll_a_out0", "unused", "unused", | |
732 | "unused"}; | |
733 | ||
734 | static void __init tegra20_audio_clk_init(void) | |
735 | { | |
736 | struct clk *clk; | |
737 | ||
738 | /* audio */ | |
739 | clk = clk_register_mux(NULL, "audio_mux", audio_parents, | |
819c1de3 JH |
740 | ARRAY_SIZE(audio_parents), |
741 | CLK_SET_RATE_NO_REPARENT, | |
37c26a90 PG |
742 | clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); |
743 | clk = clk_register_gate(NULL, "audio", "audio_mux", 0, | |
744 | clk_base + AUDIO_SYNC_CLK, 4, | |
745 | CLK_GATE_SET_TO_DISABLE, NULL); | |
746 | clk_register_clkdev(clk, "audio", NULL); | |
747 | clks[audio] = clk; | |
748 | ||
749 | /* audio_2x */ | |
750 | clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", | |
751 | CLK_SET_RATE_PARENT, 2, 1); | |
752 | clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", | |
753 | TEGRA_PERIPH_NO_RESET, clk_base, | |
d5ff89a8 | 754 | CLK_SET_RATE_PARENT, 89, |
37c26a90 PG |
755 | periph_clk_enb_refcnt); |
756 | clk_register_clkdev(clk, "audio_2x", NULL); | |
757 | clks[audio_2x] = clk; | |
758 | ||
759 | } | |
760 | ||
761 | static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p", | |
762 | "clk_m"}; | |
763 | static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", | |
764 | "clk_m"}; | |
765 | static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p", | |
766 | "clk_m"}; | |
767 | static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"}; | |
768 | static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", | |
769 | "clk_32k"}; | |
770 | static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; | |
771 | static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"}; | |
772 | static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", | |
773 | "clk_m"}; | |
774 | static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; | |
775 | ||
776 | static struct tegra_periph_init_data tegra_periph_clk_list[] = { | |
d5ff89a8 PDS |
777 | TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, i2s1), |
778 | TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, i2s2), | |
779 | TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, spdif_out), | |
780 | TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, spdif_in), | |
781 | TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, sbc1), | |
782 | TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, sbc2), | |
783 | TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, sbc3), | |
784 | TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, sbc4), | |
785 | TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, spi), | |
786 | TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, xio), | |
787 | TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, twc), | |
788 | TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, ide), | |
789 | TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, 0, ndflash), | |
790 | TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, vfir), | |
791 | TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, 0, csite), | |
792 | TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, 0, la), | |
793 | TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, owr), | |
794 | TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, mipi), | |
795 | TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, 0, vde), | |
796 | TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, 0, vi), | |
797 | TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, 0, epp), | |
798 | TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, 0, mpe), | |
799 | TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, 0, host1x), | |
800 | TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, TEGRA_PERIPH_MANUAL_RESET, gr3d), | |
801 | TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, 0, gr2d), | |
802 | TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, 0, nor), | |
803 | TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, 0, sdmmc1), | |
804 | TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, 0, sdmmc2), | |
805 | TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, 0, sdmmc3), | |
806 | TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, 0, sdmmc4), | |
807 | TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, 0, cve), | |
808 | TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, 0, tvo), | |
809 | TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, 0, tvdac), | |
810 | TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, vi_sensor), | |
811 | TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, i2c1), | |
812 | TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, i2c2), | |
813 | TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3), | |
814 | TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, dvc), | |
815 | TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi), | |
343a607c | 816 | TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, pwm), |
37c26a90 PG |
817 | }; |
818 | ||
819 | static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { | |
d5ff89a8 PDS |
820 | TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, uarta), |
821 | TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, uartb), | |
822 | TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, uartc), | |
823 | TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, uartd), | |
824 | TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, uarte), | |
825 | TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, disp1), | |
826 | TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, disp2), | |
37c26a90 PG |
827 | }; |
828 | ||
829 | static void __init tegra20_periph_clk_init(void) | |
830 | { | |
831 | struct tegra_periph_init_data *data; | |
832 | struct clk *clk; | |
833 | int i; | |
834 | ||
6ec32400 LS |
835 | /* ac97 */ |
836 | clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", | |
837 | TEGRA_PERIPH_ON_APB, | |
d5ff89a8 | 838 | clk_base, 0, 3, periph_clk_enb_refcnt); |
6ec32400 LS |
839 | clk_register_clkdev(clk, NULL, "tegra20-ac97"); |
840 | clks[ac97] = clk; | |
841 | ||
37c26a90 PG |
842 | /* apbdma */ |
843 | clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, | |
d5ff89a8 | 844 | 0, 34, periph_clk_enb_refcnt); |
37c26a90 PG |
845 | clk_register_clkdev(clk, NULL, "tegra-apbdma"); |
846 | clks[apbdma] = clk; | |
847 | ||
848 | /* rtc */ | |
849 | clk = tegra_clk_register_periph_gate("rtc", "clk_32k", | |
850 | TEGRA_PERIPH_NO_RESET, | |
d5ff89a8 | 851 | clk_base, 0, 4, periph_clk_enb_refcnt); |
37c26a90 PG |
852 | clk_register_clkdev(clk, NULL, "rtc-tegra"); |
853 | clks[rtc] = clk; | |
854 | ||
855 | /* timer */ | |
856 | clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, | |
d5ff89a8 | 857 | 0, 5, periph_clk_enb_refcnt); |
37c26a90 PG |
858 | clk_register_clkdev(clk, NULL, "timer"); |
859 | clks[timer] = clk; | |
860 | ||
861 | /* kbc */ | |
862 | clk = tegra_clk_register_periph_gate("kbc", "clk_32k", | |
863 | TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, | |
d5ff89a8 | 864 | clk_base, 0, 36, periph_clk_enb_refcnt); |
37c26a90 PG |
865 | clk_register_clkdev(clk, NULL, "tegra-kbc"); |
866 | clks[kbc] = clk; | |
867 | ||
868 | /* csus */ | |
869 | clk = tegra_clk_register_periph_gate("csus", "clk_m", | |
870 | TEGRA_PERIPH_NO_RESET, | |
d5ff89a8 | 871 | clk_base, 0, 92, periph_clk_enb_refcnt); |
37c26a90 PG |
872 | clk_register_clkdev(clk, "csus", "tengra_camera"); |
873 | clks[csus] = clk; | |
874 | ||
875 | /* vcp */ | |
876 | clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, | |
d5ff89a8 | 877 | clk_base, 0, 29, periph_clk_enb_refcnt); |
37c26a90 PG |
878 | clk_register_clkdev(clk, "vcp", "tegra-avp"); |
879 | clks[vcp] = clk; | |
880 | ||
881 | /* bsea */ | |
882 | clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, | |
d5ff89a8 | 883 | clk_base, 0, 62, periph_clk_enb_refcnt); |
37c26a90 PG |
884 | clk_register_clkdev(clk, "bsea", "tegra-avp"); |
885 | clks[bsea] = clk; | |
886 | ||
887 | /* bsev */ | |
888 | clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, | |
d5ff89a8 | 889 | clk_base, 0, 63, periph_clk_enb_refcnt); |
37c26a90 PG |
890 | clk_register_clkdev(clk, "bsev", "tegra-aes"); |
891 | clks[bsev] = clk; | |
892 | ||
893 | /* emc */ | |
894 | clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, | |
819c1de3 JH |
895 | ARRAY_SIZE(mux_pllmcp_clkm), |
896 | CLK_SET_RATE_NO_REPARENT, | |
37c26a90 PG |
897 | clk_base + CLK_SOURCE_EMC, |
898 | 30, 2, 0, NULL); | |
899 | clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, | |
d5ff89a8 | 900 | 57, periph_clk_enb_refcnt); |
37c26a90 PG |
901 | clk_register_clkdev(clk, "emc", NULL); |
902 | clks[emc] = clk; | |
903 | ||
904 | /* usbd */ | |
905 | clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, | |
d5ff89a8 | 906 | 22, periph_clk_enb_refcnt); |
37c26a90 PG |
907 | clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); |
908 | clks[usbd] = clk; | |
909 | ||
910 | /* usb2 */ | |
911 | clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, | |
d5ff89a8 | 912 | 58, periph_clk_enb_refcnt); |
37c26a90 PG |
913 | clk_register_clkdev(clk, NULL, "tegra-ehci.1"); |
914 | clks[usb2] = clk; | |
915 | ||
916 | /* usb3 */ | |
917 | clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, | |
d5ff89a8 | 918 | 59, periph_clk_enb_refcnt); |
37c26a90 PG |
919 | clk_register_clkdev(clk, NULL, "tegra-ehci.2"); |
920 | clks[usb3] = clk; | |
921 | ||
922 | /* dsi */ | |
923 | clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, | |
d5ff89a8 | 924 | 48, periph_clk_enb_refcnt); |
37c26a90 PG |
925 | clk_register_clkdev(clk, NULL, "dsi"); |
926 | clks[dsi] = clk; | |
927 | ||
928 | /* csi */ | |
929 | clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, | |
d5ff89a8 | 930 | 0, 52, periph_clk_enb_refcnt); |
37c26a90 PG |
931 | clk_register_clkdev(clk, "csi", "tegra_camera"); |
932 | clks[csi] = clk; | |
933 | ||
934 | /* isp */ | |
935 | clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, | |
d5ff89a8 | 936 | periph_clk_enb_refcnt); |
37c26a90 PG |
937 | clk_register_clkdev(clk, "isp", "tegra_camera"); |
938 | clks[isp] = clk; | |
939 | ||
940 | /* pex */ | |
941 | clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, | |
d5ff89a8 | 942 | periph_clk_enb_refcnt); |
37c26a90 PG |
943 | clk_register_clkdev(clk, "pex", NULL); |
944 | clks[pex] = clk; | |
945 | ||
946 | /* afi */ | |
947 | clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, | |
d5ff89a8 | 948 | periph_clk_enb_refcnt); |
37c26a90 PG |
949 | clk_register_clkdev(clk, "afi", NULL); |
950 | clks[afi] = clk; | |
951 | ||
952 | /* pcie_xclk */ | |
953 | clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base, | |
d5ff89a8 | 954 | 0, 74, periph_clk_enb_refcnt); |
37c26a90 PG |
955 | clk_register_clkdev(clk, "pcie_xclk", NULL); |
956 | clks[pcie_xclk] = clk; | |
957 | ||
958 | /* cdev1 */ | |
959 | clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, | |
960 | 26000000); | |
961 | clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, | |
d5ff89a8 | 962 | clk_base, 0, 94, periph_clk_enb_refcnt); |
37c26a90 PG |
963 | clk_register_clkdev(clk, "cdev1", NULL); |
964 | clks[cdev1] = clk; | |
965 | ||
966 | /* cdev2 */ | |
967 | clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, | |
968 | 26000000); | |
969 | clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, | |
d5ff89a8 | 970 | clk_base, 0, 93, periph_clk_enb_refcnt); |
37c26a90 PG |
971 | clk_register_clkdev(clk, "cdev2", NULL); |
972 | clks[cdev2] = clk; | |
973 | ||
974 | for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { | |
975 | data = &tegra_periph_clk_list[i]; | |
976 | clk = tegra_clk_register_periph(data->name, data->parent_names, | |
977 | data->num_parents, &data->periph, | |
a26a0298 | 978 | clk_base, data->offset, data->flags); |
37c26a90 PG |
979 | clk_register_clkdev(clk, data->con_id, data->dev_id); |
980 | clks[data->clk_id] = clk; | |
981 | } | |
982 | ||
983 | for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { | |
984 | data = &tegra_periph_nodiv_clk_list[i]; | |
985 | clk = tegra_clk_register_periph_nodiv(data->name, | |
986 | data->parent_names, | |
987 | data->num_parents, &data->periph, | |
988 | clk_base, data->offset); | |
989 | clk_register_clkdev(clk, data->con_id, data->dev_id); | |
990 | clks[data->clk_id] = clk; | |
991 | } | |
992 | } | |
993 | ||
994 | ||
995 | static void __init tegra20_fixed_clk_init(void) | |
996 | { | |
997 | struct clk *clk; | |
998 | ||
999 | /* clk_32k */ | |
1000 | clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, | |
1001 | 32768); | |
1002 | clk_register_clkdev(clk, "clk_32k", NULL); | |
1003 | clks[clk_32k] = clk; | |
1004 | } | |
1005 | ||
1006 | static void __init tegra20_pmc_clk_init(void) | |
1007 | { | |
1008 | struct clk *clk; | |
1009 | ||
1010 | /* blink */ | |
1011 | writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); | |
1012 | clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, | |
1013 | pmc_base + PMC_DPD_PADS_ORIDE, | |
1014 | PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); | |
1015 | clk = clk_register_gate(NULL, "blink", "blink_override", 0, | |
1016 | pmc_base + PMC_CTRL, | |
1017 | PMC_CTRL_BLINK_ENB, 0, NULL); | |
1018 | clk_register_clkdev(clk, "blink", NULL); | |
1019 | clks[blink] = clk; | |
1020 | } | |
1021 | ||
1022 | static void __init tegra20_osc_clk_init(void) | |
1023 | { | |
1024 | struct clk *clk; | |
1025 | unsigned long input_freq; | |
1026 | unsigned int pll_ref_div; | |
1027 | ||
1028 | input_freq = tegra20_clk_measure_input_freq(); | |
1029 | ||
1030 | /* clk_m */ | |
1031 | clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | | |
1032 | CLK_IGNORE_UNUSED, input_freq); | |
1033 | clk_register_clkdev(clk, "clk_m", NULL); | |
1034 | clks[clk_m] = clk; | |
1035 | ||
1036 | /* pll_ref */ | |
1037 | pll_ref_div = tegra20_get_pll_ref_div(); | |
1038 | clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", | |
1039 | CLK_SET_RATE_PARENT, 1, pll_ref_div); | |
1040 | clk_register_clkdev(clk, "pll_ref", NULL); | |
1041 | clks[pll_ref] = clk; | |
1042 | } | |
1043 | ||
1044 | /* Tegra20 CPU clock and reset control functions */ | |
1045 | static void tegra20_wait_cpu_in_reset(u32 cpu) | |
1046 | { | |
1047 | unsigned int reg; | |
1048 | ||
1049 | do { | |
1050 | reg = readl(clk_base + | |
1051 | TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); | |
1052 | cpu_relax(); | |
1053 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ | |
1054 | ||
1055 | return; | |
1056 | } | |
1057 | ||
1058 | static void tegra20_put_cpu_in_reset(u32 cpu) | |
1059 | { | |
1060 | writel(CPU_RESET(cpu), | |
1061 | clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); | |
1062 | dmb(); | |
1063 | } | |
1064 | ||
1065 | static void tegra20_cpu_out_of_reset(u32 cpu) | |
1066 | { | |
1067 | writel(CPU_RESET(cpu), | |
1068 | clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); | |
1069 | wmb(); | |
1070 | } | |
1071 | ||
1072 | static void tegra20_enable_cpu_clock(u32 cpu) | |
1073 | { | |
1074 | unsigned int reg; | |
1075 | ||
1076 | reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
1077 | writel(reg & ~CPU_CLOCK(cpu), | |
1078 | clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
1079 | barrier(); | |
1080 | reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
1081 | } | |
1082 | ||
1083 | static void tegra20_disable_cpu_clock(u32 cpu) | |
1084 | { | |
1085 | unsigned int reg; | |
1086 | ||
1087 | reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
1088 | writel(reg | CPU_CLOCK(cpu), | |
1089 | clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
1090 | } | |
1091 | ||
4a2e3279 JL |
1092 | #ifdef CONFIG_PM_SLEEP |
1093 | static bool tegra20_cpu_rail_off_ready(void) | |
1094 | { | |
1095 | unsigned int cpu_rst_status; | |
1096 | ||
1097 | cpu_rst_status = readl(clk_base + | |
1098 | TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); | |
1099 | ||
1100 | return !!(cpu_rst_status & 0x2); | |
1101 | } | |
1102 | ||
1103 | static void tegra20_cpu_clock_suspend(void) | |
1104 | { | |
1105 | /* switch coresite to clk_m, save off original source */ | |
1106 | tegra20_cpu_clk_sctx.clk_csite_src = | |
1107 | readl(clk_base + CLK_SOURCE_CSITE); | |
1108 | writel(3<<30, clk_base + CLK_SOURCE_CSITE); | |
1109 | ||
1110 | tegra20_cpu_clk_sctx.cpu_burst = | |
1111 | readl(clk_base + CCLK_BURST_POLICY); | |
1112 | tegra20_cpu_clk_sctx.pllx_base = | |
1113 | readl(clk_base + PLLX_BASE); | |
1114 | tegra20_cpu_clk_sctx.pllx_misc = | |
1115 | readl(clk_base + PLLX_MISC); | |
1116 | tegra20_cpu_clk_sctx.cclk_divider = | |
1117 | readl(clk_base + SUPER_CCLK_DIVIDER); | |
1118 | } | |
1119 | ||
1120 | static void tegra20_cpu_clock_resume(void) | |
1121 | { | |
1122 | unsigned int reg, policy; | |
1123 | ||
1124 | /* Is CPU complex already running on PLLX? */ | |
1125 | reg = readl(clk_base + CCLK_BURST_POLICY); | |
1126 | policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; | |
1127 | ||
1128 | if (policy == CCLK_IDLE_POLICY) | |
1129 | reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; | |
1130 | else if (policy == CCLK_RUN_POLICY) | |
1131 | reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; | |
1132 | else | |
1133 | BUG(); | |
1134 | ||
1135 | if (reg != CCLK_BURST_POLICY_PLLX) { | |
1136 | /* restore PLLX settings if CPU is on different PLL */ | |
1137 | writel(tegra20_cpu_clk_sctx.pllx_misc, | |
1138 | clk_base + PLLX_MISC); | |
1139 | writel(tegra20_cpu_clk_sctx.pllx_base, | |
1140 | clk_base + PLLX_BASE); | |
1141 | ||
1142 | /* wait for PLL stabilization if PLLX was enabled */ | |
1143 | if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) | |
1144 | udelay(300); | |
1145 | } | |
1146 | ||
1147 | /* | |
1148 | * Restore original burst policy setting for calls resulting from CPU | |
1149 | * LP2 in idle or system suspend. | |
1150 | */ | |
1151 | writel(tegra20_cpu_clk_sctx.cclk_divider, | |
1152 | clk_base + SUPER_CCLK_DIVIDER); | |
1153 | writel(tegra20_cpu_clk_sctx.cpu_burst, | |
1154 | clk_base + CCLK_BURST_POLICY); | |
1155 | ||
1156 | writel(tegra20_cpu_clk_sctx.clk_csite_src, | |
1157 | clk_base + CLK_SOURCE_CSITE); | |
1158 | } | |
1159 | #endif | |
1160 | ||
37c26a90 PG |
1161 | static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { |
1162 | .wait_for_reset = tegra20_wait_cpu_in_reset, | |
1163 | .put_in_reset = tegra20_put_cpu_in_reset, | |
1164 | .out_of_reset = tegra20_cpu_out_of_reset, | |
1165 | .enable_clock = tegra20_enable_cpu_clock, | |
1166 | .disable_clock = tegra20_disable_cpu_clock, | |
4a2e3279 JL |
1167 | #ifdef CONFIG_PM_SLEEP |
1168 | .rail_off_ready = tegra20_cpu_rail_off_ready, | |
1169 | .suspend = tegra20_cpu_clock_suspend, | |
1170 | .resume = tegra20_cpu_clock_resume, | |
1171 | #endif | |
37c26a90 PG |
1172 | }; |
1173 | ||
a0be7a9e | 1174 | static struct tegra_clk_init_table init_table[] __initdata = { |
37c26a90 PG |
1175 | {pll_p, clk_max, 216000000, 1}, |
1176 | {pll_p_out1, clk_max, 28800000, 1}, | |
1177 | {pll_p_out2, clk_max, 48000000, 1}, | |
1178 | {pll_p_out3, clk_max, 72000000, 1}, | |
1179 | {pll_p_out4, clk_max, 24000000, 1}, | |
1180 | {pll_c, clk_max, 600000000, 1}, | |
1181 | {pll_c_out1, clk_max, 120000000, 1}, | |
1182 | {sclk, pll_c_out1, 0, 1}, | |
1183 | {hclk, clk_max, 0, 1}, | |
1184 | {pclk, clk_max, 60000000, 1}, | |
1185 | {csite, clk_max, 0, 1}, | |
1186 | {emc, clk_max, 0, 1}, | |
1187 | {cclk, clk_max, 0, 1}, | |
527fad1b LD |
1188 | {uarta, pll_p, 0, 0}, |
1189 | {uartb, pll_p, 0, 0}, | |
1190 | {uartc, pll_p, 0, 0}, | |
1191 | {uartd, pll_p, 0, 0}, | |
1192 | {uarte, pll_p, 0, 0}, | |
37c26a90 PG |
1193 | {pll_a, clk_max, 56448000, 1}, |
1194 | {pll_a_out0, clk_max, 11289600, 1}, | |
1195 | {cdev1, clk_max, 0, 1}, | |
1196 | {blink, clk_max, 32768, 1}, | |
1197 | {i2s1, pll_a_out0, 11289600, 0}, | |
1198 | {i2s2, pll_a_out0, 11289600, 0}, | |
1199 | {sdmmc1, pll_p, 48000000, 0}, | |
1200 | {sdmmc3, pll_p, 48000000, 0}, | |
1201 | {sdmmc4, pll_p, 48000000, 0}, | |
1202 | {spi, pll_p, 20000000, 0}, | |
1203 | {sbc1, pll_p, 100000000, 0}, | |
1204 | {sbc2, pll_p, 100000000, 0}, | |
1205 | {sbc3, pll_p, 100000000, 0}, | |
1206 | {sbc4, pll_p, 100000000, 0}, | |
1207 | {host1x, pll_c, 150000000, 0}, | |
1208 | {disp1, pll_p, 600000000, 0}, | |
1209 | {disp2, pll_p, 600000000, 0}, | |
ce910686 TR |
1210 | {gr2d, pll_c, 300000000, 0}, |
1211 | {gr3d, pll_c, 300000000, 0}, | |
37c26a90 PG |
1212 | {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ |
1213 | }; | |
1214 | ||
441f199a SW |
1215 | static void __init tegra20_clock_apply_init_table(void) |
1216 | { | |
1217 | tegra_init_from_table(init_table, clks, clk_max); | |
1218 | } | |
1219 | ||
37c26a90 PG |
1220 | /* |
1221 | * Some clocks may be used by different drivers depending on the board | |
1222 | * configuration. List those here to register them twice in the clock lookup | |
1223 | * table under two names. | |
1224 | */ | |
1225 | static struct tegra_clk_duplicate tegra_clk_duplicates[] = { | |
37c26a90 PG |
1226 | TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), |
1227 | TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), | |
1228 | TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), | |
37c26a90 | 1229 | TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"), |
37c26a90 PG |
1230 | TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */ |
1231 | }; | |
1232 | ||
1233 | static const struct of_device_id pmc_match[] __initconst = { | |
1234 | { .compatible = "nvidia,tegra20-pmc" }, | |
1235 | {}, | |
1236 | }; | |
1237 | ||
061cec92 | 1238 | static void __init tegra20_clock_init(struct device_node *np) |
37c26a90 | 1239 | { |
37c26a90 PG |
1240 | struct device_node *node; |
1241 | ||
1242 | clk_base = of_iomap(np, 0); | |
1243 | if (!clk_base) { | |
1244 | pr_err("Can't map CAR registers\n"); | |
1245 | BUG(); | |
1246 | } | |
1247 | ||
1248 | node = of_find_matching_node(NULL, pmc_match); | |
1249 | if (!node) { | |
1250 | pr_err("Failed to find pmc node\n"); | |
1251 | BUG(); | |
1252 | } | |
1253 | ||
1254 | pmc_base = of_iomap(node, 0); | |
1255 | if (!pmc_base) { | |
1256 | pr_err("Can't map pmc registers\n"); | |
1257 | BUG(); | |
1258 | } | |
1259 | ||
343a607c PDS |
1260 | clks = tegra_clk_init(clk_max, TEGRA20_CLK_PERIPH_BANKS); |
1261 | if (!clks) | |
d5ff89a8 PDS |
1262 | return; |
1263 | ||
37c26a90 PG |
1264 | tegra20_osc_clk_init(); |
1265 | tegra20_pmc_clk_init(); | |
1266 | tegra20_fixed_clk_init(); | |
1267 | tegra20_pll_init(); | |
1268 | tegra20_super_clk_init(); | |
1269 | tegra20_periph_clk_init(); | |
1270 | tegra20_audio_clk_init(); | |
1271 | ||
37c26a90 PG |
1272 | tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); |
1273 | ||
343a607c | 1274 | tegra_add_of_provider(np); |
37c26a90 | 1275 | |
441f199a | 1276 | tegra_clk_apply_init_table = tegra20_clock_apply_init_table; |
37c26a90 PG |
1277 | |
1278 | tegra_cpu_car_ops = &tegra20_cpu_car_ops; | |
1279 | } | |
061cec92 | 1280 | CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init); |