]>
Commit | Line | Data |
---|---|---|
74807dff TK |
1 | /* |
2 | * OMAP3 Legacy clock data | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments, Inc | |
5 | * Tero Kristo (t-kristo@ti.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/clk-provider.h> | |
19 | #include <linux/clk/ti.h> | |
20 | ||
21 | #include "clock.h" | |
22 | ||
23 | static struct ti_clk_fixed virt_12m_ck_data = { | |
24 | .frequency = 12000000, | |
25 | }; | |
26 | ||
27 | static struct ti_clk virt_12m_ck = { | |
28 | .name = "virt_12m_ck", | |
29 | .type = TI_CLK_FIXED, | |
30 | .data = &virt_12m_ck_data, | |
31 | }; | |
32 | ||
33 | static struct ti_clk_fixed virt_13m_ck_data = { | |
34 | .frequency = 13000000, | |
35 | }; | |
36 | ||
37 | static struct ti_clk virt_13m_ck = { | |
38 | .name = "virt_13m_ck", | |
39 | .type = TI_CLK_FIXED, | |
40 | .data = &virt_13m_ck_data, | |
41 | }; | |
42 | ||
43 | static struct ti_clk_fixed virt_19200000_ck_data = { | |
44 | .frequency = 19200000, | |
45 | }; | |
46 | ||
47 | static struct ti_clk virt_19200000_ck = { | |
48 | .name = "virt_19200000_ck", | |
49 | .type = TI_CLK_FIXED, | |
50 | .data = &virt_19200000_ck_data, | |
51 | }; | |
52 | ||
53 | static struct ti_clk_fixed virt_26000000_ck_data = { | |
54 | .frequency = 26000000, | |
55 | }; | |
56 | ||
57 | static struct ti_clk virt_26000000_ck = { | |
58 | .name = "virt_26000000_ck", | |
59 | .type = TI_CLK_FIXED, | |
60 | .data = &virt_26000000_ck_data, | |
61 | }; | |
62 | ||
63 | static struct ti_clk_fixed virt_38_4m_ck_data = { | |
64 | .frequency = 38400000, | |
65 | }; | |
66 | ||
67 | static struct ti_clk virt_38_4m_ck = { | |
68 | .name = "virt_38_4m_ck", | |
69 | .type = TI_CLK_FIXED, | |
70 | .data = &virt_38_4m_ck_data, | |
71 | }; | |
72 | ||
73 | static struct ti_clk_fixed virt_16_8m_ck_data = { | |
74 | .frequency = 16800000, | |
75 | }; | |
76 | ||
77 | static struct ti_clk virt_16_8m_ck = { | |
78 | .name = "virt_16_8m_ck", | |
79 | .type = TI_CLK_FIXED, | |
80 | .data = &virt_16_8m_ck_data, | |
81 | }; | |
82 | ||
83 | static const char *osc_sys_ck_parents[] = { | |
84 | "virt_12m_ck", | |
85 | "virt_13m_ck", | |
86 | "virt_19200000_ck", | |
87 | "virt_26000000_ck", | |
88 | "virt_38_4m_ck", | |
89 | "virt_16_8m_ck", | |
90 | }; | |
91 | ||
92 | static struct ti_clk_mux osc_sys_ck_data = { | |
93 | .num_parents = ARRAY_SIZE(osc_sys_ck_parents), | |
94 | .reg = 0xd40, | |
95 | .module = TI_CLKM_PRM, | |
96 | .parents = osc_sys_ck_parents, | |
97 | }; | |
98 | ||
99 | static struct ti_clk osc_sys_ck = { | |
100 | .name = "osc_sys_ck", | |
101 | .type = TI_CLK_MUX, | |
102 | .data = &osc_sys_ck_data, | |
103 | }; | |
104 | ||
105 | static struct ti_clk_divider sys_ck_data = { | |
106 | .parent = "osc_sys_ck", | |
107 | .bit_shift = 6, | |
108 | .max_div = 3, | |
109 | .reg = 0x1270, | |
110 | .module = TI_CLKM_PRM, | |
111 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
112 | }; | |
113 | ||
114 | static struct ti_clk sys_ck = { | |
115 | .name = "sys_ck", | |
116 | .type = TI_CLK_DIVIDER, | |
117 | .data = &sys_ck_data, | |
118 | }; | |
119 | ||
120 | static const char *dpll3_ck_parents[] = { | |
121 | "sys_ck", | |
122 | "sys_ck", | |
123 | }; | |
124 | ||
125 | static struct ti_clk_dpll dpll3_ck_data = { | |
126 | .num_parents = ARRAY_SIZE(dpll3_ck_parents), | |
127 | .control_reg = 0xd00, | |
128 | .idlest_reg = 0xd20, | |
129 | .mult_div1_reg = 0xd40, | |
130 | .autoidle_reg = 0xd30, | |
131 | .module = TI_CLKM_CM, | |
132 | .parents = dpll3_ck_parents, | |
133 | .flags = CLKF_CORE, | |
134 | .freqsel_mask = 0xf0, | |
135 | .div1_mask = 0x7f00, | |
136 | .idlest_mask = 0x1, | |
137 | .auto_recal_bit = 0x3, | |
138 | .max_divider = 0x80, | |
139 | .min_divider = 0x1, | |
140 | .recal_en_bit = 0x5, | |
141 | .max_multiplier = 0x7ff, | |
142 | .enable_mask = 0x7, | |
143 | .mult_mask = 0x7ff0000, | |
144 | .recal_st_bit = 0x5, | |
145 | .autoidle_mask = 0x7, | |
146 | }; | |
147 | ||
148 | static struct ti_clk dpll3_ck = { | |
149 | .name = "dpll3_ck", | |
150 | .clkdm_name = "dpll3_clkdm", | |
151 | .type = TI_CLK_DPLL, | |
152 | .data = &dpll3_ck_data, | |
153 | }; | |
154 | ||
155 | static struct ti_clk_divider dpll3_m2_ck_data = { | |
156 | .parent = "dpll3_ck", | |
157 | .bit_shift = 27, | |
158 | .max_div = 31, | |
159 | .reg = 0xd40, | |
160 | .module = TI_CLKM_CM, | |
161 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
162 | }; | |
163 | ||
164 | static struct ti_clk dpll3_m2_ck = { | |
165 | .name = "dpll3_m2_ck", | |
166 | .type = TI_CLK_DIVIDER, | |
167 | .data = &dpll3_m2_ck_data, | |
168 | }; | |
169 | ||
170 | static struct ti_clk_fixed_factor core_ck_data = { | |
171 | .parent = "dpll3_m2_ck", | |
172 | .div = 1, | |
173 | .mult = 1, | |
174 | }; | |
175 | ||
176 | static struct ti_clk core_ck = { | |
177 | .name = "core_ck", | |
178 | .type = TI_CLK_FIXED_FACTOR, | |
179 | .data = &core_ck_data, | |
180 | }; | |
181 | ||
182 | static struct ti_clk_divider l3_ick_data = { | |
183 | .parent = "core_ck", | |
184 | .max_div = 3, | |
185 | .reg = 0xa40, | |
186 | .module = TI_CLKM_CM, | |
187 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
188 | }; | |
189 | ||
190 | static struct ti_clk l3_ick = { | |
191 | .name = "l3_ick", | |
192 | .type = TI_CLK_DIVIDER, | |
193 | .data = &l3_ick_data, | |
194 | }; | |
195 | ||
196 | static struct ti_clk_fixed_factor security_l3_ick_data = { | |
197 | .parent = "l3_ick", | |
198 | .div = 1, | |
199 | .mult = 1, | |
200 | }; | |
201 | ||
202 | static struct ti_clk security_l3_ick = { | |
203 | .name = "security_l3_ick", | |
204 | .type = TI_CLK_FIXED_FACTOR, | |
205 | .data = &security_l3_ick_data, | |
206 | }; | |
207 | ||
208 | static struct ti_clk_fixed_factor wkup_l4_ick_data = { | |
209 | .parent = "sys_ck", | |
210 | .div = 1, | |
211 | .mult = 1, | |
212 | }; | |
213 | ||
214 | static struct ti_clk wkup_l4_ick = { | |
215 | .name = "wkup_l4_ick", | |
216 | .type = TI_CLK_FIXED_FACTOR, | |
217 | .data = &wkup_l4_ick_data, | |
218 | }; | |
219 | ||
220 | static struct ti_clk_gate usim_ick_data = { | |
221 | .parent = "wkup_l4_ick", | |
222 | .bit_shift = 9, | |
223 | .reg = 0xc10, | |
224 | .module = TI_CLKM_CM, | |
225 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
226 | }; | |
227 | ||
228 | static struct ti_clk usim_ick = { | |
229 | .name = "usim_ick", | |
230 | .clkdm_name = "wkup_clkdm", | |
231 | .type = TI_CLK_GATE, | |
232 | .data = &usim_ick_data, | |
233 | }; | |
234 | ||
235 | static struct ti_clk_gate dss2_alwon_fck_data = { | |
236 | .parent = "sys_ck", | |
237 | .bit_shift = 1, | |
238 | .reg = 0xe00, | |
239 | .module = TI_CLKM_CM, | |
240 | }; | |
241 | ||
242 | static struct ti_clk dss2_alwon_fck = { | |
243 | .name = "dss2_alwon_fck", | |
244 | .clkdm_name = "dss_clkdm", | |
245 | .type = TI_CLK_GATE, | |
246 | .data = &dss2_alwon_fck_data, | |
247 | }; | |
248 | ||
249 | static struct ti_clk_divider l4_ick_data = { | |
250 | .parent = "l3_ick", | |
251 | .bit_shift = 2, | |
252 | .max_div = 3, | |
253 | .reg = 0xa40, | |
254 | .module = TI_CLKM_CM, | |
255 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
256 | }; | |
257 | ||
258 | static struct ti_clk l4_ick = { | |
259 | .name = "l4_ick", | |
260 | .type = TI_CLK_DIVIDER, | |
261 | .data = &l4_ick_data, | |
262 | }; | |
263 | ||
264 | static struct ti_clk_fixed_factor core_l4_ick_data = { | |
265 | .parent = "l4_ick", | |
266 | .div = 1, | |
267 | .mult = 1, | |
268 | }; | |
269 | ||
270 | static struct ti_clk core_l4_ick = { | |
271 | .name = "core_l4_ick", | |
272 | .type = TI_CLK_FIXED_FACTOR, | |
273 | .data = &core_l4_ick_data, | |
274 | }; | |
275 | ||
276 | static struct ti_clk_gate mmchs2_ick_data = { | |
277 | .parent = "core_l4_ick", | |
278 | .bit_shift = 25, | |
279 | .reg = 0xa10, | |
280 | .module = TI_CLKM_CM, | |
281 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
282 | }; | |
283 | ||
284 | static struct ti_clk mmchs2_ick = { | |
285 | .name = "mmchs2_ick", | |
286 | .clkdm_name = "core_l4_clkdm", | |
287 | .type = TI_CLK_GATE, | |
288 | .data = &mmchs2_ick_data, | |
289 | }; | |
290 | ||
291 | static const char *dpll4_ck_parents[] = { | |
292 | "sys_ck", | |
293 | "sys_ck", | |
294 | }; | |
295 | ||
296 | static struct ti_clk_dpll dpll4_ck_data = { | |
297 | .num_parents = ARRAY_SIZE(dpll4_ck_parents), | |
298 | .control_reg = 0xd00, | |
299 | .idlest_reg = 0xd20, | |
300 | .mult_div1_reg = 0xd44, | |
301 | .autoidle_reg = 0xd30, | |
302 | .module = TI_CLKM_CM, | |
303 | .parents = dpll4_ck_parents, | |
304 | .flags = CLKF_PER, | |
305 | .freqsel_mask = 0xf00000, | |
306 | .modes = 0x82, | |
307 | .div1_mask = 0x7f, | |
308 | .idlest_mask = 0x2, | |
309 | .auto_recal_bit = 0x13, | |
310 | .max_divider = 0x80, | |
311 | .min_divider = 0x1, | |
312 | .recal_en_bit = 0x6, | |
313 | .max_multiplier = 0x7ff, | |
314 | .enable_mask = 0x70000, | |
315 | .mult_mask = 0x7ff00, | |
316 | .recal_st_bit = 0x6, | |
317 | .autoidle_mask = 0x38, | |
318 | }; | |
319 | ||
320 | static struct ti_clk dpll4_ck = { | |
321 | .name = "dpll4_ck", | |
322 | .clkdm_name = "dpll4_clkdm", | |
323 | .type = TI_CLK_DPLL, | |
324 | .data = &dpll4_ck_data, | |
325 | }; | |
326 | ||
327 | static struct ti_clk_divider dpll4_m2_ck_data = { | |
328 | .parent = "dpll4_ck", | |
329 | .max_div = 63, | |
330 | .reg = 0xd48, | |
331 | .module = TI_CLKM_CM, | |
332 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
333 | }; | |
334 | ||
335 | static struct ti_clk dpll4_m2_ck = { | |
336 | .name = "dpll4_m2_ck", | |
337 | .type = TI_CLK_DIVIDER, | |
338 | .data = &dpll4_m2_ck_data, | |
339 | }; | |
340 | ||
341 | static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = { | |
342 | .parent = "dpll4_m2_ck", | |
343 | .div = 1, | |
344 | .mult = 2, | |
345 | }; | |
346 | ||
347 | static struct ti_clk dpll4_m2x2_mul_ck = { | |
348 | .name = "dpll4_m2x2_mul_ck", | |
349 | .type = TI_CLK_FIXED_FACTOR, | |
350 | .data = &dpll4_m2x2_mul_ck_data, | |
351 | }; | |
352 | ||
353 | static struct ti_clk_gate dpll4_m2x2_ck_data = { | |
354 | .parent = "dpll4_m2x2_mul_ck", | |
355 | .bit_shift = 0x1b, | |
356 | .reg = 0xd00, | |
357 | .module = TI_CLKM_CM, | |
358 | .flags = CLKF_SET_BIT_TO_DISABLE, | |
359 | }; | |
360 | ||
361 | static struct ti_clk dpll4_m2x2_ck = { | |
362 | .name = "dpll4_m2x2_ck", | |
363 | .type = TI_CLK_GATE, | |
364 | .data = &dpll4_m2x2_ck_data, | |
365 | }; | |
366 | ||
367 | static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = { | |
368 | .parent = "dpll4_m2x2_ck", | |
369 | .div = 1, | |
370 | .mult = 1, | |
371 | }; | |
372 | ||
373 | static struct ti_clk omap_96m_alwon_fck = { | |
374 | .name = "omap_96m_alwon_fck", | |
375 | .type = TI_CLK_FIXED_FACTOR, | |
376 | .data = &omap_96m_alwon_fck_data, | |
377 | }; | |
378 | ||
379 | static struct ti_clk_fixed_factor cm_96m_fck_data = { | |
380 | .parent = "omap_96m_alwon_fck", | |
381 | .div = 1, | |
382 | .mult = 1, | |
383 | }; | |
384 | ||
385 | static struct ti_clk cm_96m_fck = { | |
386 | .name = "cm_96m_fck", | |
387 | .type = TI_CLK_FIXED_FACTOR, | |
388 | .data = &cm_96m_fck_data, | |
389 | }; | |
390 | ||
391 | static const char *omap_96m_fck_parents[] = { | |
392 | "cm_96m_fck", | |
393 | "sys_ck", | |
394 | }; | |
395 | ||
396 | static struct ti_clk_mux omap_96m_fck_data = { | |
397 | .bit_shift = 6, | |
398 | .num_parents = ARRAY_SIZE(omap_96m_fck_parents), | |
399 | .reg = 0xd40, | |
400 | .module = TI_CLKM_CM, | |
401 | .parents = omap_96m_fck_parents, | |
402 | }; | |
403 | ||
404 | static struct ti_clk omap_96m_fck = { | |
405 | .name = "omap_96m_fck", | |
406 | .type = TI_CLK_MUX, | |
407 | .data = &omap_96m_fck_data, | |
408 | }; | |
409 | ||
410 | static struct ti_clk_fixed_factor core_96m_fck_data = { | |
411 | .parent = "omap_96m_fck", | |
412 | .div = 1, | |
413 | .mult = 1, | |
414 | }; | |
415 | ||
416 | static struct ti_clk core_96m_fck = { | |
417 | .name = "core_96m_fck", | |
418 | .type = TI_CLK_FIXED_FACTOR, | |
419 | .data = &core_96m_fck_data, | |
420 | }; | |
421 | ||
422 | static struct ti_clk_gate mspro_fck_data = { | |
423 | .parent = "core_96m_fck", | |
424 | .bit_shift = 23, | |
425 | .reg = 0xa00, | |
426 | .module = TI_CLKM_CM, | |
427 | .flags = CLKF_WAIT, | |
428 | }; | |
429 | ||
430 | static struct ti_clk mspro_fck = { | |
431 | .name = "mspro_fck", | |
432 | .clkdm_name = "core_l4_clkdm", | |
433 | .type = TI_CLK_GATE, | |
434 | .data = &mspro_fck_data, | |
435 | }; | |
436 | ||
437 | static struct ti_clk_gate dss_ick_3430es2_data = { | |
438 | .parent = "l4_ick", | |
439 | .bit_shift = 0, | |
440 | .reg = 0xe10, | |
441 | .module = TI_CLKM_CM, | |
442 | .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE, | |
443 | }; | |
444 | ||
445 | static struct ti_clk dss_ick_3430es2 = { | |
446 | .name = "dss_ick", | |
447 | .clkdm_name = "dss_clkdm", | |
448 | .type = TI_CLK_GATE, | |
449 | .data = &dss_ick_3430es2_data, | |
450 | }; | |
451 | ||
452 | static struct ti_clk_gate uart4_ick_am35xx_data = { | |
453 | .parent = "core_l4_ick", | |
454 | .bit_shift = 23, | |
455 | .reg = 0xa10, | |
456 | .module = TI_CLKM_CM, | |
457 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
458 | }; | |
459 | ||
460 | static struct ti_clk uart4_ick_am35xx = { | |
461 | .name = "uart4_ick_am35xx", | |
462 | .clkdm_name = "core_l4_clkdm", | |
463 | .type = TI_CLK_GATE, | |
464 | .data = &uart4_ick_am35xx_data, | |
465 | }; | |
466 | ||
467 | static struct ti_clk_fixed_factor security_l4_ick2_data = { | |
468 | .parent = "l4_ick", | |
469 | .div = 1, | |
470 | .mult = 1, | |
471 | }; | |
472 | ||
473 | static struct ti_clk security_l4_ick2 = { | |
474 | .name = "security_l4_ick2", | |
475 | .type = TI_CLK_FIXED_FACTOR, | |
476 | .data = &security_l4_ick2_data, | |
477 | }; | |
478 | ||
479 | static struct ti_clk_gate aes1_ick_data = { | |
480 | .parent = "security_l4_ick2", | |
481 | .bit_shift = 3, | |
482 | .reg = 0xa14, | |
483 | .module = TI_CLKM_CM, | |
484 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
485 | }; | |
486 | ||
487 | static struct ti_clk aes1_ick = { | |
488 | .name = "aes1_ick", | |
489 | .type = TI_CLK_GATE, | |
490 | .data = &aes1_ick_data, | |
491 | }; | |
492 | ||
493 | static const char *dpll5_ck_parents[] = { | |
494 | "sys_ck", | |
495 | "sys_ck", | |
496 | }; | |
497 | ||
498 | static struct ti_clk_dpll dpll5_ck_data = { | |
499 | .num_parents = ARRAY_SIZE(dpll5_ck_parents), | |
500 | .control_reg = 0xd04, | |
501 | .idlest_reg = 0xd24, | |
502 | .mult_div1_reg = 0xd4c, | |
503 | .autoidle_reg = 0xd34, | |
504 | .module = TI_CLKM_CM, | |
505 | .parents = dpll5_ck_parents, | |
506 | .freqsel_mask = 0xf0, | |
507 | .modes = 0x82, | |
508 | .div1_mask = 0x7f, | |
509 | .idlest_mask = 0x1, | |
510 | .auto_recal_bit = 0x3, | |
511 | .max_divider = 0x80, | |
512 | .min_divider = 0x1, | |
513 | .recal_en_bit = 0x19, | |
514 | .max_multiplier = 0x7ff, | |
515 | .enable_mask = 0x7, | |
516 | .mult_mask = 0x7ff00, | |
517 | .recal_st_bit = 0x19, | |
518 | .autoidle_mask = 0x7, | |
519 | }; | |
520 | ||
521 | static struct ti_clk dpll5_ck = { | |
522 | .name = "dpll5_ck", | |
523 | .clkdm_name = "dpll5_clkdm", | |
524 | .type = TI_CLK_DPLL, | |
525 | .data = &dpll5_ck_data, | |
526 | }; | |
527 | ||
528 | static struct ti_clk_divider dpll5_m2_ck_data = { | |
529 | .parent = "dpll5_ck", | |
530 | .max_div = 31, | |
531 | .reg = 0xd50, | |
532 | .module = TI_CLKM_CM, | |
533 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
534 | }; | |
535 | ||
536 | static struct ti_clk dpll5_m2_ck = { | |
537 | .name = "dpll5_m2_ck", | |
538 | .type = TI_CLK_DIVIDER, | |
539 | .data = &dpll5_m2_ck_data, | |
540 | }; | |
541 | ||
542 | static struct ti_clk_gate usbhost_120m_fck_data = { | |
543 | .parent = "dpll5_m2_ck", | |
544 | .bit_shift = 1, | |
545 | .reg = 0x1400, | |
546 | .module = TI_CLKM_CM, | |
547 | }; | |
548 | ||
549 | static struct ti_clk usbhost_120m_fck = { | |
550 | .name = "usbhost_120m_fck", | |
551 | .clkdm_name = "usbhost_clkdm", | |
552 | .type = TI_CLK_GATE, | |
553 | .data = &usbhost_120m_fck_data, | |
554 | }; | |
555 | ||
556 | static struct ti_clk_fixed_factor cm_96m_d2_fck_data = { | |
557 | .parent = "cm_96m_fck", | |
558 | .div = 2, | |
559 | .mult = 1, | |
560 | }; | |
561 | ||
562 | static struct ti_clk cm_96m_d2_fck = { | |
563 | .name = "cm_96m_d2_fck", | |
564 | .type = TI_CLK_FIXED_FACTOR, | |
565 | .data = &cm_96m_d2_fck_data, | |
566 | }; | |
567 | ||
568 | static struct ti_clk_fixed sys_altclk_data = { | |
569 | .frequency = 0x0, | |
570 | }; | |
571 | ||
572 | static struct ti_clk sys_altclk = { | |
573 | .name = "sys_altclk", | |
574 | .type = TI_CLK_FIXED, | |
575 | .data = &sys_altclk_data, | |
576 | }; | |
577 | ||
578 | static const char *omap_48m_fck_parents[] = { | |
579 | "cm_96m_d2_fck", | |
580 | "sys_altclk", | |
581 | }; | |
582 | ||
583 | static struct ti_clk_mux omap_48m_fck_data = { | |
584 | .bit_shift = 3, | |
585 | .num_parents = ARRAY_SIZE(omap_48m_fck_parents), | |
586 | .reg = 0xd40, | |
587 | .module = TI_CLKM_CM, | |
588 | .parents = omap_48m_fck_parents, | |
589 | }; | |
590 | ||
591 | static struct ti_clk omap_48m_fck = { | |
592 | .name = "omap_48m_fck", | |
593 | .type = TI_CLK_MUX, | |
594 | .data = &omap_48m_fck_data, | |
595 | }; | |
596 | ||
597 | static struct ti_clk_fixed_factor core_48m_fck_data = { | |
598 | .parent = "omap_48m_fck", | |
599 | .div = 1, | |
600 | .mult = 1, | |
601 | }; | |
602 | ||
603 | static struct ti_clk core_48m_fck = { | |
604 | .name = "core_48m_fck", | |
605 | .type = TI_CLK_FIXED_FACTOR, | |
606 | .data = &core_48m_fck_data, | |
607 | }; | |
608 | ||
609 | static struct ti_clk_fixed mcbsp_clks_data = { | |
610 | .frequency = 0x0, | |
611 | }; | |
612 | ||
613 | static struct ti_clk mcbsp_clks = { | |
614 | .name = "mcbsp_clks", | |
615 | .type = TI_CLK_FIXED, | |
616 | .data = &mcbsp_clks_data, | |
617 | }; | |
618 | ||
619 | static struct ti_clk_gate mcbsp2_gate_fck_data = { | |
620 | .parent = "mcbsp_clks", | |
621 | .bit_shift = 0, | |
622 | .reg = 0x1000, | |
623 | .module = TI_CLKM_CM, | |
624 | }; | |
625 | ||
626 | static struct ti_clk_fixed_factor per_96m_fck_data = { | |
627 | .parent = "omap_96m_alwon_fck", | |
628 | .div = 1, | |
629 | .mult = 1, | |
630 | }; | |
631 | ||
632 | static struct ti_clk per_96m_fck = { | |
633 | .name = "per_96m_fck", | |
634 | .type = TI_CLK_FIXED_FACTOR, | |
635 | .data = &per_96m_fck_data, | |
636 | }; | |
637 | ||
638 | static const char *mcbsp2_mux_fck_parents[] = { | |
639 | "per_96m_fck", | |
640 | "mcbsp_clks", | |
641 | }; | |
642 | ||
643 | static struct ti_clk_mux mcbsp2_mux_fck_data = { | |
644 | .bit_shift = 6, | |
645 | .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents), | |
646 | .reg = 0x274, | |
647 | .module = TI_CLKM_SCRM, | |
648 | .parents = mcbsp2_mux_fck_parents, | |
649 | }; | |
650 | ||
651 | static struct ti_clk_composite mcbsp2_fck_data = { | |
652 | .mux = &mcbsp2_mux_fck_data, | |
653 | .gate = &mcbsp2_gate_fck_data, | |
654 | }; | |
655 | ||
656 | static struct ti_clk mcbsp2_fck = { | |
657 | .name = "mcbsp2_fck", | |
658 | .type = TI_CLK_COMPOSITE, | |
659 | .data = &mcbsp2_fck_data, | |
660 | }; | |
661 | ||
662 | static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = { | |
663 | .parent = "dpll3_m2_ck", | |
664 | .div = 1, | |
665 | .mult = 2, | |
666 | }; | |
667 | ||
668 | static struct ti_clk dpll3_m2x2_ck = { | |
669 | .name = "dpll3_m2x2_ck", | |
670 | .type = TI_CLK_FIXED_FACTOR, | |
671 | .data = &dpll3_m2x2_ck_data, | |
672 | }; | |
673 | ||
674 | static struct ti_clk_fixed_factor corex2_fck_data = { | |
675 | .parent = "dpll3_m2x2_ck", | |
676 | .div = 1, | |
677 | .mult = 1, | |
678 | }; | |
679 | ||
680 | static struct ti_clk corex2_fck = { | |
681 | .name = "corex2_fck", | |
682 | .type = TI_CLK_FIXED_FACTOR, | |
683 | .data = &corex2_fck_data, | |
684 | }; | |
685 | ||
686 | static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = { | |
687 | .parent = "corex2_fck", | |
688 | .bit_shift = 0, | |
689 | .reg = 0xa00, | |
690 | .module = TI_CLKM_CM, | |
691 | .flags = CLKF_NO_WAIT, | |
692 | }; | |
693 | ||
694 | static int ssi_ssr_div_fck_3430es1_divs[] = { | |
695 | 0, | |
696 | 1, | |
697 | 2, | |
698 | 3, | |
699 | 4, | |
700 | 0, | |
701 | 6, | |
702 | 0, | |
703 | 8, | |
704 | }; | |
705 | ||
706 | static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = { | |
707 | .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs), | |
708 | .parent = "corex2_fck", | |
709 | .bit_shift = 8, | |
710 | .dividers = ssi_ssr_div_fck_3430es1_divs, | |
711 | .reg = 0xa40, | |
712 | .module = TI_CLKM_CM, | |
713 | }; | |
714 | ||
715 | static struct ti_clk_composite ssi_ssr_fck_3430es1_data = { | |
716 | .gate = &ssi_ssr_gate_fck_3430es1_data, | |
717 | .divider = &ssi_ssr_div_fck_3430es1_data, | |
718 | }; | |
719 | ||
720 | static struct ti_clk ssi_ssr_fck_3430es1 = { | |
721 | .name = "ssi_ssr_fck", | |
722 | .type = TI_CLK_COMPOSITE, | |
723 | .data = &ssi_ssr_fck_3430es1_data, | |
724 | }; | |
725 | ||
726 | static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = { | |
727 | .parent = "ssi_ssr_fck", | |
728 | .div = 2, | |
729 | .mult = 1, | |
730 | }; | |
731 | ||
732 | static struct ti_clk ssi_sst_fck_3430es1 = { | |
733 | .name = "ssi_sst_fck", | |
734 | .type = TI_CLK_FIXED_FACTOR, | |
735 | .data = &ssi_sst_fck_3430es1_data, | |
736 | }; | |
737 | ||
738 | static struct ti_clk_fixed omap_32k_fck_data = { | |
739 | .frequency = 32768, | |
740 | }; | |
741 | ||
742 | static struct ti_clk omap_32k_fck = { | |
743 | .name = "omap_32k_fck", | |
744 | .type = TI_CLK_FIXED, | |
745 | .data = &omap_32k_fck_data, | |
746 | }; | |
747 | ||
748 | static struct ti_clk_fixed_factor per_32k_alwon_fck_data = { | |
749 | .parent = "omap_32k_fck", | |
750 | .div = 1, | |
751 | .mult = 1, | |
752 | }; | |
753 | ||
754 | static struct ti_clk per_32k_alwon_fck = { | |
755 | .name = "per_32k_alwon_fck", | |
756 | .type = TI_CLK_FIXED_FACTOR, | |
757 | .data = &per_32k_alwon_fck_data, | |
758 | }; | |
759 | ||
760 | static struct ti_clk_gate gpio5_dbck_data = { | |
761 | .parent = "per_32k_alwon_fck", | |
762 | .bit_shift = 16, | |
763 | .reg = 0x1000, | |
764 | .module = TI_CLKM_CM, | |
765 | }; | |
766 | ||
767 | static struct ti_clk gpio5_dbck = { | |
768 | .name = "gpio5_dbck", | |
769 | .clkdm_name = "per_clkdm", | |
770 | .type = TI_CLK_GATE, | |
771 | .data = &gpio5_dbck_data, | |
772 | }; | |
773 | ||
774 | static struct ti_clk_gate gpt1_ick_data = { | |
775 | .parent = "wkup_l4_ick", | |
776 | .bit_shift = 0, | |
777 | .reg = 0xc10, | |
778 | .module = TI_CLKM_CM, | |
779 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
780 | }; | |
781 | ||
782 | static struct ti_clk gpt1_ick = { | |
783 | .name = "gpt1_ick", | |
784 | .clkdm_name = "wkup_clkdm", | |
785 | .type = TI_CLK_GATE, | |
786 | .data = &gpt1_ick_data, | |
787 | }; | |
788 | ||
789 | static struct ti_clk_gate mcspi3_fck_data = { | |
790 | .parent = "core_48m_fck", | |
791 | .bit_shift = 20, | |
792 | .reg = 0xa00, | |
793 | .module = TI_CLKM_CM, | |
794 | .flags = CLKF_WAIT, | |
795 | }; | |
796 | ||
797 | static struct ti_clk mcspi3_fck = { | |
798 | .name = "mcspi3_fck", | |
799 | .clkdm_name = "core_l4_clkdm", | |
800 | .type = TI_CLK_GATE, | |
801 | .data = &mcspi3_fck_data, | |
802 | }; | |
803 | ||
804 | static struct ti_clk_gate gpt2_gate_fck_data = { | |
805 | .parent = "sys_ck", | |
806 | .bit_shift = 3, | |
807 | .reg = 0x1000, | |
808 | .module = TI_CLKM_CM, | |
809 | }; | |
810 | ||
811 | static const char *gpt2_mux_fck_parents[] = { | |
812 | "omap_32k_fck", | |
813 | "sys_ck", | |
814 | }; | |
815 | ||
816 | static struct ti_clk_mux gpt2_mux_fck_data = { | |
817 | .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents), | |
818 | .reg = 0x1040, | |
819 | .module = TI_CLKM_CM, | |
820 | .parents = gpt2_mux_fck_parents, | |
821 | }; | |
822 | ||
823 | static struct ti_clk_composite gpt2_fck_data = { | |
824 | .mux = &gpt2_mux_fck_data, | |
825 | .gate = &gpt2_gate_fck_data, | |
826 | }; | |
827 | ||
828 | static struct ti_clk gpt2_fck = { | |
829 | .name = "gpt2_fck", | |
830 | .type = TI_CLK_COMPOSITE, | |
831 | .data = &gpt2_fck_data, | |
832 | }; | |
833 | ||
834 | static struct ti_clk_gate gpt10_ick_data = { | |
835 | .parent = "core_l4_ick", | |
836 | .bit_shift = 11, | |
837 | .reg = 0xa10, | |
838 | .module = TI_CLKM_CM, | |
839 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
840 | }; | |
841 | ||
842 | static struct ti_clk gpt10_ick = { | |
843 | .name = "gpt10_ick", | |
844 | .clkdm_name = "core_l4_clkdm", | |
845 | .type = TI_CLK_GATE, | |
846 | .data = &gpt10_ick_data, | |
847 | }; | |
848 | ||
849 | static struct ti_clk_gate uart2_fck_data = { | |
850 | .parent = "core_48m_fck", | |
851 | .bit_shift = 14, | |
852 | .reg = 0xa00, | |
853 | .module = TI_CLKM_CM, | |
854 | .flags = CLKF_WAIT, | |
855 | }; | |
856 | ||
857 | static struct ti_clk uart2_fck = { | |
858 | .name = "uart2_fck", | |
859 | .clkdm_name = "core_l4_clkdm", | |
860 | .type = TI_CLK_GATE, | |
861 | .data = &uart2_fck_data, | |
862 | }; | |
863 | ||
864 | static struct ti_clk_fixed_factor sr_l4_ick_data = { | |
865 | .parent = "l4_ick", | |
866 | .div = 1, | |
867 | .mult = 1, | |
868 | }; | |
869 | ||
870 | static struct ti_clk sr_l4_ick = { | |
871 | .name = "sr_l4_ick", | |
872 | .type = TI_CLK_FIXED_FACTOR, | |
873 | .data = &sr_l4_ick_data, | |
874 | }; | |
875 | ||
876 | static struct ti_clk_fixed_factor omap_96m_d8_fck_data = { | |
877 | .parent = "omap_96m_fck", | |
878 | .div = 8, | |
879 | .mult = 1, | |
880 | }; | |
881 | ||
882 | static struct ti_clk omap_96m_d8_fck = { | |
883 | .name = "omap_96m_d8_fck", | |
884 | .type = TI_CLK_FIXED_FACTOR, | |
885 | .data = &omap_96m_d8_fck_data, | |
886 | }; | |
887 | ||
888 | static struct ti_clk_divider dpll4_m5_ck_data = { | |
889 | .parent = "dpll4_ck", | |
890 | .max_div = 63, | |
891 | .reg = 0xf40, | |
892 | .module = TI_CLKM_CM, | |
893 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
894 | }; | |
895 | ||
896 | static struct ti_clk dpll4_m5_ck = { | |
897 | .name = "dpll4_m5_ck", | |
898 | .type = TI_CLK_DIVIDER, | |
899 | .data = &dpll4_m5_ck_data, | |
900 | }; | |
901 | ||
902 | static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = { | |
903 | .parent = "dpll4_m5_ck", | |
904 | .div = 1, | |
905 | .mult = 2, | |
906 | .flags = CLKF_SET_RATE_PARENT, | |
907 | }; | |
908 | ||
909 | static struct ti_clk dpll4_m5x2_mul_ck = { | |
910 | .name = "dpll4_m5x2_mul_ck", | |
911 | .type = TI_CLK_FIXED_FACTOR, | |
912 | .data = &dpll4_m5x2_mul_ck_data, | |
913 | }; | |
914 | ||
915 | static struct ti_clk_gate dpll4_m5x2_ck_data = { | |
916 | .parent = "dpll4_m5x2_mul_ck", | |
917 | .bit_shift = 0x1e, | |
918 | .reg = 0xd00, | |
919 | .module = TI_CLKM_CM, | |
920 | .flags = CLKF_SET_BIT_TO_DISABLE, | |
921 | }; | |
922 | ||
923 | static struct ti_clk dpll4_m5x2_ck = { | |
924 | .name = "dpll4_m5x2_ck", | |
925 | .type = TI_CLK_GATE, | |
926 | .data = &dpll4_m5x2_ck_data, | |
927 | }; | |
928 | ||
929 | static struct ti_clk_gate cam_mclk_data = { | |
930 | .parent = "dpll4_m5x2_ck", | |
931 | .bit_shift = 0, | |
932 | .reg = 0xf00, | |
933 | .module = TI_CLKM_CM, | |
934 | .flags = CLKF_SET_RATE_PARENT, | |
935 | }; | |
936 | ||
937 | static struct ti_clk cam_mclk = { | |
938 | .name = "cam_mclk", | |
939 | .type = TI_CLK_GATE, | |
940 | .data = &cam_mclk_data, | |
941 | }; | |
942 | ||
943 | static struct ti_clk_gate mcbsp3_gate_fck_data = { | |
944 | .parent = "mcbsp_clks", | |
945 | .bit_shift = 1, | |
946 | .reg = 0x1000, | |
947 | .module = TI_CLKM_CM, | |
948 | }; | |
949 | ||
950 | static const char *mcbsp3_mux_fck_parents[] = { | |
951 | "per_96m_fck", | |
952 | "mcbsp_clks", | |
953 | }; | |
954 | ||
955 | static struct ti_clk_mux mcbsp3_mux_fck_data = { | |
956 | .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents), | |
957 | .reg = 0x2d8, | |
958 | .module = TI_CLKM_SCRM, | |
959 | .parents = mcbsp3_mux_fck_parents, | |
960 | }; | |
961 | ||
962 | static struct ti_clk_composite mcbsp3_fck_data = { | |
963 | .mux = &mcbsp3_mux_fck_data, | |
964 | .gate = &mcbsp3_gate_fck_data, | |
965 | }; | |
966 | ||
967 | static struct ti_clk mcbsp3_fck = { | |
968 | .name = "mcbsp3_fck", | |
969 | .type = TI_CLK_COMPOSITE, | |
970 | .data = &mcbsp3_fck_data, | |
971 | }; | |
972 | ||
973 | static struct ti_clk_gate csi2_96m_fck_data = { | |
974 | .parent = "core_96m_fck", | |
975 | .bit_shift = 1, | |
976 | .reg = 0xf00, | |
977 | .module = TI_CLKM_CM, | |
978 | }; | |
979 | ||
980 | static struct ti_clk csi2_96m_fck = { | |
981 | .name = "csi2_96m_fck", | |
982 | .clkdm_name = "cam_clkdm", | |
983 | .type = TI_CLK_GATE, | |
984 | .data = &csi2_96m_fck_data, | |
985 | }; | |
986 | ||
987 | static struct ti_clk_gate gpt9_gate_fck_data = { | |
988 | .parent = "sys_ck", | |
989 | .bit_shift = 10, | |
990 | .reg = 0x1000, | |
991 | .module = TI_CLKM_CM, | |
992 | }; | |
993 | ||
994 | static const char *gpt9_mux_fck_parents[] = { | |
995 | "omap_32k_fck", | |
996 | "sys_ck", | |
997 | }; | |
998 | ||
999 | static struct ti_clk_mux gpt9_mux_fck_data = { | |
1000 | .bit_shift = 7, | |
1001 | .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents), | |
1002 | .reg = 0x1040, | |
1003 | .module = TI_CLKM_CM, | |
1004 | .parents = gpt9_mux_fck_parents, | |
1005 | }; | |
1006 | ||
1007 | static struct ti_clk_composite gpt9_fck_data = { | |
1008 | .mux = &gpt9_mux_fck_data, | |
1009 | .gate = &gpt9_gate_fck_data, | |
1010 | }; | |
1011 | ||
1012 | static struct ti_clk gpt9_fck = { | |
1013 | .name = "gpt9_fck", | |
1014 | .type = TI_CLK_COMPOSITE, | |
1015 | .data = &gpt9_fck_data, | |
1016 | }; | |
1017 | ||
1018 | static struct ti_clk_divider dpll3_m3_ck_data = { | |
1019 | .parent = "dpll3_ck", | |
1020 | .bit_shift = 16, | |
1021 | .max_div = 31, | |
1022 | .reg = 0x1140, | |
1023 | .module = TI_CLKM_CM, | |
1024 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1025 | }; | |
1026 | ||
1027 | static struct ti_clk dpll3_m3_ck = { | |
1028 | .name = "dpll3_m3_ck", | |
1029 | .type = TI_CLK_DIVIDER, | |
1030 | .data = &dpll3_m3_ck_data, | |
1031 | }; | |
1032 | ||
1033 | static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = { | |
1034 | .parent = "dpll3_m3_ck", | |
1035 | .div = 1, | |
1036 | .mult = 2, | |
1037 | }; | |
1038 | ||
1039 | static struct ti_clk dpll3_m3x2_mul_ck = { | |
1040 | .name = "dpll3_m3x2_mul_ck", | |
1041 | .type = TI_CLK_FIXED_FACTOR, | |
1042 | .data = &dpll3_m3x2_mul_ck_data, | |
1043 | }; | |
1044 | ||
1045 | static struct ti_clk_gate sr2_fck_data = { | |
1046 | .parent = "sys_ck", | |
1047 | .bit_shift = 7, | |
1048 | .reg = 0xc00, | |
1049 | .module = TI_CLKM_CM, | |
1050 | .flags = CLKF_WAIT, | |
1051 | }; | |
1052 | ||
1053 | static struct ti_clk sr2_fck = { | |
1054 | .name = "sr2_fck", | |
1055 | .clkdm_name = "wkup_clkdm", | |
1056 | .type = TI_CLK_GATE, | |
1057 | .data = &sr2_fck_data, | |
1058 | }; | |
1059 | ||
1060 | static struct ti_clk_fixed pclk_ck_data = { | |
1061 | .frequency = 27000000, | |
1062 | }; | |
1063 | ||
1064 | static struct ti_clk pclk_ck = { | |
1065 | .name = "pclk_ck", | |
1066 | .type = TI_CLK_FIXED, | |
1067 | .data = &pclk_ck_data, | |
1068 | }; | |
1069 | ||
1070 | static struct ti_clk_gate wdt2_ick_data = { | |
1071 | .parent = "wkup_l4_ick", | |
1072 | .bit_shift = 5, | |
1073 | .reg = 0xc10, | |
1074 | .module = TI_CLKM_CM, | |
1075 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1076 | }; | |
1077 | ||
1078 | static struct ti_clk wdt2_ick = { | |
1079 | .name = "wdt2_ick", | |
1080 | .clkdm_name = "wkup_clkdm", | |
1081 | .type = TI_CLK_GATE, | |
1082 | .data = &wdt2_ick_data, | |
1083 | }; | |
1084 | ||
1085 | static struct ti_clk_fixed_factor core_l3_ick_data = { | |
1086 | .parent = "l3_ick", | |
1087 | .div = 1, | |
1088 | .mult = 1, | |
1089 | }; | |
1090 | ||
1091 | static struct ti_clk core_l3_ick = { | |
1092 | .name = "core_l3_ick", | |
1093 | .type = TI_CLK_FIXED_FACTOR, | |
1094 | .data = &core_l3_ick_data, | |
1095 | }; | |
1096 | ||
1097 | static struct ti_clk_gate mcspi4_fck_data = { | |
1098 | .parent = "core_48m_fck", | |
1099 | .bit_shift = 21, | |
1100 | .reg = 0xa00, | |
1101 | .module = TI_CLKM_CM, | |
1102 | .flags = CLKF_WAIT, | |
1103 | }; | |
1104 | ||
1105 | static struct ti_clk mcspi4_fck = { | |
1106 | .name = "mcspi4_fck", | |
1107 | .clkdm_name = "core_l4_clkdm", | |
1108 | .type = TI_CLK_GATE, | |
1109 | .data = &mcspi4_fck_data, | |
1110 | }; | |
1111 | ||
1112 | static struct ti_clk_fixed_factor per_48m_fck_data = { | |
1113 | .parent = "omap_48m_fck", | |
1114 | .div = 1, | |
1115 | .mult = 1, | |
1116 | }; | |
1117 | ||
1118 | static struct ti_clk per_48m_fck = { | |
1119 | .name = "per_48m_fck", | |
1120 | .type = TI_CLK_FIXED_FACTOR, | |
1121 | .data = &per_48m_fck_data, | |
1122 | }; | |
1123 | ||
1124 | static struct ti_clk_gate uart4_fck_data = { | |
1125 | .parent = "per_48m_fck", | |
1126 | .bit_shift = 18, | |
1127 | .reg = 0x1000, | |
1128 | .module = TI_CLKM_CM, | |
1129 | .flags = CLKF_WAIT, | |
1130 | }; | |
1131 | ||
1132 | static struct ti_clk uart4_fck = { | |
1133 | .name = "uart4_fck", | |
1134 | .clkdm_name = "per_clkdm", | |
1135 | .type = TI_CLK_GATE, | |
1136 | .data = &uart4_fck_data, | |
1137 | }; | |
1138 | ||
1139 | static struct ti_clk_fixed_factor omap_96m_d10_fck_data = { | |
1140 | .parent = "omap_96m_fck", | |
1141 | .div = 10, | |
1142 | .mult = 1, | |
1143 | }; | |
1144 | ||
1145 | static struct ti_clk omap_96m_d10_fck = { | |
1146 | .name = "omap_96m_d10_fck", | |
1147 | .type = TI_CLK_FIXED_FACTOR, | |
1148 | .data = &omap_96m_d10_fck_data, | |
1149 | }; | |
1150 | ||
1151 | static struct ti_clk_gate usim_gate_fck_data = { | |
1152 | .parent = "omap_96m_fck", | |
1153 | .bit_shift = 9, | |
1154 | .reg = 0xc00, | |
1155 | .module = TI_CLKM_CM, | |
1156 | }; | |
1157 | ||
1158 | static struct ti_clk_fixed_factor per_l4_ick_data = { | |
1159 | .parent = "l4_ick", | |
1160 | .div = 1, | |
1161 | .mult = 1, | |
1162 | }; | |
1163 | ||
1164 | static struct ti_clk per_l4_ick = { | |
1165 | .name = "per_l4_ick", | |
1166 | .type = TI_CLK_FIXED_FACTOR, | |
1167 | .data = &per_l4_ick_data, | |
1168 | }; | |
1169 | ||
1170 | static struct ti_clk_gate gpt5_ick_data = { | |
1171 | .parent = "per_l4_ick", | |
1172 | .bit_shift = 6, | |
1173 | .reg = 0x1010, | |
1174 | .module = TI_CLKM_CM, | |
1175 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1176 | }; | |
1177 | ||
1178 | static struct ti_clk gpt5_ick = { | |
1179 | .name = "gpt5_ick", | |
1180 | .clkdm_name = "per_clkdm", | |
1181 | .type = TI_CLK_GATE, | |
1182 | .data = &gpt5_ick_data, | |
1183 | }; | |
1184 | ||
1185 | static struct ti_clk_gate mcspi2_ick_data = { | |
1186 | .parent = "core_l4_ick", | |
1187 | .bit_shift = 19, | |
1188 | .reg = 0xa10, | |
1189 | .module = TI_CLKM_CM, | |
1190 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1191 | }; | |
1192 | ||
1193 | static struct ti_clk mcspi2_ick = { | |
1194 | .name = "mcspi2_ick", | |
1195 | .clkdm_name = "core_l4_clkdm", | |
1196 | .type = TI_CLK_GATE, | |
1197 | .data = &mcspi2_ick_data, | |
1198 | }; | |
1199 | ||
1200 | static struct ti_clk_fixed_factor ssi_l4_ick_data = { | |
1201 | .parent = "l4_ick", | |
1202 | .div = 1, | |
1203 | .mult = 1, | |
1204 | }; | |
1205 | ||
1206 | static struct ti_clk ssi_l4_ick = { | |
1207 | .name = "ssi_l4_ick", | |
1208 | .clkdm_name = "core_l4_clkdm", | |
1209 | .type = TI_CLK_FIXED_FACTOR, | |
1210 | .data = &ssi_l4_ick_data, | |
1211 | }; | |
1212 | ||
1213 | static struct ti_clk_gate ssi_ick_3430es1_data = { | |
1214 | .parent = "ssi_l4_ick", | |
1215 | .bit_shift = 0, | |
1216 | .reg = 0xa10, | |
1217 | .module = TI_CLKM_CM, | |
1218 | .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, | |
1219 | }; | |
1220 | ||
1221 | static struct ti_clk ssi_ick_3430es1 = { | |
1222 | .name = "ssi_ick", | |
1223 | .clkdm_name = "core_l4_clkdm", | |
1224 | .type = TI_CLK_GATE, | |
1225 | .data = &ssi_ick_3430es1_data, | |
1226 | }; | |
1227 | ||
1228 | static struct ti_clk_gate i2c2_fck_data = { | |
1229 | .parent = "core_96m_fck", | |
1230 | .bit_shift = 16, | |
1231 | .reg = 0xa00, | |
1232 | .module = TI_CLKM_CM, | |
1233 | .flags = CLKF_WAIT, | |
1234 | }; | |
1235 | ||
1236 | static struct ti_clk i2c2_fck = { | |
1237 | .name = "i2c2_fck", | |
1238 | .clkdm_name = "core_l4_clkdm", | |
1239 | .type = TI_CLK_GATE, | |
1240 | .data = &i2c2_fck_data, | |
1241 | }; | |
1242 | ||
1243 | static struct ti_clk_divider dpll1_fck_data = { | |
1244 | .parent = "core_ck", | |
1245 | .bit_shift = 19, | |
1246 | .max_div = 7, | |
1247 | .reg = 0x940, | |
1248 | .module = TI_CLKM_CM, | |
1249 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1250 | }; | |
1251 | ||
1252 | static struct ti_clk dpll1_fck = { | |
1253 | .name = "dpll1_fck", | |
1254 | .type = TI_CLK_DIVIDER, | |
1255 | .data = &dpll1_fck_data, | |
1256 | }; | |
1257 | ||
1258 | static const char *dpll1_ck_parents[] = { | |
1259 | "sys_ck", | |
1260 | "dpll1_fck", | |
1261 | }; | |
1262 | ||
1263 | static struct ti_clk_dpll dpll1_ck_data = { | |
1264 | .num_parents = ARRAY_SIZE(dpll1_ck_parents), | |
1265 | .control_reg = 0x904, | |
1266 | .idlest_reg = 0x924, | |
1267 | .mult_div1_reg = 0x940, | |
1268 | .autoidle_reg = 0x934, | |
1269 | .module = TI_CLKM_CM, | |
1270 | .parents = dpll1_ck_parents, | |
1271 | .freqsel_mask = 0xf0, | |
1272 | .modes = 0xa0, | |
1273 | .div1_mask = 0x7f, | |
1274 | .idlest_mask = 0x1, | |
1275 | .auto_recal_bit = 0x3, | |
1276 | .max_divider = 0x80, | |
1277 | .min_divider = 0x1, | |
1278 | .recal_en_bit = 0x7, | |
1279 | .max_multiplier = 0x7ff, | |
1280 | .enable_mask = 0x7, | |
1281 | .mult_mask = 0x7ff00, | |
1282 | .recal_st_bit = 0x7, | |
1283 | .autoidle_mask = 0x7, | |
1284 | }; | |
1285 | ||
1286 | static struct ti_clk dpll1_ck = { | |
1287 | .name = "dpll1_ck", | |
1288 | .clkdm_name = "dpll1_clkdm", | |
1289 | .type = TI_CLK_DPLL, | |
1290 | .data = &dpll1_ck_data, | |
1291 | }; | |
1292 | ||
1293 | static struct ti_clk_fixed secure_32k_fck_data = { | |
1294 | .frequency = 32768, | |
1295 | }; | |
1296 | ||
1297 | static struct ti_clk secure_32k_fck = { | |
1298 | .name = "secure_32k_fck", | |
1299 | .type = TI_CLK_FIXED, | |
1300 | .data = &secure_32k_fck_data, | |
1301 | }; | |
1302 | ||
1303 | static struct ti_clk_gate gpio5_ick_data = { | |
1304 | .parent = "per_l4_ick", | |
1305 | .bit_shift = 16, | |
1306 | .reg = 0x1010, | |
1307 | .module = TI_CLKM_CM, | |
1308 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1309 | }; | |
1310 | ||
1311 | static struct ti_clk gpio5_ick = { | |
1312 | .name = "gpio5_ick", | |
1313 | .clkdm_name = "per_clkdm", | |
1314 | .type = TI_CLK_GATE, | |
1315 | .data = &gpio5_ick_data, | |
1316 | }; | |
1317 | ||
1318 | static struct ti_clk_divider dpll4_m4_ck_data = { | |
1319 | .parent = "dpll4_ck", | |
1320 | .max_div = 32, | |
1321 | .reg = 0xe40, | |
1322 | .module = TI_CLKM_CM, | |
1323 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1324 | }; | |
1325 | ||
1326 | static struct ti_clk dpll4_m4_ck = { | |
1327 | .name = "dpll4_m4_ck", | |
1328 | .type = TI_CLK_DIVIDER, | |
1329 | .data = &dpll4_m4_ck_data, | |
1330 | }; | |
1331 | ||
1332 | static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = { | |
1333 | .parent = "dpll4_m4_ck", | |
1334 | .div = 1, | |
1335 | .mult = 2, | |
1336 | .flags = CLKF_SET_RATE_PARENT, | |
1337 | }; | |
1338 | ||
1339 | static struct ti_clk dpll4_m4x2_mul_ck = { | |
1340 | .name = "dpll4_m4x2_mul_ck", | |
1341 | .type = TI_CLK_FIXED_FACTOR, | |
1342 | .data = &dpll4_m4x2_mul_ck_data, | |
1343 | }; | |
1344 | ||
1345 | static struct ti_clk_gate dpll4_m4x2_ck_data = { | |
1346 | .parent = "dpll4_m4x2_mul_ck", | |
1347 | .bit_shift = 0x1d, | |
1348 | .reg = 0xd00, | |
1349 | .module = TI_CLKM_CM, | |
1350 | .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE, | |
1351 | }; | |
1352 | ||
1353 | static struct ti_clk dpll4_m4x2_ck = { | |
1354 | .name = "dpll4_m4x2_ck", | |
1355 | .type = TI_CLK_GATE, | |
1356 | .data = &dpll4_m4x2_ck_data, | |
1357 | }; | |
1358 | ||
1359 | static struct ti_clk_gate dss1_alwon_fck_3430es2_data = { | |
1360 | .parent = "dpll4_m4x2_ck", | |
1361 | .bit_shift = 0, | |
1362 | .reg = 0xe00, | |
1363 | .module = TI_CLKM_CM, | |
1364 | .flags = CLKF_DSS | CLKF_SET_RATE_PARENT, | |
1365 | }; | |
1366 | ||
1367 | static struct ti_clk dss1_alwon_fck_3430es2 = { | |
1368 | .name = "dss1_alwon_fck", | |
1369 | .clkdm_name = "dss_clkdm", | |
1370 | .type = TI_CLK_GATE, | |
1371 | .data = &dss1_alwon_fck_3430es2_data, | |
1372 | }; | |
1373 | ||
1374 | static struct ti_clk_gate uart3_ick_data = { | |
1375 | .parent = "per_l4_ick", | |
1376 | .bit_shift = 11, | |
1377 | .reg = 0x1010, | |
1378 | .module = TI_CLKM_CM, | |
1379 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1380 | }; | |
1381 | ||
1382 | static struct ti_clk uart3_ick = { | |
1383 | .name = "uart3_ick", | |
1384 | .clkdm_name = "per_clkdm", | |
1385 | .type = TI_CLK_GATE, | |
1386 | .data = &uart3_ick_data, | |
1387 | }; | |
1388 | ||
1389 | static struct ti_clk_divider dpll4_m3_ck_data = { | |
1390 | .parent = "dpll4_ck", | |
1391 | .bit_shift = 8, | |
1392 | .max_div = 32, | |
1393 | .reg = 0xe40, | |
1394 | .module = TI_CLKM_CM, | |
1395 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1396 | }; | |
1397 | ||
1398 | static struct ti_clk dpll4_m3_ck = { | |
1399 | .name = "dpll4_m3_ck", | |
1400 | .type = TI_CLK_DIVIDER, | |
1401 | .data = &dpll4_m3_ck_data, | |
1402 | }; | |
1403 | ||
1404 | static struct ti_clk_gate mcbsp3_ick_data = { | |
1405 | .parent = "per_l4_ick", | |
1406 | .bit_shift = 1, | |
1407 | .reg = 0x1010, | |
1408 | .module = TI_CLKM_CM, | |
1409 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1410 | }; | |
1411 | ||
1412 | static struct ti_clk mcbsp3_ick = { | |
1413 | .name = "mcbsp3_ick", | |
1414 | .clkdm_name = "per_clkdm", | |
1415 | .type = TI_CLK_GATE, | |
1416 | .data = &mcbsp3_ick_data, | |
1417 | }; | |
1418 | ||
1419 | static struct ti_clk_gate gpio3_dbck_data = { | |
1420 | .parent = "per_32k_alwon_fck", | |
1421 | .bit_shift = 14, | |
1422 | .reg = 0x1000, | |
1423 | .module = TI_CLKM_CM, | |
1424 | }; | |
1425 | ||
1426 | static struct ti_clk gpio3_dbck = { | |
1427 | .name = "gpio3_dbck", | |
1428 | .clkdm_name = "per_clkdm", | |
1429 | .type = TI_CLK_GATE, | |
1430 | .data = &gpio3_dbck_data, | |
1431 | }; | |
1432 | ||
1433 | static struct ti_clk_gate fac_ick_data = { | |
1434 | .parent = "core_l4_ick", | |
1435 | .bit_shift = 8, | |
1436 | .reg = 0xa10, | |
1437 | .module = TI_CLKM_CM, | |
1438 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1439 | }; | |
1440 | ||
1441 | static struct ti_clk fac_ick = { | |
1442 | .name = "fac_ick", | |
1443 | .clkdm_name = "core_l4_clkdm", | |
1444 | .type = TI_CLK_GATE, | |
1445 | .data = &fac_ick_data, | |
1446 | }; | |
1447 | ||
1448 | static struct ti_clk_gate clkout2_src_gate_ck_data = { | |
1449 | .parent = "core_ck", | |
1450 | .bit_shift = 7, | |
1451 | .reg = 0xd70, | |
1452 | .module = TI_CLKM_CM, | |
1453 | .flags = CLKF_NO_WAIT, | |
1454 | }; | |
1455 | ||
1456 | static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = { | |
1457 | .parent = "dpll4_m3_ck", | |
1458 | .div = 1, | |
1459 | .mult = 2, | |
1460 | }; | |
1461 | ||
1462 | static struct ti_clk dpll4_m3x2_mul_ck = { | |
1463 | .name = "dpll4_m3x2_mul_ck", | |
1464 | .type = TI_CLK_FIXED_FACTOR, | |
1465 | .data = &dpll4_m3x2_mul_ck_data, | |
1466 | }; | |
1467 | ||
1468 | static struct ti_clk_gate dpll4_m3x2_ck_data = { | |
1469 | .parent = "dpll4_m3x2_mul_ck", | |
1470 | .bit_shift = 0x1c, | |
1471 | .reg = 0xd00, | |
1472 | .module = TI_CLKM_CM, | |
1473 | .flags = CLKF_SET_BIT_TO_DISABLE, | |
1474 | }; | |
1475 | ||
1476 | static struct ti_clk dpll4_m3x2_ck = { | |
1477 | .name = "dpll4_m3x2_ck", | |
1478 | .type = TI_CLK_GATE, | |
1479 | .data = &dpll4_m3x2_ck_data, | |
1480 | }; | |
1481 | ||
1482 | static const char *omap_54m_fck_parents[] = { | |
1483 | "dpll4_m3x2_ck", | |
1484 | "sys_altclk", | |
1485 | }; | |
1486 | ||
1487 | static struct ti_clk_mux omap_54m_fck_data = { | |
1488 | .bit_shift = 5, | |
1489 | .num_parents = ARRAY_SIZE(omap_54m_fck_parents), | |
1490 | .reg = 0xd40, | |
1491 | .module = TI_CLKM_CM, | |
1492 | .parents = omap_54m_fck_parents, | |
1493 | }; | |
1494 | ||
1495 | static struct ti_clk omap_54m_fck = { | |
1496 | .name = "omap_54m_fck", | |
1497 | .type = TI_CLK_MUX, | |
1498 | .data = &omap_54m_fck_data, | |
1499 | }; | |
1500 | ||
1501 | static const char *clkout2_src_mux_ck_parents[] = { | |
1502 | "core_ck", | |
1503 | "sys_ck", | |
1504 | "cm_96m_fck", | |
1505 | "omap_54m_fck", | |
1506 | }; | |
1507 | ||
1508 | static struct ti_clk_mux clkout2_src_mux_ck_data = { | |
1509 | .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents), | |
1510 | .reg = 0xd70, | |
1511 | .module = TI_CLKM_CM, | |
1512 | .parents = clkout2_src_mux_ck_parents, | |
1513 | }; | |
1514 | ||
1515 | static struct ti_clk_composite clkout2_src_ck_data = { | |
1516 | .mux = &clkout2_src_mux_ck_data, | |
1517 | .gate = &clkout2_src_gate_ck_data, | |
1518 | }; | |
1519 | ||
1520 | static struct ti_clk clkout2_src_ck = { | |
1521 | .name = "clkout2_src_ck", | |
1522 | .type = TI_CLK_COMPOSITE, | |
1523 | .data = &clkout2_src_ck_data, | |
1524 | }; | |
1525 | ||
1526 | static struct ti_clk_gate i2c1_fck_data = { | |
1527 | .parent = "core_96m_fck", | |
1528 | .bit_shift = 15, | |
1529 | .reg = 0xa00, | |
1530 | .module = TI_CLKM_CM, | |
1531 | .flags = CLKF_WAIT, | |
1532 | }; | |
1533 | ||
1534 | static struct ti_clk i2c1_fck = { | |
1535 | .name = "i2c1_fck", | |
1536 | .clkdm_name = "core_l4_clkdm", | |
1537 | .type = TI_CLK_GATE, | |
1538 | .data = &i2c1_fck_data, | |
1539 | }; | |
1540 | ||
1541 | static struct ti_clk_gate wdt3_fck_data = { | |
1542 | .parent = "per_32k_alwon_fck", | |
1543 | .bit_shift = 12, | |
1544 | .reg = 0x1000, | |
1545 | .module = TI_CLKM_CM, | |
1546 | .flags = CLKF_WAIT, | |
1547 | }; | |
1548 | ||
1549 | static struct ti_clk wdt3_fck = { | |
1550 | .name = "wdt3_fck", | |
1551 | .clkdm_name = "per_clkdm", | |
1552 | .type = TI_CLK_GATE, | |
1553 | .data = &wdt3_fck_data, | |
1554 | }; | |
1555 | ||
1556 | static struct ti_clk_gate gpt7_gate_fck_data = { | |
1557 | .parent = "sys_ck", | |
1558 | .bit_shift = 8, | |
1559 | .reg = 0x1000, | |
1560 | .module = TI_CLKM_CM, | |
1561 | }; | |
1562 | ||
1563 | static const char *gpt7_mux_fck_parents[] = { | |
1564 | "omap_32k_fck", | |
1565 | "sys_ck", | |
1566 | }; | |
1567 | ||
1568 | static struct ti_clk_mux gpt7_mux_fck_data = { | |
1569 | .bit_shift = 5, | |
1570 | .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents), | |
1571 | .reg = 0x1040, | |
1572 | .module = TI_CLKM_CM, | |
1573 | .parents = gpt7_mux_fck_parents, | |
1574 | }; | |
1575 | ||
1576 | static struct ti_clk_composite gpt7_fck_data = { | |
1577 | .mux = &gpt7_mux_fck_data, | |
1578 | .gate = &gpt7_gate_fck_data, | |
1579 | }; | |
1580 | ||
1581 | static struct ti_clk gpt7_fck = { | |
1582 | .name = "gpt7_fck", | |
1583 | .type = TI_CLK_COMPOSITE, | |
1584 | .data = &gpt7_fck_data, | |
1585 | }; | |
1586 | ||
1587 | static struct ti_clk_gate usb_l4_gate_ick_data = { | |
1588 | .parent = "l4_ick", | |
1589 | .bit_shift = 5, | |
1590 | .reg = 0xa10, | |
1591 | .module = TI_CLKM_CM, | |
1592 | .flags = CLKF_INTERFACE, | |
1593 | }; | |
1594 | ||
1595 | static struct ti_clk_divider usb_l4_div_ick_data = { | |
1596 | .parent = "l4_ick", | |
1597 | .bit_shift = 4, | |
1598 | .max_div = 1, | |
1599 | .reg = 0xa40, | |
1600 | .module = TI_CLKM_CM, | |
1601 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1602 | }; | |
1603 | ||
1604 | static struct ti_clk_composite usb_l4_ick_data = { | |
1605 | .gate = &usb_l4_gate_ick_data, | |
1606 | .divider = &usb_l4_div_ick_data, | |
1607 | }; | |
1608 | ||
1609 | static struct ti_clk usb_l4_ick = { | |
1610 | .name = "usb_l4_ick", | |
1611 | .type = TI_CLK_COMPOSITE, | |
1612 | .data = &usb_l4_ick_data, | |
1613 | }; | |
1614 | ||
1615 | static struct ti_clk_gate uart4_ick_data = { | |
1616 | .parent = "per_l4_ick", | |
1617 | .bit_shift = 18, | |
1618 | .reg = 0x1010, | |
1619 | .module = TI_CLKM_CM, | |
1620 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1621 | }; | |
1622 | ||
1623 | static struct ti_clk uart4_ick = { | |
1624 | .name = "uart4_ick", | |
1625 | .clkdm_name = "per_clkdm", | |
1626 | .type = TI_CLK_GATE, | |
1627 | .data = &uart4_ick_data, | |
1628 | }; | |
1629 | ||
1630 | static struct ti_clk_fixed dummy_ck_data = { | |
1631 | .frequency = 0, | |
1632 | }; | |
1633 | ||
1634 | static struct ti_clk dummy_ck = { | |
1635 | .name = "dummy_ck", | |
1636 | .type = TI_CLK_FIXED, | |
1637 | .data = &dummy_ck_data, | |
1638 | }; | |
1639 | ||
1640 | static const char *gpt3_mux_fck_parents[] = { | |
1641 | "omap_32k_fck", | |
1642 | "sys_ck", | |
1643 | }; | |
1644 | ||
1645 | static struct ti_clk_mux gpt3_mux_fck_data = { | |
1646 | .bit_shift = 1, | |
1647 | .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents), | |
1648 | .reg = 0x1040, | |
1649 | .module = TI_CLKM_CM, | |
1650 | .parents = gpt3_mux_fck_parents, | |
1651 | }; | |
1652 | ||
1653 | static struct ti_clk_gate gpt9_ick_data = { | |
1654 | .parent = "per_l4_ick", | |
1655 | .bit_shift = 10, | |
1656 | .reg = 0x1010, | |
1657 | .module = TI_CLKM_CM, | |
1658 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1659 | }; | |
1660 | ||
1661 | static struct ti_clk gpt9_ick = { | |
1662 | .name = "gpt9_ick", | |
1663 | .clkdm_name = "per_clkdm", | |
1664 | .type = TI_CLK_GATE, | |
1665 | .data = &gpt9_ick_data, | |
1666 | }; | |
1667 | ||
1668 | static struct ti_clk_gate gpt10_gate_fck_data = { | |
1669 | .parent = "sys_ck", | |
1670 | .bit_shift = 11, | |
1671 | .reg = 0xa00, | |
1672 | .module = TI_CLKM_CM, | |
1673 | }; | |
1674 | ||
1675 | static struct ti_clk_gate dss_ick_3430es1_data = { | |
1676 | .parent = "l4_ick", | |
1677 | .bit_shift = 0, | |
1678 | .reg = 0xe10, | |
1679 | .module = TI_CLKM_CM, | |
1680 | .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, | |
1681 | }; | |
1682 | ||
1683 | static struct ti_clk dss_ick_3430es1 = { | |
1684 | .name = "dss_ick", | |
1685 | .clkdm_name = "dss_clkdm", | |
1686 | .type = TI_CLK_GATE, | |
1687 | .data = &dss_ick_3430es1_data, | |
1688 | }; | |
1689 | ||
1690 | static struct ti_clk_gate gpt11_ick_data = { | |
1691 | .parent = "core_l4_ick", | |
1692 | .bit_shift = 12, | |
1693 | .reg = 0xa10, | |
1694 | .module = TI_CLKM_CM, | |
1695 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1696 | }; | |
1697 | ||
1698 | static struct ti_clk gpt11_ick = { | |
1699 | .name = "gpt11_ick", | |
1700 | .clkdm_name = "core_l4_clkdm", | |
1701 | .type = TI_CLK_GATE, | |
1702 | .data = &gpt11_ick_data, | |
1703 | }; | |
1704 | ||
1705 | static struct ti_clk_divider dpll2_fck_data = { | |
1706 | .parent = "core_ck", | |
1707 | .bit_shift = 19, | |
1708 | .max_div = 7, | |
1709 | .reg = 0x40, | |
1710 | .module = TI_CLKM_CM, | |
1711 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1712 | }; | |
1713 | ||
1714 | static struct ti_clk dpll2_fck = { | |
1715 | .name = "dpll2_fck", | |
1716 | .type = TI_CLK_DIVIDER, | |
1717 | .data = &dpll2_fck_data, | |
1718 | }; | |
1719 | ||
1720 | static struct ti_clk_gate uart1_fck_data = { | |
1721 | .parent = "core_48m_fck", | |
1722 | .bit_shift = 13, | |
1723 | .reg = 0xa00, | |
1724 | .module = TI_CLKM_CM, | |
1725 | .flags = CLKF_WAIT, | |
1726 | }; | |
1727 | ||
1728 | static struct ti_clk uart1_fck = { | |
1729 | .name = "uart1_fck", | |
1730 | .clkdm_name = "core_l4_clkdm", | |
1731 | .type = TI_CLK_GATE, | |
1732 | .data = &uart1_fck_data, | |
1733 | }; | |
1734 | ||
1735 | static struct ti_clk_gate hsotgusb_ick_3430es1_data = { | |
1736 | .parent = "core_l3_ick", | |
1737 | .bit_shift = 4, | |
1738 | .reg = 0xa10, | |
1739 | .module = TI_CLKM_CM, | |
1740 | .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, | |
1741 | }; | |
1742 | ||
1743 | static struct ti_clk hsotgusb_ick_3430es1 = { | |
1744 | .name = "hsotgusb_ick_3430es1", | |
1745 | .clkdm_name = "core_l3_clkdm", | |
1746 | .type = TI_CLK_GATE, | |
1747 | .data = &hsotgusb_ick_3430es1_data, | |
1748 | }; | |
1749 | ||
1750 | static struct ti_clk_gate gpio2_ick_data = { | |
1751 | .parent = "per_l4_ick", | |
1752 | .bit_shift = 13, | |
1753 | .reg = 0x1010, | |
1754 | .module = TI_CLKM_CM, | |
1755 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1756 | }; | |
1757 | ||
1758 | static struct ti_clk gpio2_ick = { | |
1759 | .name = "gpio2_ick", | |
1760 | .clkdm_name = "per_clkdm", | |
1761 | .type = TI_CLK_GATE, | |
1762 | .data = &gpio2_ick_data, | |
1763 | }; | |
1764 | ||
1765 | static struct ti_clk_gate mmchs1_ick_data = { | |
1766 | .parent = "core_l4_ick", | |
1767 | .bit_shift = 24, | |
1768 | .reg = 0xa10, | |
1769 | .module = TI_CLKM_CM, | |
1770 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1771 | }; | |
1772 | ||
1773 | static struct ti_clk mmchs1_ick = { | |
1774 | .name = "mmchs1_ick", | |
1775 | .clkdm_name = "core_l4_clkdm", | |
1776 | .type = TI_CLK_GATE, | |
1777 | .data = &mmchs1_ick_data, | |
1778 | }; | |
1779 | ||
1780 | static struct ti_clk_gate modem_fck_data = { | |
1781 | .parent = "sys_ck", | |
1782 | .bit_shift = 31, | |
1783 | .reg = 0xa00, | |
1784 | .module = TI_CLKM_CM, | |
1785 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1786 | }; | |
1787 | ||
1788 | static struct ti_clk modem_fck = { | |
1789 | .name = "modem_fck", | |
1790 | .clkdm_name = "d2d_clkdm", | |
1791 | .type = TI_CLK_GATE, | |
1792 | .data = &modem_fck_data, | |
1793 | }; | |
1794 | ||
1795 | static struct ti_clk_gate mcbsp4_ick_data = { | |
1796 | .parent = "per_l4_ick", | |
1797 | .bit_shift = 2, | |
1798 | .reg = 0x1010, | |
1799 | .module = TI_CLKM_CM, | |
1800 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1801 | }; | |
1802 | ||
1803 | static struct ti_clk mcbsp4_ick = { | |
1804 | .name = "mcbsp4_ick", | |
1805 | .clkdm_name = "per_clkdm", | |
1806 | .type = TI_CLK_GATE, | |
1807 | .data = &mcbsp4_ick_data, | |
1808 | }; | |
1809 | ||
1810 | static struct ti_clk_gate gpio1_ick_data = { | |
1811 | .parent = "wkup_l4_ick", | |
1812 | .bit_shift = 3, | |
1813 | .reg = 0xc10, | |
1814 | .module = TI_CLKM_CM, | |
1815 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
1816 | }; | |
1817 | ||
1818 | static struct ti_clk gpio1_ick = { | |
1819 | .name = "gpio1_ick", | |
1820 | .clkdm_name = "wkup_clkdm", | |
1821 | .type = TI_CLK_GATE, | |
1822 | .data = &gpio1_ick_data, | |
1823 | }; | |
1824 | ||
1825 | static const char *gpt6_mux_fck_parents[] = { | |
1826 | "omap_32k_fck", | |
1827 | "sys_ck", | |
1828 | }; | |
1829 | ||
1830 | static struct ti_clk_mux gpt6_mux_fck_data = { | |
1831 | .bit_shift = 4, | |
1832 | .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents), | |
1833 | .reg = 0x1040, | |
1834 | .module = TI_CLKM_CM, | |
1835 | .parents = gpt6_mux_fck_parents, | |
1836 | }; | |
1837 | ||
1838 | static struct ti_clk_fixed_factor dpll1_x2_ck_data = { | |
1839 | .parent = "dpll1_ck", | |
1840 | .div = 1, | |
1841 | .mult = 2, | |
1842 | }; | |
1843 | ||
1844 | static struct ti_clk dpll1_x2_ck = { | |
1845 | .name = "dpll1_x2_ck", | |
1846 | .type = TI_CLK_FIXED_FACTOR, | |
1847 | .data = &dpll1_x2_ck_data, | |
1848 | }; | |
1849 | ||
1850 | static struct ti_clk_divider dpll1_x2m2_ck_data = { | |
1851 | .parent = "dpll1_x2_ck", | |
1852 | .max_div = 31, | |
1853 | .reg = 0x944, | |
1854 | .module = TI_CLKM_CM, | |
1855 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1856 | }; | |
1857 | ||
1858 | static struct ti_clk dpll1_x2m2_ck = { | |
1859 | .name = "dpll1_x2m2_ck", | |
1860 | .type = TI_CLK_DIVIDER, | |
1861 | .data = &dpll1_x2m2_ck_data, | |
1862 | }; | |
1863 | ||
1864 | static struct ti_clk_fixed_factor mpu_ck_data = { | |
1865 | .parent = "dpll1_x2m2_ck", | |
1866 | .div = 1, | |
1867 | .mult = 1, | |
1868 | }; | |
1869 | ||
1870 | static struct ti_clk mpu_ck = { | |
1871 | .name = "mpu_ck", | |
1872 | .type = TI_CLK_FIXED_FACTOR, | |
1873 | .data = &mpu_ck_data, | |
1874 | }; | |
1875 | ||
1876 | static struct ti_clk_divider arm_fck_data = { | |
1877 | .parent = "mpu_ck", | |
1878 | .max_div = 2, | |
1879 | .reg = 0x924, | |
1880 | .module = TI_CLKM_CM, | |
1881 | }; | |
1882 | ||
1883 | static struct ti_clk arm_fck = { | |
1884 | .name = "arm_fck", | |
1885 | .type = TI_CLK_DIVIDER, | |
1886 | .data = &arm_fck_data, | |
1887 | }; | |
1888 | ||
1889 | static struct ti_clk_fixed_factor core_d3_ck_data = { | |
1890 | .parent = "core_ck", | |
1891 | .div = 3, | |
1892 | .mult = 1, | |
1893 | }; | |
1894 | ||
1895 | static struct ti_clk core_d3_ck = { | |
1896 | .name = "core_d3_ck", | |
1897 | .type = TI_CLK_FIXED_FACTOR, | |
1898 | .data = &core_d3_ck_data, | |
1899 | }; | |
1900 | ||
1901 | static struct ti_clk_gate gpt11_gate_fck_data = { | |
1902 | .parent = "sys_ck", | |
1903 | .bit_shift = 12, | |
1904 | .reg = 0xa00, | |
1905 | .module = TI_CLKM_CM, | |
1906 | }; | |
1907 | ||
1908 | static const char *gpt11_mux_fck_parents[] = { | |
1909 | "omap_32k_fck", | |
1910 | "sys_ck", | |
1911 | }; | |
1912 | ||
1913 | static struct ti_clk_mux gpt11_mux_fck_data = { | |
1914 | .bit_shift = 7, | |
1915 | .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents), | |
1916 | .reg = 0xa40, | |
1917 | .module = TI_CLKM_CM, | |
1918 | .parents = gpt11_mux_fck_parents, | |
1919 | }; | |
1920 | ||
1921 | static struct ti_clk_composite gpt11_fck_data = { | |
1922 | .mux = &gpt11_mux_fck_data, | |
1923 | .gate = &gpt11_gate_fck_data, | |
1924 | }; | |
1925 | ||
1926 | static struct ti_clk gpt11_fck = { | |
1927 | .name = "gpt11_fck", | |
1928 | .type = TI_CLK_COMPOSITE, | |
1929 | .data = &gpt11_fck_data, | |
1930 | }; | |
1931 | ||
1932 | static struct ti_clk_fixed_factor core_d6_ck_data = { | |
1933 | .parent = "core_ck", | |
1934 | .div = 6, | |
1935 | .mult = 1, | |
1936 | }; | |
1937 | ||
1938 | static struct ti_clk core_d6_ck = { | |
1939 | .name = "core_d6_ck", | |
1940 | .type = TI_CLK_FIXED_FACTOR, | |
1941 | .data = &core_d6_ck_data, | |
1942 | }; | |
1943 | ||
1944 | static struct ti_clk_gate uart4_fck_am35xx_data = { | |
1945 | .parent = "core_48m_fck", | |
1946 | .bit_shift = 23, | |
1947 | .reg = 0xa00, | |
1948 | .module = TI_CLKM_CM, | |
1949 | .flags = CLKF_WAIT, | |
1950 | }; | |
1951 | ||
1952 | static struct ti_clk uart4_fck_am35xx = { | |
1953 | .name = "uart4_fck_am35xx", | |
1954 | .clkdm_name = "core_l4_clkdm", | |
1955 | .type = TI_CLK_GATE, | |
1956 | .data = &uart4_fck_am35xx_data, | |
1957 | }; | |
1958 | ||
1959 | static struct ti_clk_gate dpll3_m3x2_ck_data = { | |
1960 | .parent = "dpll3_m3x2_mul_ck", | |
1961 | .bit_shift = 0xc, | |
1962 | .reg = 0xd00, | |
1963 | .module = TI_CLKM_CM, | |
1964 | .flags = CLKF_SET_BIT_TO_DISABLE, | |
1965 | }; | |
1966 | ||
1967 | static struct ti_clk dpll3_m3x2_ck = { | |
1968 | .name = "dpll3_m3x2_ck", | |
1969 | .type = TI_CLK_GATE, | |
1970 | .data = &dpll3_m3x2_ck_data, | |
1971 | }; | |
1972 | ||
1973 | static struct ti_clk_fixed_factor emu_core_alwon_ck_data = { | |
1974 | .parent = "dpll3_m3x2_ck", | |
1975 | .div = 1, | |
1976 | .mult = 1, | |
1977 | }; | |
1978 | ||
1979 | static struct ti_clk emu_core_alwon_ck = { | |
1980 | .name = "emu_core_alwon_ck", | |
1981 | .type = TI_CLK_FIXED_FACTOR, | |
1982 | .data = &emu_core_alwon_ck_data, | |
1983 | }; | |
1984 | ||
1985 | static struct ti_clk_divider dpll4_m6_ck_data = { | |
1986 | .parent = "dpll4_ck", | |
1987 | .bit_shift = 24, | |
1988 | .max_div = 63, | |
1989 | .reg = 0x1140, | |
1990 | .module = TI_CLKM_CM, | |
1991 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
1992 | }; | |
1993 | ||
1994 | static struct ti_clk dpll4_m6_ck = { | |
1995 | .name = "dpll4_m6_ck", | |
1996 | .type = TI_CLK_DIVIDER, | |
1997 | .data = &dpll4_m6_ck_data, | |
1998 | }; | |
1999 | ||
2000 | static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = { | |
2001 | .parent = "dpll4_m6_ck", | |
2002 | .div = 1, | |
2003 | .mult = 2, | |
2004 | }; | |
2005 | ||
2006 | static struct ti_clk dpll4_m6x2_mul_ck = { | |
2007 | .name = "dpll4_m6x2_mul_ck", | |
2008 | .type = TI_CLK_FIXED_FACTOR, | |
2009 | .data = &dpll4_m6x2_mul_ck_data, | |
2010 | }; | |
2011 | ||
2012 | static struct ti_clk_gate dpll4_m6x2_ck_data = { | |
2013 | .parent = "dpll4_m6x2_mul_ck", | |
2014 | .bit_shift = 0x1f, | |
2015 | .reg = 0xd00, | |
2016 | .module = TI_CLKM_CM, | |
2017 | .flags = CLKF_SET_BIT_TO_DISABLE, | |
2018 | }; | |
2019 | ||
2020 | static struct ti_clk dpll4_m6x2_ck = { | |
2021 | .name = "dpll4_m6x2_ck", | |
2022 | .type = TI_CLK_GATE, | |
2023 | .data = &dpll4_m6x2_ck_data, | |
2024 | }; | |
2025 | ||
2026 | static struct ti_clk_fixed_factor emu_per_alwon_ck_data = { | |
2027 | .parent = "dpll4_m6x2_ck", | |
2028 | .div = 1, | |
2029 | .mult = 1, | |
2030 | }; | |
2031 | ||
2032 | static struct ti_clk emu_per_alwon_ck = { | |
2033 | .name = "emu_per_alwon_ck", | |
2034 | .type = TI_CLK_FIXED_FACTOR, | |
2035 | .data = &emu_per_alwon_ck_data, | |
2036 | }; | |
2037 | ||
2038 | static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = { | |
2039 | .parent = "mpu_ck", | |
2040 | .div = 1, | |
2041 | .mult = 1, | |
2042 | }; | |
2043 | ||
2044 | static struct ti_clk emu_mpu_alwon_ck = { | |
2045 | .name = "emu_mpu_alwon_ck", | |
2046 | .type = TI_CLK_FIXED_FACTOR, | |
2047 | .data = &emu_mpu_alwon_ck_data, | |
2048 | }; | |
2049 | ||
2050 | static const char *emu_src_mux_ck_parents[] = { | |
2051 | "sys_ck", | |
2052 | "emu_core_alwon_ck", | |
2053 | "emu_per_alwon_ck", | |
2054 | "emu_mpu_alwon_ck", | |
2055 | }; | |
2056 | ||
2057 | static struct ti_clk_mux emu_src_mux_ck_data = { | |
2058 | .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents), | |
2059 | .reg = 0x1140, | |
2060 | .module = TI_CLKM_CM, | |
2061 | .parents = emu_src_mux_ck_parents, | |
2062 | }; | |
2063 | ||
2064 | static struct ti_clk emu_src_mux_ck = { | |
2065 | .name = "emu_src_mux_ck", | |
2066 | .type = TI_CLK_MUX, | |
2067 | .data = &emu_src_mux_ck_data, | |
2068 | }; | |
2069 | ||
2070 | static struct ti_clk_gate emu_src_ck_data = { | |
2071 | .parent = "emu_src_mux_ck", | |
2072 | .flags = CLKF_CLKDM, | |
2073 | }; | |
2074 | ||
2075 | static struct ti_clk emu_src_ck = { | |
2076 | .name = "emu_src_ck", | |
2077 | .clkdm_name = "emu_clkdm", | |
2078 | .type = TI_CLK_GATE, | |
2079 | .data = &emu_src_ck_data, | |
2080 | }; | |
2081 | ||
2082 | static struct ti_clk_divider atclk_fck_data = { | |
2083 | .parent = "emu_src_ck", | |
2084 | .bit_shift = 4, | |
2085 | .max_div = 3, | |
2086 | .reg = 0x1140, | |
2087 | .module = TI_CLKM_CM, | |
2088 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
2089 | }; | |
2090 | ||
2091 | static struct ti_clk atclk_fck = { | |
2092 | .name = "atclk_fck", | |
2093 | .type = TI_CLK_DIVIDER, | |
2094 | .data = &atclk_fck_data, | |
2095 | }; | |
2096 | ||
2097 | static struct ti_clk_gate ipss_ick_data = { | |
2098 | .parent = "core_l3_ick", | |
2099 | .bit_shift = 4, | |
2100 | .reg = 0xa10, | |
2101 | .module = TI_CLKM_CM, | |
2102 | .flags = CLKF_AM35XX | CLKF_INTERFACE, | |
2103 | }; | |
2104 | ||
2105 | static struct ti_clk ipss_ick = { | |
2106 | .name = "ipss_ick", | |
2107 | .clkdm_name = "core_l3_clkdm", | |
2108 | .type = TI_CLK_GATE, | |
2109 | .data = &ipss_ick_data, | |
2110 | }; | |
2111 | ||
2112 | static struct ti_clk_gate emac_ick_data = { | |
2113 | .parent = "ipss_ick", | |
2114 | .bit_shift = 1, | |
2115 | .reg = 0x59c, | |
2116 | .module = TI_CLKM_SCRM, | |
2117 | .flags = CLKF_AM35XX, | |
2118 | }; | |
2119 | ||
2120 | static struct ti_clk emac_ick = { | |
2121 | .name = "emac_ick", | |
2122 | .clkdm_name = "core_l3_clkdm", | |
2123 | .type = TI_CLK_GATE, | |
2124 | .data = &emac_ick_data, | |
2125 | }; | |
2126 | ||
2127 | static struct ti_clk_gate vpfe_ick_data = { | |
2128 | .parent = "ipss_ick", | |
2129 | .bit_shift = 2, | |
2130 | .reg = 0x59c, | |
2131 | .module = TI_CLKM_SCRM, | |
2132 | .flags = CLKF_AM35XX, | |
2133 | }; | |
2134 | ||
2135 | static struct ti_clk vpfe_ick = { | |
2136 | .name = "vpfe_ick", | |
2137 | .clkdm_name = "core_l3_clkdm", | |
2138 | .type = TI_CLK_GATE, | |
2139 | .data = &vpfe_ick_data, | |
2140 | }; | |
2141 | ||
2142 | static const char *dpll2_ck_parents[] = { | |
2143 | "sys_ck", | |
2144 | "dpll2_fck", | |
2145 | }; | |
2146 | ||
2147 | static struct ti_clk_dpll dpll2_ck_data = { | |
2148 | .num_parents = ARRAY_SIZE(dpll2_ck_parents), | |
2149 | .control_reg = 0x4, | |
2150 | .idlest_reg = 0x24, | |
2151 | .mult_div1_reg = 0x40, | |
2152 | .autoidle_reg = 0x34, | |
2153 | .module = TI_CLKM_CM, | |
2154 | .parents = dpll2_ck_parents, | |
2155 | .freqsel_mask = 0xf0, | |
2156 | .modes = 0xa2, | |
2157 | .div1_mask = 0x7f, | |
2158 | .idlest_mask = 0x1, | |
2159 | .auto_recal_bit = 0x3, | |
2160 | .max_divider = 0x80, | |
2161 | .min_divider = 0x1, | |
2162 | .recal_en_bit = 0x8, | |
2163 | .max_multiplier = 0x7ff, | |
2164 | .enable_mask = 0x7, | |
2165 | .mult_mask = 0x7ff00, | |
2166 | .recal_st_bit = 0x8, | |
2167 | .autoidle_mask = 0x7, | |
2168 | }; | |
2169 | ||
2170 | static struct ti_clk dpll2_ck = { | |
2171 | .name = "dpll2_ck", | |
2172 | .clkdm_name = "dpll2_clkdm", | |
2173 | .type = TI_CLK_DPLL, | |
2174 | .data = &dpll2_ck_data, | |
2175 | }; | |
2176 | ||
2177 | static struct ti_clk_divider dpll2_m2_ck_data = { | |
2178 | .parent = "dpll2_ck", | |
2179 | .max_div = 31, | |
2180 | .reg = 0x44, | |
2181 | .module = TI_CLKM_CM, | |
2182 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
2183 | }; | |
2184 | ||
2185 | static struct ti_clk dpll2_m2_ck = { | |
2186 | .name = "dpll2_m2_ck", | |
2187 | .type = TI_CLK_DIVIDER, | |
2188 | .data = &dpll2_m2_ck_data, | |
2189 | }; | |
2190 | ||
2191 | static const char *mcbsp4_mux_fck_parents[] = { | |
2192 | "per_96m_fck", | |
2193 | "mcbsp_clks", | |
2194 | }; | |
2195 | ||
2196 | static struct ti_clk_mux mcbsp4_mux_fck_data = { | |
2197 | .bit_shift = 2, | |
2198 | .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents), | |
2199 | .reg = 0x2d8, | |
2200 | .module = TI_CLKM_SCRM, | |
2201 | .parents = mcbsp4_mux_fck_parents, | |
2202 | }; | |
2203 | ||
2204 | static const char *mcbsp1_mux_fck_parents[] = { | |
2205 | "core_96m_fck", | |
2206 | "mcbsp_clks", | |
2207 | }; | |
2208 | ||
2209 | static struct ti_clk_mux mcbsp1_mux_fck_data = { | |
2210 | .bit_shift = 2, | |
2211 | .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents), | |
2212 | .reg = 0x274, | |
2213 | .module = TI_CLKM_SCRM, | |
2214 | .parents = mcbsp1_mux_fck_parents, | |
2215 | }; | |
2216 | ||
2217 | static struct ti_clk_gate gpt8_gate_fck_data = { | |
2218 | .parent = "sys_ck", | |
2219 | .bit_shift = 9, | |
2220 | .reg = 0x1000, | |
2221 | .module = TI_CLKM_CM, | |
2222 | }; | |
2223 | ||
2224 | static struct ti_clk_gate gpt8_ick_data = { | |
2225 | .parent = "per_l4_ick", | |
2226 | .bit_shift = 9, | |
2227 | .reg = 0x1010, | |
2228 | .module = TI_CLKM_CM, | |
2229 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2230 | }; | |
2231 | ||
2232 | static struct ti_clk gpt8_ick = { | |
2233 | .name = "gpt8_ick", | |
2234 | .clkdm_name = "per_clkdm", | |
2235 | .type = TI_CLK_GATE, | |
2236 | .data = &gpt8_ick_data, | |
2237 | }; | |
2238 | ||
2239 | static const char *gpt10_mux_fck_parents[] = { | |
2240 | "omap_32k_fck", | |
2241 | "sys_ck", | |
2242 | }; | |
2243 | ||
2244 | static struct ti_clk_mux gpt10_mux_fck_data = { | |
2245 | .bit_shift = 6, | |
2246 | .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents), | |
2247 | .reg = 0xa40, | |
2248 | .module = TI_CLKM_CM, | |
2249 | .parents = gpt10_mux_fck_parents, | |
2250 | }; | |
2251 | ||
2252 | static struct ti_clk_gate mmchs3_ick_data = { | |
2253 | .parent = "core_l4_ick", | |
2254 | .bit_shift = 30, | |
2255 | .reg = 0xa10, | |
2256 | .module = TI_CLKM_CM, | |
2257 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2258 | }; | |
2259 | ||
2260 | static struct ti_clk mmchs3_ick = { | |
2261 | .name = "mmchs3_ick", | |
2262 | .clkdm_name = "core_l4_clkdm", | |
2263 | .type = TI_CLK_GATE, | |
2264 | .data = &mmchs3_ick_data, | |
2265 | }; | |
2266 | ||
2267 | static struct ti_clk_gate gpio3_ick_data = { | |
2268 | .parent = "per_l4_ick", | |
2269 | .bit_shift = 14, | |
2270 | .reg = 0x1010, | |
2271 | .module = TI_CLKM_CM, | |
2272 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2273 | }; | |
2274 | ||
2275 | static struct ti_clk gpio3_ick = { | |
2276 | .name = "gpio3_ick", | |
2277 | .clkdm_name = "per_clkdm", | |
2278 | .type = TI_CLK_GATE, | |
2279 | .data = &gpio3_ick_data, | |
2280 | }; | |
2281 | ||
2282 | static const char *traceclk_src_fck_parents[] = { | |
2283 | "sys_ck", | |
2284 | "emu_core_alwon_ck", | |
2285 | "emu_per_alwon_ck", | |
2286 | "emu_mpu_alwon_ck", | |
2287 | }; | |
2288 | ||
2289 | static struct ti_clk_mux traceclk_src_fck_data = { | |
2290 | .bit_shift = 2, | |
2291 | .num_parents = ARRAY_SIZE(traceclk_src_fck_parents), | |
2292 | .reg = 0x1140, | |
2293 | .module = TI_CLKM_CM, | |
2294 | .parents = traceclk_src_fck_parents, | |
2295 | }; | |
2296 | ||
2297 | static struct ti_clk traceclk_src_fck = { | |
2298 | .name = "traceclk_src_fck", | |
2299 | .type = TI_CLK_MUX, | |
2300 | .data = &traceclk_src_fck_data, | |
2301 | }; | |
2302 | ||
2303 | static struct ti_clk_divider traceclk_fck_data = { | |
2304 | .parent = "traceclk_src_fck", | |
2305 | .bit_shift = 11, | |
2306 | .max_div = 7, | |
2307 | .reg = 0x1140, | |
2308 | .module = TI_CLKM_CM, | |
2309 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
2310 | }; | |
2311 | ||
2312 | static struct ti_clk traceclk_fck = { | |
2313 | .name = "traceclk_fck", | |
2314 | .type = TI_CLK_DIVIDER, | |
2315 | .data = &traceclk_fck_data, | |
2316 | }; | |
2317 | ||
2318 | static struct ti_clk_gate mcbsp5_gate_fck_data = { | |
2319 | .parent = "mcbsp_clks", | |
2320 | .bit_shift = 10, | |
2321 | .reg = 0xa00, | |
2322 | .module = TI_CLKM_CM, | |
2323 | }; | |
2324 | ||
2325 | static struct ti_clk_gate sad2d_ick_data = { | |
2326 | .parent = "l3_ick", | |
2327 | .bit_shift = 3, | |
2328 | .reg = 0xa10, | |
2329 | .module = TI_CLKM_CM, | |
2330 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2331 | }; | |
2332 | ||
2333 | static struct ti_clk sad2d_ick = { | |
2334 | .name = "sad2d_ick", | |
2335 | .clkdm_name = "d2d_clkdm", | |
2336 | .type = TI_CLK_GATE, | |
2337 | .data = &sad2d_ick_data, | |
2338 | }; | |
2339 | ||
2340 | static const char *gpt1_mux_fck_parents[] = { | |
2341 | "omap_32k_fck", | |
2342 | "sys_ck", | |
2343 | }; | |
2344 | ||
2345 | static struct ti_clk_mux gpt1_mux_fck_data = { | |
2346 | .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents), | |
2347 | .reg = 0xc40, | |
2348 | .module = TI_CLKM_CM, | |
2349 | .parents = gpt1_mux_fck_parents, | |
2350 | }; | |
2351 | ||
2352 | static struct ti_clk_gate hecc_ck_data = { | |
2353 | .parent = "sys_ck", | |
2354 | .bit_shift = 3, | |
2355 | .reg = 0x59c, | |
2356 | .module = TI_CLKM_SCRM, | |
2357 | .flags = CLKF_AM35XX, | |
2358 | }; | |
2359 | ||
2360 | static struct ti_clk hecc_ck = { | |
2361 | .name = "hecc_ck", | |
2362 | .clkdm_name = "core_l3_clkdm", | |
2363 | .type = TI_CLK_GATE, | |
2364 | .data = &hecc_ck_data, | |
2365 | }; | |
2366 | ||
2367 | static struct ti_clk_gate gpt1_gate_fck_data = { | |
2368 | .parent = "sys_ck", | |
2369 | .bit_shift = 0, | |
2370 | .reg = 0xc00, | |
2371 | .module = TI_CLKM_CM, | |
2372 | }; | |
2373 | ||
2374 | static struct ti_clk_composite gpt1_fck_data = { | |
2375 | .mux = &gpt1_mux_fck_data, | |
2376 | .gate = &gpt1_gate_fck_data, | |
2377 | }; | |
2378 | ||
2379 | static struct ti_clk gpt1_fck = { | |
2380 | .name = "gpt1_fck", | |
2381 | .type = TI_CLK_COMPOSITE, | |
2382 | .data = &gpt1_fck_data, | |
2383 | }; | |
2384 | ||
2385 | static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = { | |
2386 | .parent = "dpll4_m2x2_mul_ck", | |
2387 | .bit_shift = 0x1b, | |
2388 | .reg = 0xd00, | |
2389 | .module = TI_CLKM_CM, | |
2390 | .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, | |
2391 | }; | |
2392 | ||
2393 | static struct ti_clk dpll4_m2x2_ck_omap36xx = { | |
2394 | .name = "dpll4_m2x2_ck", | |
2395 | .type = TI_CLK_GATE, | |
2396 | .data = &dpll4_m2x2_ck_omap36xx_data, | |
2397 | .patch = &dpll4_m2x2_ck, | |
2398 | }; | |
2399 | ||
2400 | static struct ti_clk_divider gfx_l3_fck_data = { | |
2401 | .parent = "l3_ick", | |
2402 | .max_div = 7, | |
2403 | .reg = 0xb40, | |
2404 | .module = TI_CLKM_CM, | |
2405 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
2406 | }; | |
2407 | ||
2408 | static struct ti_clk gfx_l3_fck = { | |
2409 | .name = "gfx_l3_fck", | |
2410 | .type = TI_CLK_DIVIDER, | |
2411 | .data = &gfx_l3_fck_data, | |
2412 | }; | |
2413 | ||
2414 | static struct ti_clk_gate gfx_cg1_ck_data = { | |
2415 | .parent = "gfx_l3_fck", | |
2416 | .bit_shift = 1, | |
2417 | .reg = 0xb00, | |
2418 | .module = TI_CLKM_CM, | |
2419 | .flags = CLKF_WAIT, | |
2420 | }; | |
2421 | ||
2422 | static struct ti_clk gfx_cg1_ck = { | |
2423 | .name = "gfx_cg1_ck", | |
2424 | .clkdm_name = "gfx_3430es1_clkdm", | |
2425 | .type = TI_CLK_GATE, | |
2426 | .data = &gfx_cg1_ck_data, | |
2427 | }; | |
2428 | ||
2429 | static struct ti_clk_gate mailboxes_ick_data = { | |
2430 | .parent = "core_l4_ick", | |
2431 | .bit_shift = 7, | |
2432 | .reg = 0xa10, | |
2433 | .module = TI_CLKM_CM, | |
2434 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2435 | }; | |
2436 | ||
2437 | static struct ti_clk mailboxes_ick = { | |
2438 | .name = "mailboxes_ick", | |
2439 | .clkdm_name = "core_l4_clkdm", | |
2440 | .type = TI_CLK_GATE, | |
2441 | .data = &mailboxes_ick_data, | |
2442 | }; | |
2443 | ||
2444 | static struct ti_clk_gate sha11_ick_data = { | |
2445 | .parent = "security_l4_ick2", | |
2446 | .bit_shift = 1, | |
2447 | .reg = 0xa14, | |
2448 | .module = TI_CLKM_CM, | |
2449 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2450 | }; | |
2451 | ||
2452 | static struct ti_clk sha11_ick = { | |
2453 | .name = "sha11_ick", | |
2454 | .type = TI_CLK_GATE, | |
2455 | .data = &sha11_ick_data, | |
2456 | }; | |
2457 | ||
2458 | static struct ti_clk_gate hsotgusb_ick_am35xx_data = { | |
2459 | .parent = "ipss_ick", | |
2460 | .bit_shift = 0, | |
2461 | .reg = 0x59c, | |
2462 | .module = TI_CLKM_SCRM, | |
2463 | .flags = CLKF_AM35XX, | |
2464 | }; | |
2465 | ||
2466 | static struct ti_clk hsotgusb_ick_am35xx = { | |
2467 | .name = "hsotgusb_ick_am35xx", | |
2468 | .clkdm_name = "core_l3_clkdm", | |
2469 | .type = TI_CLK_GATE, | |
2470 | .data = &hsotgusb_ick_am35xx_data, | |
2471 | }; | |
2472 | ||
2473 | static struct ti_clk_gate mmchs3_fck_data = { | |
2474 | .parent = "core_96m_fck", | |
2475 | .bit_shift = 30, | |
2476 | .reg = 0xa00, | |
2477 | .module = TI_CLKM_CM, | |
2478 | .flags = CLKF_WAIT, | |
2479 | }; | |
2480 | ||
2481 | static struct ti_clk mmchs3_fck = { | |
2482 | .name = "mmchs3_fck", | |
2483 | .clkdm_name = "core_l4_clkdm", | |
2484 | .type = TI_CLK_GATE, | |
2485 | .data = &mmchs3_fck_data, | |
2486 | }; | |
2487 | ||
2488 | static struct ti_clk_divider pclk_fck_data = { | |
2489 | .parent = "emu_src_ck", | |
2490 | .bit_shift = 8, | |
2491 | .max_div = 7, | |
2492 | .reg = 0x1140, | |
2493 | .module = TI_CLKM_CM, | |
2494 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
2495 | }; | |
2496 | ||
2497 | static struct ti_clk pclk_fck = { | |
2498 | .name = "pclk_fck", | |
2499 | .type = TI_CLK_DIVIDER, | |
2500 | .data = &pclk_fck_data, | |
2501 | }; | |
2502 | ||
2503 | static const char *dpll4_ck_omap36xx_parents[] = { | |
2504 | "sys_ck", | |
2505 | "sys_ck", | |
2506 | }; | |
2507 | ||
2508 | static struct ti_clk_dpll dpll4_ck_omap36xx_data = { | |
2509 | .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents), | |
2510 | .control_reg = 0xd00, | |
2511 | .idlest_reg = 0xd20, | |
2512 | .mult_div1_reg = 0xd44, | |
2513 | .autoidle_reg = 0xd30, | |
2514 | .module = TI_CLKM_CM, | |
2515 | .parents = dpll4_ck_omap36xx_parents, | |
2516 | .modes = 0x82, | |
2517 | .div1_mask = 0x7f, | |
2518 | .idlest_mask = 0x2, | |
2519 | .auto_recal_bit = 0x13, | |
2520 | .max_divider = 0x80, | |
2521 | .min_divider = 0x1, | |
2522 | .recal_en_bit = 0x6, | |
2523 | .max_multiplier = 0xfff, | |
2524 | .enable_mask = 0x70000, | |
2525 | .mult_mask = 0xfff00, | |
2526 | .recal_st_bit = 0x6, | |
2527 | .autoidle_mask = 0x38, | |
2528 | .sddiv_mask = 0xff000000, | |
2529 | .dco_mask = 0xe00000, | |
2530 | .flags = CLKF_PER | CLKF_J_TYPE, | |
2531 | }; | |
2532 | ||
2533 | static struct ti_clk dpll4_ck_omap36xx = { | |
2534 | .name = "dpll4_ck", | |
2535 | .type = TI_CLK_DPLL, | |
2536 | .data = &dpll4_ck_omap36xx_data, | |
2537 | .patch = &dpll4_ck, | |
2538 | }; | |
2539 | ||
2540 | static struct ti_clk_gate uart3_fck_data = { | |
2541 | .parent = "per_48m_fck", | |
2542 | .bit_shift = 11, | |
2543 | .reg = 0x1000, | |
2544 | .module = TI_CLKM_CM, | |
2545 | .flags = CLKF_WAIT, | |
2546 | }; | |
2547 | ||
2548 | static struct ti_clk uart3_fck = { | |
2549 | .name = "uart3_fck", | |
2550 | .clkdm_name = "per_clkdm", | |
2551 | .type = TI_CLK_GATE, | |
2552 | .data = &uart3_fck_data, | |
2553 | }; | |
2554 | ||
2555 | static struct ti_clk_fixed_factor wkup_32k_fck_data = { | |
2556 | .parent = "omap_32k_fck", | |
2557 | .div = 1, | |
2558 | .mult = 1, | |
2559 | }; | |
2560 | ||
2561 | static struct ti_clk wkup_32k_fck = { | |
2562 | .name = "wkup_32k_fck", | |
2563 | .type = TI_CLK_FIXED_FACTOR, | |
2564 | .data = &wkup_32k_fck_data, | |
2565 | }; | |
2566 | ||
2567 | static struct ti_clk_gate sys_clkout1_data = { | |
2568 | .parent = "osc_sys_ck", | |
2569 | .bit_shift = 7, | |
2570 | .reg = 0xd70, | |
2571 | .module = TI_CLKM_PRM, | |
2572 | }; | |
2573 | ||
2574 | static struct ti_clk sys_clkout1 = { | |
2575 | .name = "sys_clkout1", | |
2576 | .type = TI_CLK_GATE, | |
2577 | .data = &sys_clkout1_data, | |
2578 | }; | |
2579 | ||
2580 | static struct ti_clk_fixed_factor gpmc_fck_data = { | |
2581 | .parent = "core_l3_ick", | |
2582 | .div = 1, | |
2583 | .mult = 1, | |
2584 | }; | |
2585 | ||
2586 | static struct ti_clk gpmc_fck = { | |
2587 | .name = "gpmc_fck", | |
2588 | .type = TI_CLK_FIXED_FACTOR, | |
2589 | .data = &gpmc_fck_data, | |
2590 | }; | |
2591 | ||
2592 | static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = { | |
2593 | .parent = "dpll5_m2_ck", | |
2594 | .div = 20, | |
2595 | .mult = 1, | |
2596 | }; | |
2597 | ||
2598 | static struct ti_clk dpll5_m2_d20_ck = { | |
2599 | .name = "dpll5_m2_d20_ck", | |
2600 | .type = TI_CLK_FIXED_FACTOR, | |
2601 | .data = &dpll5_m2_d20_ck_data, | |
2602 | }; | |
2603 | ||
2604 | static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = { | |
2605 | .parent = "dpll4_m5x2_mul_ck", | |
2606 | .bit_shift = 0x1e, | |
2607 | .reg = 0xd00, | |
2608 | .module = TI_CLKM_CM, | |
2609 | .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE, | |
2610 | }; | |
2611 | ||
2612 | static struct ti_clk dpll4_m5x2_ck_omap36xx = { | |
2613 | .name = "dpll4_m5x2_ck", | |
2614 | .type = TI_CLK_GATE, | |
2615 | .data = &dpll4_m5x2_ck_omap36xx_data, | |
2616 | .patch = &dpll4_m5x2_ck, | |
2617 | }; | |
2618 | ||
2619 | static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = { | |
2620 | .parent = "corex2_fck", | |
2621 | .bit_shift = 0, | |
2622 | .reg = 0xa00, | |
2623 | .module = TI_CLKM_CM, | |
2624 | .flags = CLKF_NO_WAIT, | |
2625 | }; | |
2626 | ||
2627 | static struct ti_clk_gate uart1_ick_data = { | |
2628 | .parent = "core_l4_ick", | |
2629 | .bit_shift = 13, | |
2630 | .reg = 0xa10, | |
2631 | .module = TI_CLKM_CM, | |
2632 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2633 | }; | |
2634 | ||
2635 | static struct ti_clk uart1_ick = { | |
2636 | .name = "uart1_ick", | |
2637 | .clkdm_name = "core_l4_clkdm", | |
2638 | .type = TI_CLK_GATE, | |
2639 | .data = &uart1_ick_data, | |
2640 | }; | |
2641 | ||
2642 | static struct ti_clk_gate iva2_ck_data = { | |
2643 | .parent = "dpll2_m2_ck", | |
2644 | .bit_shift = 0, | |
2645 | .reg = 0x0, | |
2646 | .module = TI_CLKM_CM, | |
2647 | .flags = CLKF_WAIT, | |
2648 | }; | |
2649 | ||
2650 | static struct ti_clk iva2_ck = { | |
2651 | .name = "iva2_ck", | |
2652 | .clkdm_name = "iva2_clkdm", | |
2653 | .type = TI_CLK_GATE, | |
2654 | .data = &iva2_ck_data, | |
2655 | }; | |
2656 | ||
2657 | static struct ti_clk_gate pka_ick_data = { | |
2658 | .parent = "security_l3_ick", | |
2659 | .bit_shift = 4, | |
2660 | .reg = 0xa14, | |
2661 | .module = TI_CLKM_CM, | |
2662 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2663 | }; | |
2664 | ||
2665 | static struct ti_clk pka_ick = { | |
2666 | .name = "pka_ick", | |
2667 | .type = TI_CLK_GATE, | |
2668 | .data = &pka_ick_data, | |
2669 | }; | |
2670 | ||
2671 | static struct ti_clk_gate gpt12_ick_data = { | |
2672 | .parent = "wkup_l4_ick", | |
2673 | .bit_shift = 1, | |
2674 | .reg = 0xc10, | |
2675 | .module = TI_CLKM_CM, | |
2676 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2677 | }; | |
2678 | ||
2679 | static struct ti_clk gpt12_ick = { | |
2680 | .name = "gpt12_ick", | |
2681 | .clkdm_name = "wkup_clkdm", | |
2682 | .type = TI_CLK_GATE, | |
2683 | .data = &gpt12_ick_data, | |
2684 | }; | |
2685 | ||
2686 | static const char *mcbsp5_mux_fck_parents[] = { | |
2687 | "core_96m_fck", | |
2688 | "mcbsp_clks", | |
2689 | }; | |
2690 | ||
2691 | static struct ti_clk_mux mcbsp5_mux_fck_data = { | |
2692 | .bit_shift = 4, | |
2693 | .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents), | |
2694 | .reg = 0x2d8, | |
2695 | .module = TI_CLKM_SCRM, | |
2696 | .parents = mcbsp5_mux_fck_parents, | |
2697 | }; | |
2698 | ||
2699 | static struct ti_clk_composite mcbsp5_fck_data = { | |
2700 | .mux = &mcbsp5_mux_fck_data, | |
2701 | .gate = &mcbsp5_gate_fck_data, | |
2702 | }; | |
2703 | ||
2704 | static struct ti_clk mcbsp5_fck = { | |
2705 | .name = "mcbsp5_fck", | |
2706 | .type = TI_CLK_COMPOSITE, | |
2707 | .data = &mcbsp5_fck_data, | |
2708 | }; | |
2709 | ||
2710 | static struct ti_clk_gate usbhost_48m_fck_data = { | |
2711 | .parent = "omap_48m_fck", | |
2712 | .bit_shift = 0, | |
2713 | .reg = 0x1400, | |
2714 | .module = TI_CLKM_CM, | |
2715 | .flags = CLKF_DSS, | |
2716 | }; | |
2717 | ||
2718 | static struct ti_clk usbhost_48m_fck = { | |
2719 | .name = "usbhost_48m_fck", | |
2720 | .clkdm_name = "usbhost_clkdm", | |
2721 | .type = TI_CLK_GATE, | |
2722 | .data = &usbhost_48m_fck_data, | |
2723 | }; | |
2724 | ||
2725 | static struct ti_clk_gate des1_ick_data = { | |
2726 | .parent = "security_l4_ick2", | |
2727 | .bit_shift = 0, | |
2728 | .reg = 0xa14, | |
2729 | .module = TI_CLKM_CM, | |
2730 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
2731 | }; | |
2732 | ||
2733 | static struct ti_clk des1_ick = { | |
2734 | .name = "des1_ick", | |
2735 | .type = TI_CLK_GATE, | |
2736 | .data = &des1_ick_data, | |
2737 | }; | |
2738 | ||
2739 | static struct ti_clk_gate sgx_gate_fck_data = { | |
2740 | .parent = "core_ck", | |
2741 | .bit_shift = 1, | |
2742 | .reg = 0xb00, | |
2743 | .module = TI_CLKM_CM, | |
2744 | }; | |
2745 | ||
2746 | static struct ti_clk_fixed_factor core_d4_ck_data = { | |
2747 | .parent = "core_ck", | |
2748 | .div = 4, | |
2749 | .mult = 1, | |
2750 | }; | |
2751 | ||
2752 | static struct ti_clk core_d4_ck = { | |
2753 | .name = "core_d4_ck", | |
2754 | .type = TI_CLK_FIXED_FACTOR, | |
2755 | .data = &core_d4_ck_data, | |
2756 | }; | |
2757 | ||
2758 | static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = { | |
2759 | .parent = "dpll4_m2x2_ck", | |
2760 | .div = 1, | |
2761 | .mult = 1, | |
2762 | }; | |
2763 | ||
2764 | static struct ti_clk omap_192m_alwon_fck = { | |
2765 | .name = "omap_192m_alwon_fck", | |
2766 | .type = TI_CLK_FIXED_FACTOR, | |
2767 | .data = &omap_192m_alwon_fck_data, | |
2768 | }; | |
2769 | ||
2770 | static struct ti_clk_fixed_factor core_d2_ck_data = { | |
2771 | .parent = "core_ck", | |
2772 | .div = 2, | |
2773 | .mult = 1, | |
2774 | }; | |
2775 | ||
2776 | static struct ti_clk core_d2_ck = { | |
2777 | .name = "core_d2_ck", | |
2778 | .type = TI_CLK_FIXED_FACTOR, | |
2779 | .data = &core_d2_ck_data, | |
2780 | }; | |
2781 | ||
2782 | static struct ti_clk_fixed_factor corex2_d3_fck_data = { | |
2783 | .parent = "corex2_fck", | |
2784 | .div = 3, | |
2785 | .mult = 1, | |
2786 | }; | |
2787 | ||
2788 | static struct ti_clk corex2_d3_fck = { | |
2789 | .name = "corex2_d3_fck", | |
2790 | .type = TI_CLK_FIXED_FACTOR, | |
2791 | .data = &corex2_d3_fck_data, | |
2792 | }; | |
2793 | ||
2794 | static struct ti_clk_fixed_factor corex2_d5_fck_data = { | |
2795 | .parent = "corex2_fck", | |
2796 | .div = 5, | |
2797 | .mult = 1, | |
2798 | }; | |
2799 | ||
2800 | static struct ti_clk corex2_d5_fck = { | |
2801 | .name = "corex2_d5_fck", | |
2802 | .type = TI_CLK_FIXED_FACTOR, | |
2803 | .data = &corex2_d5_fck_data, | |
2804 | }; | |
2805 | ||
2806 | static const char *sgx_mux_fck_parents[] = { | |
2807 | "core_d3_ck", | |
2808 | "core_d4_ck", | |
2809 | "core_d6_ck", | |
2810 | "cm_96m_fck", | |
2811 | "omap_192m_alwon_fck", | |
2812 | "core_d2_ck", | |
2813 | "corex2_d3_fck", | |
2814 | "corex2_d5_fck", | |
2815 | }; | |
2816 | ||
2817 | static struct ti_clk_mux sgx_mux_fck_data = { | |
2818 | .num_parents = ARRAY_SIZE(sgx_mux_fck_parents), | |
2819 | .reg = 0xb40, | |
2820 | .module = TI_CLKM_CM, | |
2821 | .parents = sgx_mux_fck_parents, | |
2822 | }; | |
2823 | ||
2824 | static struct ti_clk_composite sgx_fck_data = { | |
2825 | .mux = &sgx_mux_fck_data, | |
2826 | .gate = &sgx_gate_fck_data, | |
2827 | }; | |
2828 | ||
2829 | static struct ti_clk sgx_fck = { | |
2830 | .name = "sgx_fck", | |
2831 | .type = TI_CLK_COMPOSITE, | |
2832 | .data = &sgx_fck_data, | |
2833 | }; | |
2834 | ||
2835 | static struct ti_clk_gate mcspi1_fck_data = { | |
2836 | .parent = "core_48m_fck", | |
2837 | .bit_shift = 18, | |
2838 | .reg = 0xa00, | |
2839 | .module = TI_CLKM_CM, | |
2840 | .flags = CLKF_WAIT, | |
2841 | }; | |
2842 | ||
2843 | static struct ti_clk mcspi1_fck = { | |
2844 | .name = "mcspi1_fck", | |
2845 | .clkdm_name = "core_l4_clkdm", | |
2846 | .type = TI_CLK_GATE, | |
2847 | .data = &mcspi1_fck_data, | |
2848 | }; | |
2849 | ||
2850 | static struct ti_clk_gate mmchs2_fck_data = { | |
2851 | .parent = "core_96m_fck", | |
2852 | .bit_shift = 25, | |
2853 | .reg = 0xa00, | |
2854 | .module = TI_CLKM_CM, | |
2855 | .flags = CLKF_WAIT, | |
2856 | }; | |
2857 | ||
2858 | static struct ti_clk mmchs2_fck = { | |
2859 | .name = "mmchs2_fck", | |
2860 | .clkdm_name = "core_l4_clkdm", | |
2861 | .type = TI_CLK_GATE, | |
2862 | .data = &mmchs2_fck_data, | |
2863 | }; | |
2864 | ||
2865 | static struct ti_clk_gate mcspi2_fck_data = { | |
2866 | .parent = "core_48m_fck", | |
2867 | .bit_shift = 19, | |
2868 | .reg = 0xa00, | |
2869 | .module = TI_CLKM_CM, | |
2870 | .flags = CLKF_WAIT, | |
2871 | }; | |
2872 | ||
2873 | static struct ti_clk mcspi2_fck = { | |
2874 | .name = "mcspi2_fck", | |
2875 | .clkdm_name = "core_l4_clkdm", | |
2876 | .type = TI_CLK_GATE, | |
2877 | .data = &mcspi2_fck_data, | |
2878 | }; | |
2879 | ||
2880 | static struct ti_clk_gate vpfe_fck_data = { | |
2881 | .parent = "pclk_ck", | |
2882 | .bit_shift = 10, | |
2883 | .reg = 0x59c, | |
2884 | .module = TI_CLKM_SCRM, | |
2885 | }; | |
2886 | ||
2887 | static struct ti_clk vpfe_fck = { | |
2888 | .name = "vpfe_fck", | |
2889 | .type = TI_CLK_GATE, | |
2890 | .data = &vpfe_fck_data, | |
2891 | }; | |
2892 | ||
2893 | static struct ti_clk_gate gpt4_gate_fck_data = { | |
2894 | .parent = "sys_ck", | |
2895 | .bit_shift = 5, | |
2896 | .reg = 0x1000, | |
2897 | .module = TI_CLKM_CM, | |
2898 | }; | |
2899 | ||
2900 | static struct ti_clk_gate mcbsp1_gate_fck_data = { | |
2901 | .parent = "mcbsp_clks", | |
2902 | .bit_shift = 9, | |
2903 | .reg = 0xa00, | |
2904 | .module = TI_CLKM_CM, | |
2905 | }; | |
2906 | ||
2907 | static struct ti_clk_gate gpt5_gate_fck_data = { | |
2908 | .parent = "sys_ck", | |
2909 | .bit_shift = 6, | |
2910 | .reg = 0x1000, | |
2911 | .module = TI_CLKM_CM, | |
2912 | }; | |
2913 | ||
2914 | static const char *gpt5_mux_fck_parents[] = { | |
2915 | "omap_32k_fck", | |
2916 | "sys_ck", | |
2917 | }; | |
2918 | ||
2919 | static struct ti_clk_mux gpt5_mux_fck_data = { | |
2920 | .bit_shift = 3, | |
2921 | .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents), | |
2922 | .reg = 0x1040, | |
2923 | .module = TI_CLKM_CM, | |
2924 | .parents = gpt5_mux_fck_parents, | |
2925 | }; | |
2926 | ||
2927 | static struct ti_clk_composite gpt5_fck_data = { | |
2928 | .mux = &gpt5_mux_fck_data, | |
2929 | .gate = &gpt5_gate_fck_data, | |
2930 | }; | |
2931 | ||
2932 | static struct ti_clk gpt5_fck = { | |
2933 | .name = "gpt5_fck", | |
2934 | .type = TI_CLK_COMPOSITE, | |
2935 | .data = &gpt5_fck_data, | |
2936 | }; | |
2937 | ||
2938 | static struct ti_clk_gate ts_fck_data = { | |
2939 | .parent = "omap_32k_fck", | |
2940 | .bit_shift = 1, | |
2941 | .reg = 0xa08, | |
2942 | .module = TI_CLKM_CM, | |
2943 | }; | |
2944 | ||
2945 | static struct ti_clk ts_fck = { | |
2946 | .name = "ts_fck", | |
2947 | .clkdm_name = "core_l4_clkdm", | |
2948 | .type = TI_CLK_GATE, | |
2949 | .data = &ts_fck_data, | |
2950 | }; | |
2951 | ||
2952 | static struct ti_clk_fixed_factor wdt1_fck_data = { | |
2953 | .parent = "secure_32k_fck", | |
2954 | .div = 1, | |
2955 | .mult = 1, | |
2956 | }; | |
2957 | ||
2958 | static struct ti_clk wdt1_fck = { | |
2959 | .name = "wdt1_fck", | |
2960 | .type = TI_CLK_FIXED_FACTOR, | |
2961 | .data = &wdt1_fck_data, | |
2962 | }; | |
2963 | ||
2964 | static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = { | |
2965 | .parent = "dpll4_m6x2_mul_ck", | |
2966 | .bit_shift = 0x1f, | |
2967 | .reg = 0xd00, | |
2968 | .module = TI_CLKM_CM, | |
2969 | .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, | |
2970 | }; | |
2971 | ||
2972 | static struct ti_clk dpll4_m6x2_ck_omap36xx = { | |
2973 | .name = "dpll4_m6x2_ck", | |
2974 | .type = TI_CLK_GATE, | |
2975 | .data = &dpll4_m6x2_ck_omap36xx_data, | |
2976 | .patch = &dpll4_m6x2_ck, | |
2977 | }; | |
2978 | ||
2979 | static const char *gpt4_mux_fck_parents[] = { | |
2980 | "omap_32k_fck", | |
2981 | "sys_ck", | |
2982 | }; | |
2983 | ||
2984 | static struct ti_clk_mux gpt4_mux_fck_data = { | |
2985 | .bit_shift = 2, | |
2986 | .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents), | |
2987 | .reg = 0x1040, | |
2988 | .module = TI_CLKM_CM, | |
2989 | .parents = gpt4_mux_fck_parents, | |
2990 | }; | |
2991 | ||
2992 | static struct ti_clk_gate usbhost_ick_data = { | |
2993 | .parent = "l4_ick", | |
2994 | .bit_shift = 0, | |
2995 | .reg = 0x1410, | |
2996 | .module = TI_CLKM_CM, | |
2997 | .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE, | |
2998 | }; | |
2999 | ||
3000 | static struct ti_clk usbhost_ick = { | |
3001 | .name = "usbhost_ick", | |
3002 | .clkdm_name = "usbhost_clkdm", | |
3003 | .type = TI_CLK_GATE, | |
3004 | .data = &usbhost_ick_data, | |
3005 | }; | |
3006 | ||
3007 | static struct ti_clk_gate mcbsp2_ick_data = { | |
3008 | .parent = "per_l4_ick", | |
3009 | .bit_shift = 0, | |
3010 | .reg = 0x1010, | |
3011 | .module = TI_CLKM_CM, | |
3012 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3013 | }; | |
3014 | ||
3015 | static struct ti_clk mcbsp2_ick = { | |
3016 | .name = "mcbsp2_ick", | |
3017 | .clkdm_name = "per_clkdm", | |
3018 | .type = TI_CLK_GATE, | |
3019 | .data = &mcbsp2_ick_data, | |
3020 | }; | |
3021 | ||
3022 | static struct ti_clk_gate omapctrl_ick_data = { | |
3023 | .parent = "core_l4_ick", | |
3024 | .bit_shift = 6, | |
3025 | .reg = 0xa10, | |
3026 | .module = TI_CLKM_CM, | |
3027 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3028 | }; | |
3029 | ||
3030 | static struct ti_clk omapctrl_ick = { | |
3031 | .name = "omapctrl_ick", | |
3032 | .clkdm_name = "core_l4_clkdm", | |
3033 | .type = TI_CLK_GATE, | |
3034 | .data = &omapctrl_ick_data, | |
3035 | }; | |
3036 | ||
3037 | static struct ti_clk_fixed_factor omap_96m_d4_fck_data = { | |
3038 | .parent = "omap_96m_fck", | |
3039 | .div = 4, | |
3040 | .mult = 1, | |
3041 | }; | |
3042 | ||
3043 | static struct ti_clk omap_96m_d4_fck = { | |
3044 | .name = "omap_96m_d4_fck", | |
3045 | .type = TI_CLK_FIXED_FACTOR, | |
3046 | .data = &omap_96m_d4_fck_data, | |
3047 | }; | |
3048 | ||
3049 | static struct ti_clk_gate gpt6_ick_data = { | |
3050 | .parent = "per_l4_ick", | |
3051 | .bit_shift = 7, | |
3052 | .reg = 0x1010, | |
3053 | .module = TI_CLKM_CM, | |
3054 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3055 | }; | |
3056 | ||
3057 | static struct ti_clk gpt6_ick = { | |
3058 | .name = "gpt6_ick", | |
3059 | .clkdm_name = "per_clkdm", | |
3060 | .type = TI_CLK_GATE, | |
3061 | .data = &gpt6_ick_data, | |
3062 | }; | |
3063 | ||
3064 | static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = { | |
3065 | .parent = "dpll3_m3x2_mul_ck", | |
3066 | .bit_shift = 0xc, | |
3067 | .reg = 0xd00, | |
3068 | .module = TI_CLKM_CM, | |
3069 | .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, | |
3070 | }; | |
3071 | ||
3072 | static struct ti_clk dpll3_m3x2_ck_omap36xx = { | |
3073 | .name = "dpll3_m3x2_ck", | |
3074 | .type = TI_CLK_GATE, | |
3075 | .data = &dpll3_m3x2_ck_omap36xx_data, | |
3076 | .patch = &dpll3_m3x2_ck, | |
3077 | }; | |
3078 | ||
3079 | static struct ti_clk_gate i2c3_ick_data = { | |
3080 | .parent = "core_l4_ick", | |
3081 | .bit_shift = 17, | |
3082 | .reg = 0xa10, | |
3083 | .module = TI_CLKM_CM, | |
3084 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3085 | }; | |
3086 | ||
3087 | static struct ti_clk i2c3_ick = { | |
3088 | .name = "i2c3_ick", | |
3089 | .clkdm_name = "core_l4_clkdm", | |
3090 | .type = TI_CLK_GATE, | |
3091 | .data = &i2c3_ick_data, | |
3092 | }; | |
3093 | ||
3094 | static struct ti_clk_gate gpio6_ick_data = { | |
3095 | .parent = "per_l4_ick", | |
3096 | .bit_shift = 17, | |
3097 | .reg = 0x1010, | |
3098 | .module = TI_CLKM_CM, | |
3099 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3100 | }; | |
3101 | ||
3102 | static struct ti_clk gpio6_ick = { | |
3103 | .name = "gpio6_ick", | |
3104 | .clkdm_name = "per_clkdm", | |
3105 | .type = TI_CLK_GATE, | |
3106 | .data = &gpio6_ick_data, | |
3107 | }; | |
3108 | ||
3109 | static struct ti_clk_gate mspro_ick_data = { | |
3110 | .parent = "core_l4_ick", | |
3111 | .bit_shift = 23, | |
3112 | .reg = 0xa10, | |
3113 | .module = TI_CLKM_CM, | |
3114 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3115 | }; | |
3116 | ||
3117 | static struct ti_clk mspro_ick = { | |
3118 | .name = "mspro_ick", | |
3119 | .clkdm_name = "core_l4_clkdm", | |
3120 | .type = TI_CLK_GATE, | |
3121 | .data = &mspro_ick_data, | |
3122 | }; | |
3123 | ||
3124 | static struct ti_clk_composite mcbsp1_fck_data = { | |
3125 | .mux = &mcbsp1_mux_fck_data, | |
3126 | .gate = &mcbsp1_gate_fck_data, | |
3127 | }; | |
3128 | ||
3129 | static struct ti_clk mcbsp1_fck = { | |
3130 | .name = "mcbsp1_fck", | |
3131 | .type = TI_CLK_COMPOSITE, | |
3132 | .data = &mcbsp1_fck_data, | |
3133 | }; | |
3134 | ||
3135 | static struct ti_clk_gate gpt3_gate_fck_data = { | |
3136 | .parent = "sys_ck", | |
3137 | .bit_shift = 4, | |
3138 | .reg = 0x1000, | |
3139 | .module = TI_CLKM_CM, | |
3140 | }; | |
3141 | ||
3142 | static struct ti_clk_fixed rmii_ck_data = { | |
3143 | .frequency = 50000000, | |
3144 | }; | |
3145 | ||
3146 | static struct ti_clk rmii_ck = { | |
3147 | .name = "rmii_ck", | |
3148 | .type = TI_CLK_FIXED, | |
3149 | .data = &rmii_ck_data, | |
3150 | }; | |
3151 | ||
3152 | static struct ti_clk_gate gpt6_gate_fck_data = { | |
3153 | .parent = "sys_ck", | |
3154 | .bit_shift = 7, | |
3155 | .reg = 0x1000, | |
3156 | .module = TI_CLKM_CM, | |
3157 | }; | |
3158 | ||
3159 | static struct ti_clk_composite gpt6_fck_data = { | |
3160 | .mux = &gpt6_mux_fck_data, | |
3161 | .gate = &gpt6_gate_fck_data, | |
3162 | }; | |
3163 | ||
3164 | static struct ti_clk gpt6_fck = { | |
3165 | .name = "gpt6_fck", | |
3166 | .type = TI_CLK_COMPOSITE, | |
3167 | .data = &gpt6_fck_data, | |
3168 | }; | |
3169 | ||
3170 | static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = { | |
3171 | .parent = "dpll5_m2_ck", | |
3172 | .div = 4, | |
3173 | .mult = 1, | |
3174 | }; | |
3175 | ||
3176 | static struct ti_clk dpll5_m2_d4_ck = { | |
3177 | .name = "dpll5_m2_d4_ck", | |
3178 | .type = TI_CLK_FIXED_FACTOR, | |
3179 | .data = &dpll5_m2_d4_ck_data, | |
3180 | }; | |
3181 | ||
3182 | static struct ti_clk_fixed_factor sys_d2_ck_data = { | |
3183 | .parent = "sys_ck", | |
3184 | .div = 2, | |
3185 | .mult = 1, | |
3186 | }; | |
3187 | ||
3188 | static struct ti_clk sys_d2_ck = { | |
3189 | .name = "sys_d2_ck", | |
3190 | .type = TI_CLK_FIXED_FACTOR, | |
3191 | .data = &sys_d2_ck_data, | |
3192 | }; | |
3193 | ||
3194 | static struct ti_clk_fixed_factor omap_96m_d2_fck_data = { | |
3195 | .parent = "omap_96m_fck", | |
3196 | .div = 2, | |
3197 | .mult = 1, | |
3198 | }; | |
3199 | ||
3200 | static struct ti_clk omap_96m_d2_fck = { | |
3201 | .name = "omap_96m_d2_fck", | |
3202 | .type = TI_CLK_FIXED_FACTOR, | |
3203 | .data = &omap_96m_d2_fck_data, | |
3204 | }; | |
3205 | ||
3206 | static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = { | |
3207 | .parent = "dpll5_m2_ck", | |
3208 | .div = 8, | |
3209 | .mult = 1, | |
3210 | }; | |
3211 | ||
3212 | static struct ti_clk dpll5_m2_d8_ck = { | |
3213 | .name = "dpll5_m2_d8_ck", | |
3214 | .type = TI_CLK_FIXED_FACTOR, | |
3215 | .data = &dpll5_m2_d8_ck_data, | |
3216 | }; | |
3217 | ||
3218 | static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = { | |
3219 | .parent = "dpll5_m2_ck", | |
3220 | .div = 16, | |
3221 | .mult = 1, | |
3222 | }; | |
3223 | ||
3224 | static struct ti_clk dpll5_m2_d16_ck = { | |
3225 | .name = "dpll5_m2_d16_ck", | |
3226 | .type = TI_CLK_FIXED_FACTOR, | |
3227 | .data = &dpll5_m2_d16_ck_data, | |
3228 | }; | |
3229 | ||
3230 | static const char *usim_mux_fck_parents[] = { | |
3231 | "sys_ck", | |
3232 | "sys_d2_ck", | |
3233 | "omap_96m_d2_fck", | |
3234 | "omap_96m_d4_fck", | |
3235 | "omap_96m_d8_fck", | |
3236 | "omap_96m_d10_fck", | |
3237 | "dpll5_m2_d4_ck", | |
3238 | "dpll5_m2_d8_ck", | |
3239 | "dpll5_m2_d16_ck", | |
3240 | "dpll5_m2_d20_ck", | |
3241 | }; | |
3242 | ||
3243 | static struct ti_clk_mux usim_mux_fck_data = { | |
3244 | .bit_shift = 3, | |
3245 | .num_parents = ARRAY_SIZE(usim_mux_fck_parents), | |
3246 | .reg = 0xc40, | |
3247 | .module = TI_CLKM_CM, | |
3248 | .parents = usim_mux_fck_parents, | |
3249 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
3250 | }; | |
3251 | ||
3252 | static struct ti_clk_composite usim_fck_data = { | |
3253 | .mux = &usim_mux_fck_data, | |
3254 | .gate = &usim_gate_fck_data, | |
3255 | }; | |
3256 | ||
3257 | static struct ti_clk usim_fck = { | |
3258 | .name = "usim_fck", | |
3259 | .type = TI_CLK_COMPOSITE, | |
3260 | .data = &usim_fck_data, | |
3261 | }; | |
3262 | ||
3263 | static int ssi_ssr_div_fck_3430es2_divs[] = { | |
3264 | 0, | |
3265 | 1, | |
3266 | 2, | |
3267 | 3, | |
3268 | 4, | |
3269 | 0, | |
3270 | 6, | |
3271 | 0, | |
3272 | 8, | |
3273 | }; | |
3274 | ||
3275 | static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = { | |
3276 | .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs), | |
3277 | .parent = "corex2_fck", | |
3278 | .bit_shift = 8, | |
3279 | .dividers = ssi_ssr_div_fck_3430es2_divs, | |
3280 | .reg = 0xa40, | |
3281 | .module = TI_CLKM_CM, | |
3282 | }; | |
3283 | ||
3284 | static struct ti_clk_composite ssi_ssr_fck_3430es2_data = { | |
3285 | .gate = &ssi_ssr_gate_fck_3430es2_data, | |
3286 | .divider = &ssi_ssr_div_fck_3430es2_data, | |
3287 | }; | |
3288 | ||
3289 | static struct ti_clk ssi_ssr_fck_3430es2 = { | |
3290 | .name = "ssi_ssr_fck", | |
3291 | .type = TI_CLK_COMPOSITE, | |
3292 | .data = &ssi_ssr_fck_3430es2_data, | |
3293 | }; | |
3294 | ||
3295 | static struct ti_clk_gate dss1_alwon_fck_3430es1_data = { | |
3296 | .parent = "dpll4_m4x2_ck", | |
3297 | .bit_shift = 0, | |
3298 | .reg = 0xe00, | |
3299 | .module = TI_CLKM_CM, | |
3300 | .flags = CLKF_SET_RATE_PARENT, | |
3301 | }; | |
3302 | ||
3303 | static struct ti_clk dss1_alwon_fck_3430es1 = { | |
3304 | .name = "dss1_alwon_fck", | |
3305 | .clkdm_name = "dss_clkdm", | |
3306 | .type = TI_CLK_GATE, | |
3307 | .data = &dss1_alwon_fck_3430es1_data, | |
3308 | }; | |
3309 | ||
3310 | static struct ti_clk_gate gpt3_ick_data = { | |
3311 | .parent = "per_l4_ick", | |
3312 | .bit_shift = 4, | |
3313 | .reg = 0x1010, | |
3314 | .module = TI_CLKM_CM, | |
3315 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3316 | }; | |
3317 | ||
3318 | static struct ti_clk gpt3_ick = { | |
3319 | .name = "gpt3_ick", | |
3320 | .clkdm_name = "per_clkdm", | |
3321 | .type = TI_CLK_GATE, | |
3322 | .data = &gpt3_ick_data, | |
3323 | }; | |
3324 | ||
3325 | static struct ti_clk_fixed_factor omap_12m_fck_data = { | |
3326 | .parent = "omap_48m_fck", | |
3327 | .div = 4, | |
3328 | .mult = 1, | |
3329 | }; | |
3330 | ||
3331 | static struct ti_clk omap_12m_fck = { | |
3332 | .name = "omap_12m_fck", | |
3333 | .type = TI_CLK_FIXED_FACTOR, | |
3334 | .data = &omap_12m_fck_data, | |
3335 | }; | |
3336 | ||
3337 | static struct ti_clk_fixed_factor core_12m_fck_data = { | |
3338 | .parent = "omap_12m_fck", | |
3339 | .div = 1, | |
3340 | .mult = 1, | |
3341 | }; | |
3342 | ||
3343 | static struct ti_clk core_12m_fck = { | |
3344 | .name = "core_12m_fck", | |
3345 | .type = TI_CLK_FIXED_FACTOR, | |
3346 | .data = &core_12m_fck_data, | |
3347 | }; | |
3348 | ||
3349 | static struct ti_clk_gate hdq_fck_data = { | |
3350 | .parent = "core_12m_fck", | |
3351 | .bit_shift = 22, | |
3352 | .reg = 0xa00, | |
3353 | .module = TI_CLKM_CM, | |
3354 | .flags = CLKF_WAIT, | |
3355 | }; | |
3356 | ||
3357 | static struct ti_clk hdq_fck = { | |
3358 | .name = "hdq_fck", | |
3359 | .clkdm_name = "core_l4_clkdm", | |
3360 | .type = TI_CLK_GATE, | |
3361 | .data = &hdq_fck_data, | |
3362 | }; | |
3363 | ||
3364 | static struct ti_clk_gate usbtll_fck_data = { | |
3365 | .parent = "dpll5_m2_ck", | |
3366 | .bit_shift = 2, | |
3367 | .reg = 0xa08, | |
3368 | .module = TI_CLKM_CM, | |
3369 | .flags = CLKF_WAIT, | |
3370 | }; | |
3371 | ||
3372 | static struct ti_clk usbtll_fck = { | |
3373 | .name = "usbtll_fck", | |
3374 | .clkdm_name = "core_l4_clkdm", | |
3375 | .type = TI_CLK_GATE, | |
3376 | .data = &usbtll_fck_data, | |
3377 | }; | |
3378 | ||
3379 | static struct ti_clk_gate hsotgusb_fck_am35xx_data = { | |
3380 | .parent = "sys_ck", | |
3381 | .bit_shift = 8, | |
3382 | .reg = 0x59c, | |
3383 | .module = TI_CLKM_SCRM, | |
3384 | }; | |
3385 | ||
3386 | static struct ti_clk hsotgusb_fck_am35xx = { | |
3387 | .name = "hsotgusb_fck_am35xx", | |
3388 | .clkdm_name = "core_l3_clkdm", | |
3389 | .type = TI_CLK_GATE, | |
3390 | .data = &hsotgusb_fck_am35xx_data, | |
3391 | }; | |
3392 | ||
3393 | static struct ti_clk_gate hsotgusb_ick_3430es2_data = { | |
3394 | .parent = "core_l3_ick", | |
3395 | .bit_shift = 4, | |
3396 | .reg = 0xa10, | |
3397 | .module = TI_CLKM_CM, | |
3398 | .flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE, | |
3399 | }; | |
3400 | ||
3401 | static struct ti_clk hsotgusb_ick_3430es2 = { | |
3402 | .name = "hsotgusb_ick_3430es2", | |
3403 | .clkdm_name = "core_l3_clkdm", | |
3404 | .type = TI_CLK_GATE, | |
3405 | .data = &hsotgusb_ick_3430es2_data, | |
3406 | }; | |
3407 | ||
3408 | static struct ti_clk_gate gfx_l3_ck_data = { | |
3409 | .parent = "l3_ick", | |
3410 | .bit_shift = 0, | |
3411 | .reg = 0xb10, | |
3412 | .module = TI_CLKM_CM, | |
3413 | .flags = CLKF_WAIT, | |
3414 | }; | |
3415 | ||
3416 | static struct ti_clk gfx_l3_ck = { | |
3417 | .name = "gfx_l3_ck", | |
3418 | .clkdm_name = "gfx_3430es1_clkdm", | |
3419 | .type = TI_CLK_GATE, | |
3420 | .data = &gfx_l3_ck_data, | |
3421 | }; | |
3422 | ||
3423 | static struct ti_clk_fixed_factor gfx_l3_ick_data = { | |
3424 | .parent = "gfx_l3_ck", | |
3425 | .div = 1, | |
3426 | .mult = 1, | |
3427 | }; | |
3428 | ||
3429 | static struct ti_clk gfx_l3_ick = { | |
3430 | .name = "gfx_l3_ick", | |
3431 | .type = TI_CLK_FIXED_FACTOR, | |
3432 | .data = &gfx_l3_ick_data, | |
3433 | }; | |
3434 | ||
3435 | static struct ti_clk_gate mcbsp1_ick_data = { | |
3436 | .parent = "core_l4_ick", | |
3437 | .bit_shift = 9, | |
3438 | .reg = 0xa10, | |
3439 | .module = TI_CLKM_CM, | |
3440 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3441 | }; | |
3442 | ||
3443 | static struct ti_clk mcbsp1_ick = { | |
3444 | .name = "mcbsp1_ick", | |
3445 | .clkdm_name = "core_l4_clkdm", | |
3446 | .type = TI_CLK_GATE, | |
3447 | .data = &mcbsp1_ick_data, | |
3448 | }; | |
3449 | ||
3450 | static struct ti_clk_fixed_factor gpt12_fck_data = { | |
3451 | .parent = "secure_32k_fck", | |
3452 | .div = 1, | |
3453 | .mult = 1, | |
3454 | }; | |
3455 | ||
3456 | static struct ti_clk gpt12_fck = { | |
3457 | .name = "gpt12_fck", | |
3458 | .type = TI_CLK_FIXED_FACTOR, | |
3459 | .data = &gpt12_fck_data, | |
3460 | }; | |
3461 | ||
3462 | static struct ti_clk_gate gfx_cg2_ck_data = { | |
3463 | .parent = "gfx_l3_fck", | |
3464 | .bit_shift = 2, | |
3465 | .reg = 0xb00, | |
3466 | .module = TI_CLKM_CM, | |
3467 | .flags = CLKF_WAIT, | |
3468 | }; | |
3469 | ||
3470 | static struct ti_clk gfx_cg2_ck = { | |
3471 | .name = "gfx_cg2_ck", | |
3472 | .clkdm_name = "gfx_3430es1_clkdm", | |
3473 | .type = TI_CLK_GATE, | |
3474 | .data = &gfx_cg2_ck_data, | |
3475 | }; | |
3476 | ||
3477 | static struct ti_clk_gate i2c2_ick_data = { | |
3478 | .parent = "core_l4_ick", | |
3479 | .bit_shift = 16, | |
3480 | .reg = 0xa10, | |
3481 | .module = TI_CLKM_CM, | |
3482 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3483 | }; | |
3484 | ||
3485 | static struct ti_clk i2c2_ick = { | |
3486 | .name = "i2c2_ick", | |
3487 | .clkdm_name = "core_l4_clkdm", | |
3488 | .type = TI_CLK_GATE, | |
3489 | .data = &i2c2_ick_data, | |
3490 | }; | |
3491 | ||
3492 | static struct ti_clk_gate gpio4_dbck_data = { | |
3493 | .parent = "per_32k_alwon_fck", | |
3494 | .bit_shift = 15, | |
3495 | .reg = 0x1000, | |
3496 | .module = TI_CLKM_CM, | |
3497 | }; | |
3498 | ||
3499 | static struct ti_clk gpio4_dbck = { | |
3500 | .name = "gpio4_dbck", | |
3501 | .clkdm_name = "per_clkdm", | |
3502 | .type = TI_CLK_GATE, | |
3503 | .data = &gpio4_dbck_data, | |
3504 | }; | |
3505 | ||
3506 | static struct ti_clk_gate i2c3_fck_data = { | |
3507 | .parent = "core_96m_fck", | |
3508 | .bit_shift = 17, | |
3509 | .reg = 0xa00, | |
3510 | .module = TI_CLKM_CM, | |
3511 | .flags = CLKF_WAIT, | |
3512 | }; | |
3513 | ||
3514 | static struct ti_clk i2c3_fck = { | |
3515 | .name = "i2c3_fck", | |
3516 | .clkdm_name = "core_l4_clkdm", | |
3517 | .type = TI_CLK_GATE, | |
3518 | .data = &i2c3_fck_data, | |
3519 | }; | |
3520 | ||
3521 | static struct ti_clk_composite gpt3_fck_data = { | |
3522 | .mux = &gpt3_mux_fck_data, | |
3523 | .gate = &gpt3_gate_fck_data, | |
3524 | }; | |
3525 | ||
3526 | static struct ti_clk gpt3_fck = { | |
3527 | .name = "gpt3_fck", | |
3528 | .type = TI_CLK_COMPOSITE, | |
3529 | .data = &gpt3_fck_data, | |
3530 | }; | |
3531 | ||
3532 | static struct ti_clk_gate i2c1_ick_data = { | |
3533 | .parent = "core_l4_ick", | |
3534 | .bit_shift = 15, | |
3535 | .reg = 0xa10, | |
3536 | .module = TI_CLKM_CM, | |
3537 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3538 | }; | |
3539 | ||
3540 | static struct ti_clk i2c1_ick = { | |
3541 | .name = "i2c1_ick", | |
3542 | .clkdm_name = "core_l4_clkdm", | |
3543 | .type = TI_CLK_GATE, | |
3544 | .data = &i2c1_ick_data, | |
3545 | }; | |
3546 | ||
3547 | static struct ti_clk_gate omap_32ksync_ick_data = { | |
3548 | .parent = "wkup_l4_ick", | |
3549 | .bit_shift = 2, | |
3550 | .reg = 0xc10, | |
3551 | .module = TI_CLKM_CM, | |
3552 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3553 | }; | |
3554 | ||
3555 | static struct ti_clk omap_32ksync_ick = { | |
3556 | .name = "omap_32ksync_ick", | |
3557 | .clkdm_name = "wkup_clkdm", | |
3558 | .type = TI_CLK_GATE, | |
3559 | .data = &omap_32ksync_ick_data, | |
3560 | }; | |
3561 | ||
3562 | static struct ti_clk_gate aes2_ick_data = { | |
3563 | .parent = "core_l4_ick", | |
3564 | .bit_shift = 28, | |
3565 | .reg = 0xa10, | |
3566 | .module = TI_CLKM_CM, | |
3567 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3568 | }; | |
3569 | ||
3570 | static struct ti_clk aes2_ick = { | |
3571 | .name = "aes2_ick", | |
3572 | .clkdm_name = "core_l4_clkdm", | |
3573 | .type = TI_CLK_GATE, | |
3574 | .data = &aes2_ick_data, | |
3575 | }; | |
3576 | ||
3577 | static const char *gpt8_mux_fck_parents[] = { | |
3578 | "omap_32k_fck", | |
3579 | "sys_ck", | |
3580 | }; | |
3581 | ||
3582 | static struct ti_clk_mux gpt8_mux_fck_data = { | |
3583 | .bit_shift = 6, | |
3584 | .num_parents = ARRAY_SIZE(gpt8_mux_fck_parents), | |
3585 | .reg = 0x1040, | |
3586 | .module = TI_CLKM_CM, | |
3587 | .parents = gpt8_mux_fck_parents, | |
3588 | }; | |
3589 | ||
3590 | static struct ti_clk_composite gpt8_fck_data = { | |
3591 | .mux = &gpt8_mux_fck_data, | |
3592 | .gate = &gpt8_gate_fck_data, | |
3593 | }; | |
3594 | ||
3595 | static struct ti_clk gpt8_fck = { | |
3596 | .name = "gpt8_fck", | |
3597 | .type = TI_CLK_COMPOSITE, | |
3598 | .data = &gpt8_fck_data, | |
3599 | }; | |
3600 | ||
3601 | static struct ti_clk_gate mcbsp4_gate_fck_data = { | |
3602 | .parent = "mcbsp_clks", | |
3603 | .bit_shift = 2, | |
3604 | .reg = 0x1000, | |
3605 | .module = TI_CLKM_CM, | |
3606 | }; | |
3607 | ||
3608 | static struct ti_clk_composite mcbsp4_fck_data = { | |
3609 | .mux = &mcbsp4_mux_fck_data, | |
3610 | .gate = &mcbsp4_gate_fck_data, | |
3611 | }; | |
3612 | ||
3613 | static struct ti_clk mcbsp4_fck = { | |
3614 | .name = "mcbsp4_fck", | |
3615 | .type = TI_CLK_COMPOSITE, | |
3616 | .data = &mcbsp4_fck_data, | |
3617 | }; | |
3618 | ||
3619 | static struct ti_clk_gate gpio2_dbck_data = { | |
3620 | .parent = "per_32k_alwon_fck", | |
3621 | .bit_shift = 13, | |
3622 | .reg = 0x1000, | |
3623 | .module = TI_CLKM_CM, | |
3624 | }; | |
3625 | ||
3626 | static struct ti_clk gpio2_dbck = { | |
3627 | .name = "gpio2_dbck", | |
3628 | .clkdm_name = "per_clkdm", | |
3629 | .type = TI_CLK_GATE, | |
3630 | .data = &gpio2_dbck_data, | |
3631 | }; | |
3632 | ||
3633 | static struct ti_clk_gate usbtll_ick_data = { | |
3634 | .parent = "core_l4_ick", | |
3635 | .bit_shift = 2, | |
3636 | .reg = 0xa18, | |
3637 | .module = TI_CLKM_CM, | |
3638 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3639 | }; | |
3640 | ||
3641 | static struct ti_clk usbtll_ick = { | |
3642 | .name = "usbtll_ick", | |
3643 | .clkdm_name = "core_l4_clkdm", | |
3644 | .type = TI_CLK_GATE, | |
3645 | .data = &usbtll_ick_data, | |
3646 | }; | |
3647 | ||
3648 | static struct ti_clk_gate mcspi4_ick_data = { | |
3649 | .parent = "core_l4_ick", | |
3650 | .bit_shift = 21, | |
3651 | .reg = 0xa10, | |
3652 | .module = TI_CLKM_CM, | |
3653 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3654 | }; | |
3655 | ||
3656 | static struct ti_clk mcspi4_ick = { | |
3657 | .name = "mcspi4_ick", | |
3658 | .clkdm_name = "core_l4_clkdm", | |
3659 | .type = TI_CLK_GATE, | |
3660 | .data = &mcspi4_ick_data, | |
3661 | }; | |
3662 | ||
3663 | static struct ti_clk_gate dss_96m_fck_data = { | |
3664 | .parent = "omap_96m_fck", | |
3665 | .bit_shift = 2, | |
3666 | .reg = 0xe00, | |
3667 | .module = TI_CLKM_CM, | |
3668 | }; | |
3669 | ||
3670 | static struct ti_clk dss_96m_fck = { | |
3671 | .name = "dss_96m_fck", | |
3672 | .clkdm_name = "dss_clkdm", | |
3673 | .type = TI_CLK_GATE, | |
3674 | .data = &dss_96m_fck_data, | |
3675 | }; | |
3676 | ||
3677 | static struct ti_clk_divider rm_ick_data = { | |
3678 | .parent = "l4_ick", | |
3679 | .bit_shift = 1, | |
3680 | .max_div = 3, | |
3681 | .reg = 0xc40, | |
3682 | .module = TI_CLKM_CM, | |
3683 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
3684 | }; | |
3685 | ||
3686 | static struct ti_clk rm_ick = { | |
3687 | .name = "rm_ick", | |
3688 | .type = TI_CLK_DIVIDER, | |
3689 | .data = &rm_ick_data, | |
3690 | }; | |
3691 | ||
3692 | static struct ti_clk_gate hdq_ick_data = { | |
3693 | .parent = "core_l4_ick", | |
3694 | .bit_shift = 22, | |
3695 | .reg = 0xa10, | |
3696 | .module = TI_CLKM_CM, | |
3697 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3698 | }; | |
3699 | ||
3700 | static struct ti_clk hdq_ick = { | |
3701 | .name = "hdq_ick", | |
3702 | .clkdm_name = "core_l4_clkdm", | |
3703 | .type = TI_CLK_GATE, | |
3704 | .data = &hdq_ick_data, | |
3705 | }; | |
3706 | ||
3707 | static struct ti_clk_fixed_factor dpll3_x2_ck_data = { | |
3708 | .parent = "dpll3_ck", | |
3709 | .div = 1, | |
3710 | .mult = 2, | |
3711 | }; | |
3712 | ||
3713 | static struct ti_clk dpll3_x2_ck = { | |
3714 | .name = "dpll3_x2_ck", | |
3715 | .type = TI_CLK_FIXED_FACTOR, | |
3716 | .data = &dpll3_x2_ck_data, | |
3717 | }; | |
3718 | ||
3719 | static struct ti_clk_gate mad2d_ick_data = { | |
3720 | .parent = "l3_ick", | |
3721 | .bit_shift = 3, | |
3722 | .reg = 0xa18, | |
3723 | .module = TI_CLKM_CM, | |
3724 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3725 | }; | |
3726 | ||
3727 | static struct ti_clk mad2d_ick = { | |
3728 | .name = "mad2d_ick", | |
3729 | .clkdm_name = "d2d_clkdm", | |
3730 | .type = TI_CLK_GATE, | |
3731 | .data = &mad2d_ick_data, | |
3732 | }; | |
3733 | ||
3734 | static struct ti_clk_gate fshostusb_fck_data = { | |
3735 | .parent = "core_48m_fck", | |
3736 | .bit_shift = 5, | |
3737 | .reg = 0xa00, | |
3738 | .module = TI_CLKM_CM, | |
3739 | .flags = CLKF_WAIT, | |
3740 | }; | |
3741 | ||
3742 | static struct ti_clk fshostusb_fck = { | |
3743 | .name = "fshostusb_fck", | |
3744 | .clkdm_name = "core_l4_clkdm", | |
3745 | .type = TI_CLK_GATE, | |
3746 | .data = &fshostusb_fck_data, | |
3747 | }; | |
3748 | ||
3749 | static struct ti_clk_gate sr1_fck_data = { | |
3750 | .parent = "sys_ck", | |
3751 | .bit_shift = 6, | |
3752 | .reg = 0xc00, | |
3753 | .module = TI_CLKM_CM, | |
3754 | .flags = CLKF_WAIT, | |
3755 | }; | |
3756 | ||
3757 | static struct ti_clk sr1_fck = { | |
3758 | .name = "sr1_fck", | |
3759 | .clkdm_name = "wkup_clkdm", | |
3760 | .type = TI_CLK_GATE, | |
3761 | .data = &sr1_fck_data, | |
3762 | }; | |
3763 | ||
3764 | static struct ti_clk_gate des2_ick_data = { | |
3765 | .parent = "core_l4_ick", | |
3766 | .bit_shift = 26, | |
3767 | .reg = 0xa10, | |
3768 | .module = TI_CLKM_CM, | |
3769 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3770 | }; | |
3771 | ||
3772 | static struct ti_clk des2_ick = { | |
3773 | .name = "des2_ick", | |
3774 | .clkdm_name = "core_l4_clkdm", | |
3775 | .type = TI_CLK_GATE, | |
3776 | .data = &des2_ick_data, | |
3777 | }; | |
3778 | ||
3779 | static struct ti_clk_gate sdrc_ick_data = { | |
3780 | .parent = "core_l3_ick", | |
3781 | .bit_shift = 1, | |
3782 | .reg = 0xa10, | |
3783 | .module = TI_CLKM_CM, | |
3784 | .flags = CLKF_WAIT, | |
3785 | }; | |
3786 | ||
3787 | static struct ti_clk sdrc_ick = { | |
3788 | .name = "sdrc_ick", | |
3789 | .clkdm_name = "core_l3_clkdm", | |
3790 | .type = TI_CLK_GATE, | |
3791 | .data = &sdrc_ick_data, | |
3792 | }; | |
3793 | ||
3794 | static struct ti_clk_composite gpt4_fck_data = { | |
3795 | .mux = &gpt4_mux_fck_data, | |
3796 | .gate = &gpt4_gate_fck_data, | |
3797 | }; | |
3798 | ||
3799 | static struct ti_clk gpt4_fck = { | |
3800 | .name = "gpt4_fck", | |
3801 | .type = TI_CLK_COMPOSITE, | |
3802 | .data = &gpt4_fck_data, | |
3803 | }; | |
3804 | ||
3805 | static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = { | |
3806 | .parent = "dpll4_m3x2_mul_ck", | |
3807 | .bit_shift = 0x1c, | |
3808 | .reg = 0xd00, | |
3809 | .module = TI_CLKM_CM, | |
3810 | .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE, | |
3811 | }; | |
3812 | ||
3813 | static struct ti_clk dpll4_m3x2_ck_omap36xx = { | |
3814 | .name = "dpll4_m3x2_ck", | |
3815 | .type = TI_CLK_GATE, | |
3816 | .data = &dpll4_m3x2_ck_omap36xx_data, | |
3817 | .patch = &dpll4_m3x2_ck, | |
3818 | }; | |
3819 | ||
3820 | static struct ti_clk_gate cpefuse_fck_data = { | |
3821 | .parent = "sys_ck", | |
3822 | .bit_shift = 0, | |
3823 | .reg = 0xa08, | |
3824 | .module = TI_CLKM_CM, | |
3825 | }; | |
3826 | ||
3827 | static struct ti_clk cpefuse_fck = { | |
3828 | .name = "cpefuse_fck", | |
3829 | .clkdm_name = "core_l4_clkdm", | |
3830 | .type = TI_CLK_GATE, | |
3831 | .data = &cpefuse_fck_data, | |
3832 | }; | |
3833 | ||
3834 | static struct ti_clk_gate mcspi3_ick_data = { | |
3835 | .parent = "core_l4_ick", | |
3836 | .bit_shift = 20, | |
3837 | .reg = 0xa10, | |
3838 | .module = TI_CLKM_CM, | |
3839 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3840 | }; | |
3841 | ||
3842 | static struct ti_clk mcspi3_ick = { | |
3843 | .name = "mcspi3_ick", | |
3844 | .clkdm_name = "core_l4_clkdm", | |
3845 | .type = TI_CLK_GATE, | |
3846 | .data = &mcspi3_ick_data, | |
3847 | }; | |
3848 | ||
3849 | static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = { | |
3850 | .parent = "ssi_ssr_fck", | |
3851 | .div = 2, | |
3852 | .mult = 1, | |
3853 | }; | |
3854 | ||
3855 | static struct ti_clk ssi_sst_fck_3430es2 = { | |
3856 | .name = "ssi_sst_fck", | |
3857 | .type = TI_CLK_FIXED_FACTOR, | |
3858 | .data = &ssi_sst_fck_3430es2_data, | |
3859 | }; | |
3860 | ||
3861 | static struct ti_clk_gate gpio1_dbck_data = { | |
3862 | .parent = "wkup_32k_fck", | |
3863 | .bit_shift = 3, | |
3864 | .reg = 0xc00, | |
3865 | .module = TI_CLKM_CM, | |
3866 | }; | |
3867 | ||
3868 | static struct ti_clk gpio1_dbck = { | |
3869 | .name = "gpio1_dbck", | |
3870 | .clkdm_name = "wkup_clkdm", | |
3871 | .type = TI_CLK_GATE, | |
3872 | .data = &gpio1_dbck_data, | |
3873 | }; | |
3874 | ||
3875 | static struct ti_clk_gate gpt4_ick_data = { | |
3876 | .parent = "per_l4_ick", | |
3877 | .bit_shift = 5, | |
3878 | .reg = 0x1010, | |
3879 | .module = TI_CLKM_CM, | |
3880 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3881 | }; | |
3882 | ||
3883 | static struct ti_clk gpt4_ick = { | |
3884 | .name = "gpt4_ick", | |
3885 | .clkdm_name = "per_clkdm", | |
3886 | .type = TI_CLK_GATE, | |
3887 | .data = &gpt4_ick_data, | |
3888 | }; | |
3889 | ||
3890 | static struct ti_clk_gate gpt2_ick_data = { | |
3891 | .parent = "per_l4_ick", | |
3892 | .bit_shift = 3, | |
3893 | .reg = 0x1010, | |
3894 | .module = TI_CLKM_CM, | |
3895 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3896 | }; | |
3897 | ||
3898 | static struct ti_clk gpt2_ick = { | |
3899 | .name = "gpt2_ick", | |
3900 | .clkdm_name = "per_clkdm", | |
3901 | .type = TI_CLK_GATE, | |
3902 | .data = &gpt2_ick_data, | |
3903 | }; | |
3904 | ||
3905 | static struct ti_clk_gate mmchs1_fck_data = { | |
3906 | .parent = "core_96m_fck", | |
3907 | .bit_shift = 24, | |
3908 | .reg = 0xa00, | |
3909 | .module = TI_CLKM_CM, | |
3910 | .flags = CLKF_WAIT, | |
3911 | }; | |
3912 | ||
3913 | static struct ti_clk mmchs1_fck = { | |
3914 | .name = "mmchs1_fck", | |
3915 | .clkdm_name = "core_l4_clkdm", | |
3916 | .type = TI_CLK_GATE, | |
3917 | .data = &mmchs1_fck_data, | |
3918 | }; | |
3919 | ||
3920 | static struct ti_clk_fixed dummy_apb_pclk_data = { | |
3921 | .frequency = 0x0, | |
3922 | }; | |
3923 | ||
3924 | static struct ti_clk dummy_apb_pclk = { | |
3925 | .name = "dummy_apb_pclk", | |
3926 | .type = TI_CLK_FIXED, | |
3927 | .data = &dummy_apb_pclk_data, | |
3928 | }; | |
3929 | ||
3930 | static struct ti_clk_gate gpio6_dbck_data = { | |
3931 | .parent = "per_32k_alwon_fck", | |
3932 | .bit_shift = 17, | |
3933 | .reg = 0x1000, | |
3934 | .module = TI_CLKM_CM, | |
3935 | }; | |
3936 | ||
3937 | static struct ti_clk gpio6_dbck = { | |
3938 | .name = "gpio6_dbck", | |
3939 | .clkdm_name = "per_clkdm", | |
3940 | .type = TI_CLK_GATE, | |
3941 | .data = &gpio6_dbck_data, | |
3942 | }; | |
3943 | ||
3944 | static struct ti_clk_gate uart2_ick_data = { | |
3945 | .parent = "core_l4_ick", | |
3946 | .bit_shift = 14, | |
3947 | .reg = 0xa10, | |
3948 | .module = TI_CLKM_CM, | |
3949 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3950 | }; | |
3951 | ||
3952 | static struct ti_clk uart2_ick = { | |
3953 | .name = "uart2_ick", | |
3954 | .clkdm_name = "core_l4_clkdm", | |
3955 | .type = TI_CLK_GATE, | |
3956 | .data = &uart2_ick_data, | |
3957 | }; | |
3958 | ||
3959 | static struct ti_clk_fixed_factor dpll4_x2_ck_data = { | |
3960 | .parent = "dpll4_ck", | |
3961 | .div = 1, | |
3962 | .mult = 2, | |
3963 | }; | |
3964 | ||
3965 | static struct ti_clk dpll4_x2_ck = { | |
3966 | .name = "dpll4_x2_ck", | |
3967 | .type = TI_CLK_FIXED_FACTOR, | |
3968 | .data = &dpll4_x2_ck_data, | |
3969 | }; | |
3970 | ||
3971 | static struct ti_clk_gate gpt7_ick_data = { | |
3972 | .parent = "per_l4_ick", | |
3973 | .bit_shift = 8, | |
3974 | .reg = 0x1010, | |
3975 | .module = TI_CLKM_CM, | |
3976 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
3977 | }; | |
3978 | ||
3979 | static struct ti_clk gpt7_ick = { | |
3980 | .name = "gpt7_ick", | |
3981 | .clkdm_name = "per_clkdm", | |
3982 | .type = TI_CLK_GATE, | |
3983 | .data = &gpt7_ick_data, | |
3984 | }; | |
3985 | ||
3986 | static struct ti_clk_gate dss_tv_fck_data = { | |
3987 | .parent = "omap_54m_fck", | |
3988 | .bit_shift = 2, | |
3989 | .reg = 0xe00, | |
3990 | .module = TI_CLKM_CM, | |
3991 | }; | |
3992 | ||
3993 | static struct ti_clk dss_tv_fck = { | |
3994 | .name = "dss_tv_fck", | |
3995 | .clkdm_name = "dss_clkdm", | |
3996 | .type = TI_CLK_GATE, | |
3997 | .data = &dss_tv_fck_data, | |
3998 | }; | |
3999 | ||
4000 | static struct ti_clk_gate mcbsp5_ick_data = { | |
4001 | .parent = "core_l4_ick", | |
4002 | .bit_shift = 10, | |
4003 | .reg = 0xa10, | |
4004 | .module = TI_CLKM_CM, | |
4005 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4006 | }; | |
4007 | ||
4008 | static struct ti_clk mcbsp5_ick = { | |
4009 | .name = "mcbsp5_ick", | |
4010 | .clkdm_name = "core_l4_clkdm", | |
4011 | .type = TI_CLK_GATE, | |
4012 | .data = &mcbsp5_ick_data, | |
4013 | }; | |
4014 | ||
4015 | static struct ti_clk_gate mcspi1_ick_data = { | |
4016 | .parent = "core_l4_ick", | |
4017 | .bit_shift = 18, | |
4018 | .reg = 0xa10, | |
4019 | .module = TI_CLKM_CM, | |
4020 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4021 | }; | |
4022 | ||
4023 | static struct ti_clk mcspi1_ick = { | |
4024 | .name = "mcspi1_ick", | |
4025 | .clkdm_name = "core_l4_clkdm", | |
4026 | .type = TI_CLK_GATE, | |
4027 | .data = &mcspi1_ick_data, | |
4028 | }; | |
4029 | ||
4030 | static struct ti_clk_gate d2d_26m_fck_data = { | |
4031 | .parent = "sys_ck", | |
4032 | .bit_shift = 3, | |
4033 | .reg = 0xa00, | |
4034 | .module = TI_CLKM_CM, | |
4035 | .flags = CLKF_WAIT, | |
4036 | }; | |
4037 | ||
4038 | static struct ti_clk d2d_26m_fck = { | |
4039 | .name = "d2d_26m_fck", | |
4040 | .clkdm_name = "d2d_clkdm", | |
4041 | .type = TI_CLK_GATE, | |
4042 | .data = &d2d_26m_fck_data, | |
4043 | }; | |
4044 | ||
4045 | static struct ti_clk_gate wdt3_ick_data = { | |
4046 | .parent = "per_l4_ick", | |
4047 | .bit_shift = 12, | |
4048 | .reg = 0x1010, | |
4049 | .module = TI_CLKM_CM, | |
4050 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4051 | }; | |
4052 | ||
4053 | static struct ti_clk wdt3_ick = { | |
4054 | .name = "wdt3_ick", | |
4055 | .clkdm_name = "per_clkdm", | |
4056 | .type = TI_CLK_GATE, | |
4057 | .data = &wdt3_ick_data, | |
4058 | }; | |
4059 | ||
4060 | static struct ti_clk_divider pclkx2_fck_data = { | |
4061 | .parent = "emu_src_ck", | |
4062 | .bit_shift = 6, | |
4063 | .max_div = 3, | |
4064 | .reg = 0x1140, | |
4065 | .module = TI_CLKM_CM, | |
4066 | .flags = CLKF_INDEX_STARTS_AT_ONE, | |
4067 | }; | |
4068 | ||
4069 | static struct ti_clk pclkx2_fck = { | |
4070 | .name = "pclkx2_fck", | |
4071 | .type = TI_CLK_DIVIDER, | |
4072 | .data = &pclkx2_fck_data, | |
4073 | }; | |
4074 | ||
4075 | static struct ti_clk_gate sha12_ick_data = { | |
4076 | .parent = "core_l4_ick", | |
4077 | .bit_shift = 27, | |
4078 | .reg = 0xa10, | |
4079 | .module = TI_CLKM_CM, | |
4080 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4081 | }; | |
4082 | ||
4083 | static struct ti_clk sha12_ick = { | |
4084 | .name = "sha12_ick", | |
4085 | .clkdm_name = "core_l4_clkdm", | |
4086 | .type = TI_CLK_GATE, | |
4087 | .data = &sha12_ick_data, | |
4088 | }; | |
4089 | ||
4090 | static struct ti_clk_gate emac_fck_data = { | |
4091 | .parent = "rmii_ck", | |
4092 | .bit_shift = 9, | |
4093 | .reg = 0x59c, | |
4094 | .module = TI_CLKM_SCRM, | |
4095 | }; | |
4096 | ||
4097 | static struct ti_clk emac_fck = { | |
4098 | .name = "emac_fck", | |
4099 | .type = TI_CLK_GATE, | |
4100 | .data = &emac_fck_data, | |
4101 | }; | |
4102 | ||
4103 | static struct ti_clk_composite gpt10_fck_data = { | |
4104 | .mux = &gpt10_mux_fck_data, | |
4105 | .gate = &gpt10_gate_fck_data, | |
4106 | }; | |
4107 | ||
4108 | static struct ti_clk gpt10_fck = { | |
4109 | .name = "gpt10_fck", | |
4110 | .type = TI_CLK_COMPOSITE, | |
4111 | .data = &gpt10_fck_data, | |
4112 | }; | |
4113 | ||
4114 | static struct ti_clk_gate wdt2_fck_data = { | |
4115 | .parent = "wkup_32k_fck", | |
4116 | .bit_shift = 5, | |
4117 | .reg = 0xc00, | |
4118 | .module = TI_CLKM_CM, | |
4119 | .flags = CLKF_WAIT, | |
4120 | }; | |
4121 | ||
4122 | static struct ti_clk wdt2_fck = { | |
4123 | .name = "wdt2_fck", | |
4124 | .clkdm_name = "wkup_clkdm", | |
4125 | .type = TI_CLK_GATE, | |
4126 | .data = &wdt2_fck_data, | |
4127 | }; | |
4128 | ||
4129 | static struct ti_clk_gate cam_ick_data = { | |
4130 | .parent = "l4_ick", | |
4131 | .bit_shift = 0, | |
4132 | .reg = 0xf10, | |
4133 | .module = TI_CLKM_CM, | |
4134 | .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE, | |
4135 | }; | |
4136 | ||
4137 | static struct ti_clk cam_ick = { | |
4138 | .name = "cam_ick", | |
4139 | .clkdm_name = "cam_clkdm", | |
4140 | .type = TI_CLK_GATE, | |
4141 | .data = &cam_ick_data, | |
4142 | }; | |
4143 | ||
4144 | static struct ti_clk_gate ssi_ick_3430es2_data = { | |
4145 | .parent = "ssi_l4_ick", | |
4146 | .bit_shift = 0, | |
4147 | .reg = 0xa10, | |
4148 | .module = TI_CLKM_CM, | |
4149 | .flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE, | |
4150 | }; | |
4151 | ||
4152 | static struct ti_clk ssi_ick_3430es2 = { | |
4153 | .name = "ssi_ick", | |
4154 | .clkdm_name = "core_l4_clkdm", | |
4155 | .type = TI_CLK_GATE, | |
4156 | .data = &ssi_ick_3430es2_data, | |
4157 | }; | |
4158 | ||
4159 | static struct ti_clk_gate gpio4_ick_data = { | |
4160 | .parent = "per_l4_ick", | |
4161 | .bit_shift = 15, | |
4162 | .reg = 0x1010, | |
4163 | .module = TI_CLKM_CM, | |
4164 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4165 | }; | |
4166 | ||
4167 | static struct ti_clk gpio4_ick = { | |
4168 | .name = "gpio4_ick", | |
4169 | .clkdm_name = "per_clkdm", | |
4170 | .type = TI_CLK_GATE, | |
4171 | .data = &gpio4_ick_data, | |
4172 | }; | |
4173 | ||
4174 | static struct ti_clk_gate wdt1_ick_data = { | |
4175 | .parent = "wkup_l4_ick", | |
4176 | .bit_shift = 4, | |
4177 | .reg = 0xc10, | |
4178 | .module = TI_CLKM_CM, | |
4179 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4180 | }; | |
4181 | ||
4182 | static struct ti_clk wdt1_ick = { | |
4183 | .name = "wdt1_ick", | |
4184 | .clkdm_name = "wkup_clkdm", | |
4185 | .type = TI_CLK_GATE, | |
4186 | .data = &wdt1_ick_data, | |
4187 | }; | |
4188 | ||
4189 | static struct ti_clk_gate rng_ick_data = { | |
4190 | .parent = "security_l4_ick2", | |
4191 | .bit_shift = 2, | |
4192 | .reg = 0xa14, | |
4193 | .module = TI_CLKM_CM, | |
4194 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4195 | }; | |
4196 | ||
4197 | static struct ti_clk rng_ick = { | |
4198 | .name = "rng_ick", | |
4199 | .type = TI_CLK_GATE, | |
4200 | .data = &rng_ick_data, | |
4201 | }; | |
4202 | ||
4203 | static struct ti_clk_gate icr_ick_data = { | |
4204 | .parent = "core_l4_ick", | |
4205 | .bit_shift = 29, | |
4206 | .reg = 0xa10, | |
4207 | .module = TI_CLKM_CM, | |
4208 | .flags = CLKF_OMAP3 | CLKF_INTERFACE, | |
4209 | }; | |
4210 | ||
4211 | static struct ti_clk icr_ick = { | |
4212 | .name = "icr_ick", | |
4213 | .clkdm_name = "core_l4_clkdm", | |
4214 | .type = TI_CLK_GATE, | |
4215 | .data = &icr_ick_data, | |
4216 | }; | |
4217 | ||
4218 | static struct ti_clk_gate sgx_ick_data = { | |
4219 | .parent = "l3_ick", | |
4220 | .bit_shift = 0, | |
4221 | .reg = 0xb10, | |
4222 | .module = TI_CLKM_CM, | |
4223 | .flags = CLKF_WAIT, | |
4224 | }; | |
4225 | ||
4226 | static struct ti_clk sgx_ick = { | |
4227 | .name = "sgx_ick", | |
4228 | .clkdm_name = "sgx_clkdm", | |
4229 | .type = TI_CLK_GATE, | |
4230 | .data = &sgx_ick_data, | |
4231 | }; | |
4232 | ||
4233 | static struct ti_clk_divider sys_clkout2_data = { | |
4234 | .parent = "clkout2_src_ck", | |
4235 | .bit_shift = 3, | |
4236 | .max_div = 64, | |
4237 | .reg = 0xd70, | |
4238 | .module = TI_CLKM_CM, | |
4239 | .flags = CLKF_INDEX_POWER_OF_TWO, | |
4240 | }; | |
4241 | ||
4242 | static struct ti_clk sys_clkout2 = { | |
4243 | .name = "sys_clkout2", | |
4244 | .type = TI_CLK_DIVIDER, | |
4245 | .data = &sys_clkout2_data, | |
4246 | }; | |
4247 | ||
4248 | static struct ti_clk_alias omap34xx_omap36xx_clks[] = { | |
4249 | CLK(NULL, "security_l4_ick2", &security_l4_ick2), | |
4250 | CLK(NULL, "aes1_ick", &aes1_ick), | |
4251 | CLK("omap_rng", "ick", &rng_ick), | |
4252 | CLK("omap3-rom-rng", "ick", &rng_ick), | |
4253 | CLK(NULL, "sha11_ick", &sha11_ick), | |
4254 | CLK(NULL, "des1_ick", &des1_ick), | |
4255 | CLK(NULL, "cam_mclk", &cam_mclk), | |
4256 | CLK(NULL, "cam_ick", &cam_ick), | |
4257 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck), | |
4258 | CLK(NULL, "security_l3_ick", &security_l3_ick), | |
4259 | CLK(NULL, "pka_ick", &pka_ick), | |
4260 | CLK(NULL, "icr_ick", &icr_ick), | |
4261 | CLK(NULL, "des2_ick", &des2_ick), | |
4262 | CLK(NULL, "mspro_ick", &mspro_ick), | |
4263 | CLK(NULL, "mailboxes_ick", &mailboxes_ick), | |
4264 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), | |
4265 | CLK(NULL, "sr1_fck", &sr1_fck), | |
4266 | CLK(NULL, "sr2_fck", &sr2_fck), | |
4267 | CLK(NULL, "sr_l4_ick", &sr_l4_ick), | |
4268 | CLK(NULL, "dpll2_fck", &dpll2_fck), | |
4269 | CLK(NULL, "dpll2_ck", &dpll2_ck), | |
4270 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck), | |
4271 | CLK(NULL, "iva2_ck", &iva2_ck), | |
4272 | CLK(NULL, "modem_fck", &modem_fck), | |
4273 | CLK(NULL, "sad2d_ick", &sad2d_ick), | |
4274 | CLK(NULL, "mad2d_ick", &mad2d_ick), | |
4275 | CLK(NULL, "mspro_fck", &mspro_fck), | |
4276 | { NULL }, | |
4277 | }; | |
4278 | ||
4279 | static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = { | |
4280 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2), | |
4281 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2), | |
4282 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2), | |
4283 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2), | |
4284 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2), | |
4285 | CLK(NULL, "sys_d2_ck", &sys_d2_ck), | |
4286 | CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck), | |
4287 | CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck), | |
4288 | CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck), | |
4289 | CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck), | |
4290 | CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck), | |
4291 | CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck), | |
4292 | CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck), | |
4293 | CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck), | |
4294 | CLK(NULL, "usim_fck", &usim_fck), | |
4295 | CLK(NULL, "usim_ick", &usim_ick), | |
4296 | { NULL }, | |
4297 | }; | |
4298 | ||
4299 | static struct ti_clk_alias omap3xxx_clks[] = { | |
4300 | CLK(NULL, "apb_pclk", &dummy_apb_pclk), | |
4301 | CLK(NULL, "omap_32k_fck", &omap_32k_fck), | |
4302 | CLK(NULL, "virt_12m_ck", &virt_12m_ck), | |
4303 | CLK(NULL, "virt_13m_ck", &virt_13m_ck), | |
4304 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), | |
4305 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), | |
4306 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck), | |
4307 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck), | |
4308 | CLK(NULL, "osc_sys_ck", &osc_sys_ck), | |
4309 | CLK("twl", "fck", &osc_sys_ck), | |
4310 | CLK(NULL, "sys_ck", &sys_ck), | |
4311 | CLK(NULL, "timer_sys_ck", &sys_ck), | |
4312 | CLK(NULL, "dpll4_ck", &dpll4_ck), | |
4313 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck), | |
4314 | CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck), | |
4315 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck), | |
4316 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck), | |
4317 | CLK(NULL, "dpll3_ck", &dpll3_ck), | |
4318 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck), | |
4319 | CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck), | |
4320 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck), | |
4321 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck), | |
4322 | CLK(NULL, "sys_altclk", &sys_altclk), | |
4323 | CLK(NULL, "mcbsp_clks", &mcbsp_clks), | |
4324 | CLK(NULL, "sys_clkout1", &sys_clkout1), | |
4325 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck), | |
4326 | CLK(NULL, "core_ck", &core_ck), | |
4327 | CLK(NULL, "dpll1_fck", &dpll1_fck), | |
4328 | CLK(NULL, "dpll1_ck", &dpll1_ck), | |
4329 | CLK(NULL, "cpufreq_ck", &dpll1_ck), | |
4330 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck), | |
4331 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck), | |
4332 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck), | |
4333 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck), | |
4334 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck), | |
4335 | CLK(NULL, "cm_96m_fck", &cm_96m_fck), | |
4336 | CLK(NULL, "omap_96m_fck", &omap_96m_fck), | |
4337 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck), | |
4338 | CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck), | |
4339 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck), | |
4340 | CLK(NULL, "omap_54m_fck", &omap_54m_fck), | |
4341 | CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck), | |
4342 | CLK(NULL, "omap_48m_fck", &omap_48m_fck), | |
4343 | CLK(NULL, "omap_12m_fck", &omap_12m_fck), | |
4344 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck), | |
4345 | CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck), | |
4346 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck), | |
4347 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck), | |
4348 | CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck), | |
4349 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck), | |
4350 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck), | |
4351 | CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck), | |
4352 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck), | |
4353 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck), | |
4354 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck), | |
4355 | CLK(NULL, "sys_clkout2", &sys_clkout2), | |
4356 | CLK(NULL, "corex2_fck", &corex2_fck), | |
4357 | CLK(NULL, "mpu_ck", &mpu_ck), | |
4358 | CLK(NULL, "arm_fck", &arm_fck), | |
4359 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck), | |
4360 | CLK(NULL, "l3_ick", &l3_ick), | |
4361 | CLK(NULL, "l4_ick", &l4_ick), | |
4362 | CLK(NULL, "rm_ick", &rm_ick), | |
4363 | CLK(NULL, "timer_32k_ck", &omap_32k_fck), | |
4364 | CLK(NULL, "gpt10_fck", &gpt10_fck), | |
4365 | CLK(NULL, "gpt11_fck", &gpt11_fck), | |
4366 | CLK(NULL, "core_96m_fck", &core_96m_fck), | |
4367 | CLK(NULL, "mmchs2_fck", &mmchs2_fck), | |
4368 | CLK(NULL, "mmchs1_fck", &mmchs1_fck), | |
4369 | CLK(NULL, "i2c3_fck", &i2c3_fck), | |
4370 | CLK(NULL, "i2c2_fck", &i2c2_fck), | |
4371 | CLK(NULL, "i2c1_fck", &i2c1_fck), | |
4372 | CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), | |
4373 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), | |
4374 | CLK(NULL, "core_48m_fck", &core_48m_fck), | |
4375 | CLK(NULL, "mcspi4_fck", &mcspi4_fck), | |
4376 | CLK(NULL, "mcspi3_fck", &mcspi3_fck), | |
4377 | CLK(NULL, "mcspi2_fck", &mcspi2_fck), | |
4378 | CLK(NULL, "mcspi1_fck", &mcspi1_fck), | |
4379 | CLK(NULL, "uart2_fck", &uart2_fck), | |
4380 | CLK(NULL, "uart1_fck", &uart1_fck), | |
4381 | CLK(NULL, "core_12m_fck", &core_12m_fck), | |
4382 | CLK("omap_hdq.0", "fck", &hdq_fck), | |
4383 | CLK(NULL, "hdq_fck", &hdq_fck), | |
4384 | CLK(NULL, "core_l3_ick", &core_l3_ick), | |
4385 | CLK(NULL, "sdrc_ick", &sdrc_ick), | |
4386 | CLK(NULL, "gpmc_fck", &gpmc_fck), | |
4387 | CLK(NULL, "core_l4_ick", &core_l4_ick), | |
4388 | CLK("omap_hsmmc.1", "ick", &mmchs2_ick), | |
4389 | CLK("omap_hsmmc.0", "ick", &mmchs1_ick), | |
4390 | CLK(NULL, "mmchs2_ick", &mmchs2_ick), | |
4391 | CLK(NULL, "mmchs1_ick", &mmchs1_ick), | |
4392 | CLK("omap_hdq.0", "ick", &hdq_ick), | |
4393 | CLK(NULL, "hdq_ick", &hdq_ick), | |
4394 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick), | |
4395 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick), | |
4396 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick), | |
4397 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick), | |
4398 | CLK(NULL, "mcspi4_ick", &mcspi4_ick), | |
4399 | CLK(NULL, "mcspi3_ick", &mcspi3_ick), | |
4400 | CLK(NULL, "mcspi2_ick", &mcspi2_ick), | |
4401 | CLK(NULL, "mcspi1_ick", &mcspi1_ick), | |
4402 | CLK("omap_i2c.3", "ick", &i2c3_ick), | |
4403 | CLK("omap_i2c.2", "ick", &i2c2_ick), | |
4404 | CLK("omap_i2c.1", "ick", &i2c1_ick), | |
4405 | CLK(NULL, "i2c3_ick", &i2c3_ick), | |
4406 | CLK(NULL, "i2c2_ick", &i2c2_ick), | |
4407 | CLK(NULL, "i2c1_ick", &i2c1_ick), | |
4408 | CLK(NULL, "uart2_ick", &uart2_ick), | |
4409 | CLK(NULL, "uart1_ick", &uart1_ick), | |
4410 | CLK(NULL, "gpt11_ick", &gpt11_ick), | |
4411 | CLK(NULL, "gpt10_ick", &gpt10_ick), | |
4412 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), | |
4413 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), | |
4414 | CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), | |
4415 | CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), | |
4416 | CLK(NULL, "omapctrl_ick", &omapctrl_ick), | |
4417 | CLK(NULL, "dss_tv_fck", &dss_tv_fck), | |
4418 | CLK(NULL, "dss_96m_fck", &dss_96m_fck), | |
4419 | CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck), | |
4420 | CLK(NULL, "init_60m_fclk", &dummy_ck), | |
4421 | CLK(NULL, "gpt1_fck", &gpt1_fck), | |
4422 | CLK(NULL, "aes2_ick", &aes2_ick), | |
4423 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck), | |
4424 | CLK(NULL, "gpio1_dbck", &gpio1_dbck), | |
4425 | CLK(NULL, "sha12_ick", &sha12_ick), | |
4426 | CLK(NULL, "wdt2_fck", &wdt2_fck), | |
4427 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick), | |
4428 | CLK("omap_wdt", "ick", &wdt2_ick), | |
4429 | CLK(NULL, "wdt2_ick", &wdt2_ick), | |
4430 | CLK(NULL, "wdt1_ick", &wdt1_ick), | |
4431 | CLK(NULL, "gpio1_ick", &gpio1_ick), | |
4432 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick), | |
4433 | CLK(NULL, "gpt12_ick", &gpt12_ick), | |
4434 | CLK(NULL, "gpt1_ick", &gpt1_ick), | |
4435 | CLK(NULL, "per_96m_fck", &per_96m_fck), | |
4436 | CLK(NULL, "per_48m_fck", &per_48m_fck), | |
4437 | CLK(NULL, "uart3_fck", &uart3_fck), | |
4438 | CLK(NULL, "gpt2_fck", &gpt2_fck), | |
4439 | CLK(NULL, "gpt3_fck", &gpt3_fck), | |
4440 | CLK(NULL, "gpt4_fck", &gpt4_fck), | |
4441 | CLK(NULL, "gpt5_fck", &gpt5_fck), | |
4442 | CLK(NULL, "gpt6_fck", &gpt6_fck), | |
4443 | CLK(NULL, "gpt7_fck", &gpt7_fck), | |
4444 | CLK(NULL, "gpt8_fck", &gpt8_fck), | |
4445 | CLK(NULL, "gpt9_fck", &gpt9_fck), | |
4446 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck), | |
4447 | CLK(NULL, "gpio6_dbck", &gpio6_dbck), | |
4448 | CLK(NULL, "gpio5_dbck", &gpio5_dbck), | |
4449 | CLK(NULL, "gpio4_dbck", &gpio4_dbck), | |
4450 | CLK(NULL, "gpio3_dbck", &gpio3_dbck), | |
4451 | CLK(NULL, "gpio2_dbck", &gpio2_dbck), | |
4452 | CLK(NULL, "wdt3_fck", &wdt3_fck), | |
4453 | CLK(NULL, "per_l4_ick", &per_l4_ick), | |
4454 | CLK(NULL, "gpio6_ick", &gpio6_ick), | |
4455 | CLK(NULL, "gpio5_ick", &gpio5_ick), | |
4456 | CLK(NULL, "gpio4_ick", &gpio4_ick), | |
4457 | CLK(NULL, "gpio3_ick", &gpio3_ick), | |
4458 | CLK(NULL, "gpio2_ick", &gpio2_ick), | |
4459 | CLK(NULL, "wdt3_ick", &wdt3_ick), | |
4460 | CLK(NULL, "uart3_ick", &uart3_ick), | |
4461 | CLK(NULL, "uart4_ick", &uart4_ick), | |
4462 | CLK(NULL, "gpt9_ick", &gpt9_ick), | |
4463 | CLK(NULL, "gpt8_ick", &gpt8_ick), | |
4464 | CLK(NULL, "gpt7_ick", &gpt7_ick), | |
4465 | CLK(NULL, "gpt6_ick", &gpt6_ick), | |
4466 | CLK(NULL, "gpt5_ick", &gpt5_ick), | |
4467 | CLK(NULL, "gpt4_ick", &gpt4_ick), | |
4468 | CLK(NULL, "gpt3_ick", &gpt3_ick), | |
4469 | CLK(NULL, "gpt2_ick", &gpt2_ick), | |
4470 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), | |
4471 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), | |
4472 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), | |
4473 | CLK(NULL, "mcbsp4_ick", &mcbsp2_ick), | |
4474 | CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), | |
4475 | CLK(NULL, "mcbsp2_ick", &mcbsp4_ick), | |
4476 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), | |
4477 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), | |
4478 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), | |
4479 | CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck), | |
4480 | CLK("etb", "emu_src_ck", &emu_src_ck), | |
4481 | CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck), | |
4482 | CLK(NULL, "emu_src_ck", &emu_src_ck), | |
4483 | CLK(NULL, "pclk_fck", &pclk_fck), | |
4484 | CLK(NULL, "pclkx2_fck", &pclkx2_fck), | |
4485 | CLK(NULL, "atclk_fck", &atclk_fck), | |
4486 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck), | |
4487 | CLK(NULL, "traceclk_fck", &traceclk_fck), | |
4488 | CLK(NULL, "secure_32k_fck", &secure_32k_fck), | |
4489 | CLK(NULL, "gpt12_fck", &gpt12_fck), | |
4490 | CLK(NULL, "wdt1_fck", &wdt1_fck), | |
4491 | { NULL }, | |
4492 | }; | |
4493 | ||
4494 | static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = { | |
4495 | CLK(NULL, "dpll5_ck", &dpll5_ck), | |
4496 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck), | |
4497 | CLK(NULL, "core_d3_ck", &core_d3_ck), | |
4498 | CLK(NULL, "core_d4_ck", &core_d4_ck), | |
4499 | CLK(NULL, "core_d6_ck", &core_d6_ck), | |
4500 | CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck), | |
4501 | CLK(NULL, "core_d2_ck", &core_d2_ck), | |
4502 | CLK(NULL, "corex2_d3_fck", &corex2_d3_fck), | |
4503 | CLK(NULL, "corex2_d5_fck", &corex2_d5_fck), | |
4504 | CLK(NULL, "sgx_fck", &sgx_fck), | |
4505 | CLK(NULL, "sgx_ick", &sgx_ick), | |
4506 | CLK(NULL, "cpefuse_fck", &cpefuse_fck), | |
4507 | CLK(NULL, "ts_fck", &ts_fck), | |
4508 | CLK(NULL, "usbtll_fck", &usbtll_fck), | |
4509 | CLK(NULL, "usbtll_ick", &usbtll_ick), | |
4510 | CLK("omap_hsmmc.2", "ick", &mmchs3_ick), | |
4511 | CLK(NULL, "mmchs3_ick", &mmchs3_ick), | |
4512 | CLK(NULL, "mmchs3_fck", &mmchs3_fck), | |
4513 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2), | |
4514 | CLK("omapdss_dss", "ick", &dss_ick_3430es2), | |
4515 | CLK(NULL, "dss_ick", &dss_ick_3430es2), | |
4516 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), | |
4517 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), | |
4518 | CLK(NULL, "usbhost_ick", &usbhost_ick), | |
4519 | { NULL }, | |
4520 | }; | |
4521 | ||
4522 | static struct ti_clk_alias omap3430es1_clks[] = { | |
4523 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck), | |
4524 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck), | |
4525 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick), | |
4526 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck), | |
4527 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck), | |
4528 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck), | |
4529 | CLK(NULL, "fshostusb_fck", &fshostusb_fck), | |
4530 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1), | |
4531 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1), | |
4532 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1), | |
4533 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1), | |
4534 | CLK(NULL, "fac_ick", &fac_ick), | |
4535 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1), | |
4536 | CLK(NULL, "usb_l4_ick", &usb_l4_ick), | |
4537 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1), | |
4538 | CLK("omapdss_dss", "ick", &dss_ick_3430es1), | |
4539 | CLK(NULL, "dss_ick", &dss_ick_3430es1), | |
4540 | { NULL }, | |
4541 | }; | |
4542 | ||
4543 | static struct ti_clk_alias omap36xx_clks[] = { | |
4544 | CLK(NULL, "uart4_fck", &uart4_fck), | |
4545 | { NULL }, | |
4546 | }; | |
4547 | ||
4548 | static struct ti_clk_alias am35xx_clks[] = { | |
4549 | CLK(NULL, "ipss_ick", &ipss_ick), | |
4550 | CLK(NULL, "rmii_ck", &rmii_ck), | |
4551 | CLK(NULL, "pclk_ck", &pclk_ck), | |
4552 | CLK(NULL, "emac_ick", &emac_ick), | |
4553 | CLK(NULL, "emac_fck", &emac_fck), | |
4554 | CLK("davinci_emac.0", NULL, &emac_ick), | |
4555 | CLK("davinci_mdio.0", NULL, &emac_fck), | |
4556 | CLK("vpfe-capture", "master", &vpfe_ick), | |
4557 | CLK("vpfe-capture", "slave", &vpfe_fck), | |
4558 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx), | |
4559 | CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx), | |
4560 | CLK(NULL, "hecc_ck", &hecc_ck), | |
4561 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx), | |
4562 | CLK(NULL, "uart4_fck", &uart4_fck_am35xx), | |
4563 | { NULL }, | |
4564 | }; | |
4565 | ||
4566 | static struct ti_clk *omap36xx_clk_patches[] = { | |
4567 | &dpll4_m3x2_ck_omap36xx, | |
4568 | &dpll3_m3x2_ck_omap36xx, | |
4569 | &dpll4_m6x2_ck_omap36xx, | |
4570 | &dpll4_m2x2_ck_omap36xx, | |
4571 | &dpll4_m5x2_ck_omap36xx, | |
4572 | &dpll4_ck_omap36xx, | |
4573 | NULL, | |
4574 | }; | |
4575 | ||
4576 | static const char *enable_init_clks[] = { | |
4577 | "sdrc_ick", | |
4578 | "gpmc_fck", | |
4579 | "omapctrl_ick", | |
4580 | }; | |
4581 | ||
4582 | static void __init omap3_clk_legacy_common_init(void) | |
4583 | { | |
4584 | omap2_clk_disable_autoidle_all(); | |
4585 | ||
4586 | omap2_clk_enable_init_clocks(enable_init_clks, | |
4587 | ARRAY_SIZE(enable_init_clks)); | |
4588 | ||
4589 | pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", | |
4590 | (clk_get_rate(osc_sys_ck.clk) / 1000000), | |
4591 | (clk_get_rate(osc_sys_ck.clk) / 100000) % 10, | |
4592 | (clk_get_rate(core_ck.clk) / 1000000), | |
4593 | (clk_get_rate(arm_fck.clk) / 1000000)); | |
4594 | } | |
4595 | ||
4596 | int __init omap3430es1_clk_legacy_init(void) | |
4597 | { | |
4598 | int r; | |
4599 | ||
4600 | r = ti_clk_register_legacy_clks(omap3430es1_clks); | |
4601 | r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks); | |
4602 | r |= ti_clk_register_legacy_clks(omap3xxx_clks); | |
4603 | ||
4604 | omap3_clk_legacy_common_init(); | |
4605 | ||
4606 | return r; | |
4607 | } | |
4608 | ||
4609 | int __init omap3430_clk_legacy_init(void) | |
4610 | { | |
4611 | int r; | |
4612 | ||
4613 | r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks); | |
4614 | r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks); | |
4615 | r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks); | |
4616 | r |= ti_clk_register_legacy_clks(omap3xxx_clks); | |
4617 | ||
4618 | omap3_clk_legacy_common_init(); | |
4619 | omap3_clk_lock_dpll5(); | |
4620 | ||
4621 | return r; | |
4622 | } | |
4623 | ||
4624 | int __init omap36xx_clk_legacy_init(void) | |
4625 | { | |
4626 | int r; | |
4627 | ||
4628 | ti_clk_patch_legacy_clks(omap36xx_clk_patches); | |
4629 | r = ti_clk_register_legacy_clks(omap36xx_clks); | |
4630 | r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks); | |
4631 | r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks); | |
4632 | r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks); | |
4633 | r |= ti_clk_register_legacy_clks(omap3xxx_clks); | |
4634 | ||
4635 | omap3_clk_legacy_common_init(); | |
4636 | omap3_clk_lock_dpll5(); | |
4637 | ||
4638 | return r; | |
4639 | } | |
4640 | ||
4641 | int __init am35xx_clk_legacy_init(void) | |
4642 | { | |
4643 | int r; | |
4644 | ||
4645 | r = ti_clk_register_legacy_clks(am35xx_clks); | |
4646 | r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks); | |
4647 | r |= ti_clk_register_legacy_clks(omap3xxx_clks); | |
4648 | ||
4649 | omap3_clk_legacy_common_init(); | |
4650 | omap3_clk_lock_dpll5(); | |
4651 | ||
4652 | return r; | |
4653 | } |