[mirror_ubuntu-jammy-kernel.git] / drivers / clk / ti / clk-dra7-atl.c

/*
 * DRA7 ATL (Audio Tracking Logic) clock driver
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/init.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/clk/ti.h>

#include "clock.h"

#define DRA7_ATL_INSTANCES	4

#define DRA7_ATL_PPMR_REG(id)		(0x200 + (id * 0x80))
#define DRA7_ATL_BBSR_REG(id)		(0x204 + (id * 0x80))
#define DRA7_ATL_ATLCR_REG(id)		(0x208 + (id * 0x80))
#define DRA7_ATL_SWEN_REG(id)		(0x210 + (id * 0x80))
#define DRA7_ATL_BWSMUX_REG(id)		(0x214 + (id * 0x80))
#define DRA7_ATL_AWSMUX_REG(id)		(0x218 + (id * 0x80))
#define DRA7_ATL_PCLKMUX_REG(id)	(0x21c + (id * 0x80))

#define DRA7_ATL_SWEN			BIT(0)
#define DRA7_ATL_DIVIDER_MASK		(0x1f)
#define DRA7_ATL_PCLKMUX		BIT(0)
struct dra7_atl_clock_info;

struct dra7_atl_desc {
	struct clk *clk;
	struct clk_hw hw;
	struct dra7_atl_clock_info *cinfo;
	int id;

	bool probed;		/* the driver for the IP has been loaded */
	bool valid;		/* configured */
	bool enabled;
	u32 bws;		/* Baseband Word Select Mux */
	u32 aws;		/* Audio Word Select Mux */
	u32 divider;		/* Cached divider value */
};

struct dra7_atl_clock_info {
	struct device *dev;
	void __iomem *iobase;

	struct dra7_atl_desc *cdesc;
};

#define to_atl_desc(_hw)	container_of(_hw, struct dra7_atl_desc, hw)

static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
			     u32 val)
{
	__raw_writel(val, cinfo->iobase + reg);
}

static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
{
	return __raw_readl(cinfo->iobase + reg);
}

static int atl_clk_enable(struct clk_hw *hw)
{
	struct dra7_atl_desc *cdesc = to_atl_desc(hw);

	if (!cdesc->probed)
		goto out;

	if (unlikely(!cdesc->valid))
		dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
			 cdesc->id);
	pm_runtime_get_sync(cdesc->cinfo->dev);

	atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
		  cdesc->divider - 1);
	atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);

out:
	cdesc->enabled = true;

	return 0;
}

static void atl_clk_disable(struct clk_hw *hw)
{
	struct dra7_atl_desc *cdesc = to_atl_desc(hw);

	if (!cdesc->probed)
		goto out;

	atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
	pm_runtime_put_sync(cdesc->cinfo->dev);

out:
	cdesc->enabled = false;
}

static int atl_clk_is_enabled(struct clk_hw *hw)
{
	struct dra7_atl_desc *cdesc = to_atl_desc(hw);

	return cdesc->enabled;
}

static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
					 unsigned long parent_rate)
{
	struct dra7_atl_desc *cdesc = to_atl_desc(hw);

	return parent_rate / cdesc->divider;
}

static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
			       unsigned long *parent_rate)
{
	unsigned divider;

	divider = (*parent_rate + rate / 2) / rate;
	if (divider > DRA7_ATL_DIVIDER_MASK + 1)
		divider = DRA7_ATL_DIVIDER_MASK + 1;

	return *parent_rate / divider;
}

static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{
	struct dra7_atl_desc *cdesc;
	u32 divider;

	if (!hw || !rate)
		return -EINVAL;

	cdesc = to_atl_desc(hw);
	divider = ((parent_rate + rate / 2) / rate) - 1;
	if (divider > DRA7_ATL_DIVIDER_MASK)
		divider = DRA7_ATL_DIVIDER_MASK;

	cdesc->divider = divider + 1;

	return 0;
}

static const struct clk_ops atl_clk_ops = {
	.enable		= atl_clk_enable,
	.disable	= atl_clk_disable,
	.is_enabled	= atl_clk_is_enabled,
	.recalc_rate	= atl_clk_recalc_rate,
	.round_rate	= atl_clk_round_rate,
	.set_rate	= atl_clk_set_rate,
};

static void __init of_dra7_atl_clock_setup(struct device_node *node)
{
	struct dra7_atl_desc *clk_hw = NULL;
	struct clk_init_data init = { NULL };
	const char **parent_names = NULL;
	struct clk *clk;

	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	if (!clk_hw) {
		pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
		return;
	}

	clk_hw->hw.init = &init;
	clk_hw->divider = 1;
	init.name = node->name;
	init.ops = &atl_clk_ops;
	init.flags = CLK_IGNORE_UNUSED;
	init.num_parents = of_clk_get_parent_count(node);

	if (init.num_parents != 1) {
		pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
		       node);
		goto cleanup;
	}

	parent_names = kzalloc(sizeof(char *), GFP_KERNEL);

	if (!parent_names)
		goto cleanup;

	parent_names[0] = of_clk_get_parent_name(node, 0);

	init.parent_names = parent_names;

	clk = ti_clk_register(NULL, &clk_hw->hw, node->name);

	if (!IS_ERR(clk)) {
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
		kfree(parent_names);
		return;
	}
cleanup:
	kfree(parent_names);
	kfree(clk_hw);
}
CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);

static int of_dra7_atl_clk_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct dra7_atl_clock_info *cinfo;
	int i;
	int ret = 0;

	if (!node)
		return -ENODEV;

	cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
	if (!cinfo)
		return -ENOMEM;

	cinfo->iobase = of_iomap(node, 0);
	cinfo->dev = &pdev->dev;
	pm_runtime_enable(cinfo->dev);

	pm_runtime_get_sync(cinfo->dev);
	atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);

	for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
		struct device_node *cfg_node;
		char prop[5];
		struct dra7_atl_desc *cdesc;
		struct of_phandle_args clkspec;
		struct clk *clk;
		int rc;

		rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
						NULL, i, &clkspec);

		if (rc) {
			pr_err("%s: failed to lookup atl clock %d\n", __func__,
			       i);
			return -EINVAL;
		}

		clk = of_clk_get_from_provider(&clkspec);
		if (IS_ERR(clk)) {
			pr_err("%s: failed to get atl clock %d from provider\n",
			       __func__, i);
			return PTR_ERR(clk);
		}

		cdesc = to_atl_desc(__clk_get_hw(clk));
		cdesc->cinfo = cinfo;
		cdesc->id = i;

		/* Get configuration for the ATL instances */
		snprintf(prop, sizeof(prop), "atl%u", i);
		cfg_node = of_get_child_by_name(node, prop);
		if (cfg_node) {
			ret = of_property_read_u32(cfg_node, "bws",
						   &cdesc->bws);
			ret |= of_property_read_u32(cfg_node, "aws",
						    &cdesc->aws);
			if (!ret) {
				cdesc->valid = true;
				atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
					  cdesc->bws);
				atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
					  cdesc->aws);
			}
			of_node_put(cfg_node);
		}

		cdesc->probed = true;
		/*
		 * Enable the clock if it has been asked prior to loading the
		 * hw driver
		 */
		if (cdesc->enabled)
			atl_clk_enable(__clk_get_hw(clk));
	}
	pm_runtime_put_sync(cinfo->dev);

	return ret;
}

static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
	{ .compatible = "ti,dra7-atl", },
	{},
};

static struct platform_driver dra7_atl_clk_driver = {
	.driver = {
		.name = "dra7-atl",
		.suppress_bind_attrs = true,
		.of_match_table = of_dra7_atl_clk_match_tbl,
	},
	.probe = of_dra7_atl_clk_probe,
};
builtin_platform_driver(dra7_atl_clk_driver);
Commit	Line	Data
9ac33b0c PU	1	/*
	2	* DRA7 ATL (Audio Tracking Logic) clock driver
	3	*
	4	* Copyright (C) 2013 Texas Instruments, Inc.
	5	*
	6	* Peter Ujfalusi <peter.ujfalusi@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
172ff5a2	18	#include <linux/init.h>
1b29e601	19	#include <linux/clk.h>
9ac33b0c PU	20	#include <linux/clk-provider.h>
	21	#include <linux/slab.h>
	22	#include <linux/io.h>
	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/pm_runtime.h>
1ae79c46 TK	27	#include <linux/clk/ti.h>
	28
	29	#include "clock.h"
9ac33b0c PU	30
	31	#define DRA7_ATL_INSTANCES 4
	32
	33	#define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
	34	#define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
	35	#define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
	36	#define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
	37	#define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
	38	#define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
	39	#define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
	40
	41	#define DRA7_ATL_SWEN BIT(0)
	42	#define DRA7_ATL_DIVIDER_MASK (0x1f)
	43	#define DRA7_ATL_PCLKMUX BIT(0)
	44	struct dra7_atl_clock_info;
	45
	46	struct dra7_atl_desc {
	47	struct clk *clk;
	48	struct clk_hw hw;
	49	struct dra7_atl_clock_info *cinfo;
	50	int id;
	51
	52	bool probed; /* the driver for the IP has been loaded */
	53	bool valid; /* configured */
	54	bool enabled;
	55	u32 bws; /* Baseband Word Select Mux */
	56	u32 aws; /* Audio Word Select Mux */
	57	u32 divider; /* Cached divider value */
	58	};
	59
	60	struct dra7_atl_clock_info {
	61	struct device *dev;
	62	void __iomem *iobase;
	63
	64	struct dra7_atl_desc *cdesc;
	65	};
	66
	67	#define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
	68
	69	static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
	70	u32 val)
	71	{
	72	__raw_writel(val, cinfo->iobase + reg);
	73	}
	74
	75	static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
	76	{
	77	return __raw_readl(cinfo->iobase + reg);
	78	}
	79
	80	static int atl_clk_enable(struct clk_hw *hw)
	81	{
	82	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
	83
	84	if (!cdesc->probed)
	85	goto out;
	86
	87	if (unlikely(!cdesc->valid))
	88	dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
	89	cdesc->id);
	90	pm_runtime_get_sync(cdesc->cinfo->dev);
	91
	92	atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
	93	cdesc->divider - 1);
94	atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
95
96	out:
97	cdesc->enabled = true;
98
99	return 0;
100	}
101
102	static void atl_clk_disable(struct clk_hw *hw)
103	{
104	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
105
106	if (!cdesc->probed)
107	goto out;
108
109	atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
110	pm_runtime_put_sync(cdesc->cinfo->dev);
111
112	out:
113	cdesc->enabled = false;
114	}
115
116	static int atl_clk_is_enabled(struct clk_hw *hw)
117	{
118	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
119
120	return cdesc->enabled;
121	}
122
123	static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
124	unsigned long parent_rate)
125	{
126	struct dra7_atl_desc *cdesc = to_atl_desc(hw);
127
128	return parent_rate / cdesc->divider;
129	}
130
131	static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
132	unsigned long *parent_rate)
133	{
134	unsigned divider;
135
136	divider = (*parent_rate + rate / 2) / rate;
137	if (divider > DRA7_ATL_DIVIDER_MASK + 1)
138	divider = DRA7_ATL_DIVIDER_MASK + 1;
139
140	return *parent_rate / divider;
141	}
142
143	static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
144	unsigned long parent_rate)
145	{
20411dad	146	struct dra7_atl_desc *cdesc;
9ac33b0c PU	147	u32 divider;
9ac33b0c PU	148
20411dad NM	149	if (!hw \|\| !rate)
	150	return -EINVAL;
	151
	152	cdesc = to_atl_desc(hw);
9ac33b0c PU	153	divider = ((parent_rate + rate / 2) / rate) - 1;
	154	if (divider > DRA7_ATL_DIVIDER_MASK)
	155	divider = DRA7_ATL_DIVIDER_MASK;
	156
	157	cdesc->divider = divider + 1;
	158
	159	return 0;
	160	}
	161
412d6b47	162	static const struct clk_ops atl_clk_ops = {
9ac33b0c PU	163	.enable = atl_clk_enable,
	164	.disable = atl_clk_disable,
	165	.is_enabled = atl_clk_is_enabled,
	166	.recalc_rate = atl_clk_recalc_rate,
	167	.round_rate = atl_clk_round_rate,
	168	.set_rate = atl_clk_set_rate,
	169	};
	170
	171	static void __init of_dra7_atl_clock_setup(struct device_node *node)
	172	{
	173	struct dra7_atl_desc *clk_hw = NULL;
412d6b47	174	struct clk_init_data init = { NULL };
9ac33b0c PU	175	const char **parent_names = NULL;
	176	struct clk *clk;
	177
	178	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	179	if (!clk_hw) {
	180	pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
	181	return;
	182	}
	183
	184	clk_hw->hw.init = &init;
	185	clk_hw->divider = 1;
	186	init.name = node->name;
	187	init.ops = &atl_clk_ops;
	188	init.flags = CLK_IGNORE_UNUSED;
	189	init.num_parents = of_clk_get_parent_count(node);
	190
	191	if (init.num_parents != 1) {
e665f029 RH	192	pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
e665f029 RH	193	node);
9ac33b0c PU	194	goto cleanup;
	195	}
	196
	197	parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
	198
	199	if (!parent_names)
	200	goto cleanup;
	201
	202	parent_names[0] = of_clk_get_parent_name(node, 0);
	203
	204	init.parent_names = parent_names;
	205
1ae79c46	206	clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
9ac33b0c PU	207
	208	if (!IS_ERR(clk)) {
	209	of_clk_add_provider(node, of_clk_src_simple_get, clk);
73b5d5f7	210	kfree(parent_names);
9ac33b0c PU	211	return;
	212	}
	213	cleanup:
	214	kfree(parent_names);
	215	kfree(clk_hw);
	216	}
	217	CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
	218
	219	static int of_dra7_atl_clk_probe(struct platform_device *pdev)
	220	{
	221	struct device_node *node = pdev->dev.of_node;
	222	struct dra7_atl_clock_info *cinfo;
	223	int i;
	224	int ret = 0;
	225
	226	if (!node)
	227	return -ENODEV;
	228
	229	cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
	230	if (!cinfo)
	231	return -ENOMEM;
	232
	233	cinfo->iobase = of_iomap(node, 0);
	234	cinfo->dev = &pdev->dev;
	235	pm_runtime_enable(cinfo->dev);
	236
	237	pm_runtime_get_sync(cinfo->dev);
	238	atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
	239
	240	for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
	241	struct device_node *cfg_node;
	242	char prop[5];
	243	struct dra7_atl_desc *cdesc;
	244	struct of_phandle_args clkspec;
	245	struct clk *clk;
	246	int rc;
	247
	248	rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
	249	NULL, i, &clkspec);
	250
	251	if (rc) {
	252	pr_err("%s: failed to lookup atl clock %d\n", __func__,
	253	i);
	254	return -EINVAL;
	255	}
	256
	257	clk = of_clk_get_from_provider(&clkspec);
e0cdcda5 KK	258	if (IS_ERR(clk)) {
	259	pr_err("%s: failed to get atl clock %d from provider\n",
	260	__func__, i);
	261	return PTR_ERR(clk);
	262	}
9ac33b0c PU	263
	264	cdesc = to_atl_desc(__clk_get_hw(clk));
	265	cdesc->cinfo = cinfo;
	266	cdesc->id = i;
	267
	268	/* Get configuration for the ATL instances */
	269	snprintf(prop, sizeof(prop), "atl%u", i);
33ec6dbc	270	cfg_node = of_get_child_by_name(node, prop);
9ac33b0c PU	271	if (cfg_node) {
	272	ret = of_property_read_u32(cfg_node, "bws",
	273	&cdesc->bws);
	274	ret \|= of_property_read_u32(cfg_node, "aws",
	275	&cdesc->aws);
	276	if (!ret) {
	277	cdesc->valid = true;
	278	atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
	279	cdesc->bws);
	280	atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
	281	cdesc->aws);
	282	}
660e1551	283	of_node_put(cfg_node);
9ac33b0c PU	284	}
	285
	286	cdesc->probed = true;
	287	/*
	288	* Enable the clock if it has been asked prior to loading the
	289	* hw driver
	290	*/
	291	if (cdesc->enabled)
	292	atl_clk_enable(__clk_get_hw(clk));
	293	}
	294	pm_runtime_put_sync(cinfo->dev);
	295
	296	return ret;
	297	}
	298
f375573c	299	static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
9ac33b0c PU	300	{ .compatible = "ti,dra7-atl", },
	301	{},
	302	};
9ac33b0c PU	303
	304	static struct platform_driver dra7_atl_clk_driver = {
	305	.driver = {
	306	.name = "dra7-atl",
172ff5a2	307	.suppress_bind_attrs = true,
9ac33b0c PU	308	.of_match_table = of_dra7_atl_clk_match_tbl,
	309	},
	310	.probe = of_dra7_atl_clk_probe,
9ac33b0c	311	};
172ff5a2	312	builtin_platform_driver(dra7_atl_clk_driver);