[mirror_ubuntu-jammy-kernel.git] / drivers / clk / ti / clkt_dpll.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP2/3/4 DPLL clock functions
 *
 * Copyright (C) 2005-2008 Texas Instruments, Inc.
 * Copyright (C) 2004-2010 Nokia Corporation
 *
 * Contacts:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/clk/ti.h>

#include <asm/div64.h>

#include "clock.h"

/* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER		2
#define DPLL_MIN_DIVIDER		1

/* Possible error results from _dpll_test_mult */
#define DPLL_MULT_UNDERFLOW		-1

/*
 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
 * The higher the scale factor, the greater the risk of arithmetic overflow,
 * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
 * must be a power of DPLL_SCALE_BASE.
 */
#define DPLL_SCALE_FACTOR		64
#define DPLL_SCALE_BASE			2
#define DPLL_ROUNDING_VAL		((DPLL_SCALE_BASE / 2) * \
					 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))

/*
 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
 * From device data manual section 4.3 "DPLL and DLL Specifications".
 */
#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN	500000
#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX	2500000

/* _dpll_test_fint() return codes */
#define DPLL_FINT_UNDERFLOW		-1
#define DPLL_FINT_INVALID		-2

/* Private functions */

/*
 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
 * @clk: DPLL struct clk to test
 * @n: divider value (N) to test
 *
 * Tests whether a particular divider @n will result in a valid DPLL
 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
 * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
 * (assuming that it is counting N upwards), or -2 if the enclosing loop
 * should skip to the next iteration (again assuming N is increasing).
 */
static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
{
	struct dpll_data *dd;
	long fint, fint_min, fint_max;
	int ret = 0;

	dd = clk->dpll_data;

	/* DPLL divider must result in a valid jitter correction val */
	fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;

	if (dd->flags & DPLL_J_TYPE) {
		fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
		fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
	} else {
		fint_min = ti_clk_get_features()->fint_min;
		fint_max = ti_clk_get_features()->fint_max;
	}

	if (!fint_min || !fint_max) {
		WARN(1, "No fint limits available!\n");
		return DPLL_FINT_INVALID;
	}

	if (fint < ti_clk_get_features()->fint_min) {
		pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
			 n);
		dd->max_divider = n;
		ret = DPLL_FINT_UNDERFLOW;
	} else if (fint > ti_clk_get_features()->fint_max) {
		pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
			 n);
		dd->min_divider = n;
		ret = DPLL_FINT_INVALID;
	} else if (fint > ti_clk_get_features()->fint_band1_max &&
		   fint < ti_clk_get_features()->fint_band2_min) {
		pr_debug("rejecting n=%d due to Fint failure\n", n);
		ret = DPLL_FINT_INVALID;
	}

	return ret;
}

static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
					    unsigned int m, unsigned int n)
{
	unsigned long long num;

	num = (unsigned long long)parent_rate * m;
	do_div(num, n);
	return num;
}

/*
 * _dpll_test_mult - test a DPLL multiplier value
 * @m: pointer to the DPLL m (multiplier) value under test
 * @n: current DPLL n (divider) value under test
 * @new_rate: pointer to storage for the resulting rounded rate
 * @target_rate: the desired DPLL rate
 * @parent_rate: the DPLL's parent clock rate
 *
 * This code tests a DPLL multiplier value, ensuring that the
 * resulting rate will not be higher than the target_rate, and that
 * the multiplier value itself is valid for the DPLL.  Initially, the
 * integer pointed to by the m argument should be prescaled by
 * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
 * a non-scaled m upon return.  This non-scaled m will result in a
 * new_rate as close as possible to target_rate (but not greater than
 * target_rate) given the current (parent_rate, n, prescaled m)
 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
 * non-scaled m attempted to underflow, which can allow the calling
 * function to bail out early; or 0 upon success.
 */
static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
			   unsigned long target_rate,
			   unsigned long parent_rate)
{
	int r = 0, carry = 0;

	/* Unscale m and round if necessary */
	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
		carry = 1;
	*m = (*m / DPLL_SCALE_FACTOR) + carry;

	/*
	 * The new rate must be <= the target rate to avoid programming
	 * a rate that is impossible for the hardware to handle
	 */
	*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
	if (*new_rate > target_rate) {
		(*m)--;
		*new_rate = 0;
	}

	/* Guard against m underflow */
	if (*m < DPLL_MIN_MULTIPLIER) {
		*m = DPLL_MIN_MULTIPLIER;
		*new_rate = 0;
		r = DPLL_MULT_UNDERFLOW;
	}

	if (*new_rate == 0)
		*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);

	return r;
}

/**
 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
 * @v: bitfield value of the DPLL enable
 *
 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
 */
static int _omap2_dpll_is_in_bypass(u32 v)
{
	u8 mask, val;

	mask = ti_clk_get_features()->dpll_bypass_vals;

	/*
	 * Each set bit in the mask corresponds to a bypass value equal
	 * to the bitshift. Go through each set-bit in the mask and
	 * compare against the given register value.
	 */
	while (mask) {
		val = __ffs(mask);
		mask ^= (1 << val);
		if (v == val)
			return 1;
	}

	return 0;
}

/* Public functions */
u8 omap2_init_dpll_parent(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	u32 v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return -EINVAL;

	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	/* Reparent the struct clk in case the dpll is in bypass */
	if (_omap2_dpll_is_in_bypass(v))
		return 1;

	return 0;
}

/**
 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
 * @clk: struct clk * of a DPLL
 *
 * DPLLs can be locked or bypassed - basically, enabled or disabled.
 * When locked, the DPLL output depends on the M and N values.  When
 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
 * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
 * if the clock @clk is not a DPLL.
 */
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
{
	u64 dpll_clk;
	u32 dpll_mult, dpll_div, v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return 0;

	/* Return bypass rate if DPLL is bypassed */
	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	if (_omap2_dpll_is_in_bypass(v))
		return clk_hw_get_rate(dd->clk_bypass);

	v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
	dpll_mult = v & dd->mult_mask;
	dpll_mult >>= __ffs(dd->mult_mask);
	dpll_div = v & dd->div1_mask;
	dpll_div >>= __ffs(dd->div1_mask);

	dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
	do_div(dpll_clk, dpll_div + 1);

	return dpll_clk;
}

/* DPLL rate rounding code */

/**
 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
 * @clk: struct clk * for a DPLL
 * @target_rate: desired DPLL clock rate
 *
 * Given a DPLL and a desired target rate, round the target rate to a
 * possible, programmable rate for this DPLL.  Attempts to select the
 * minimum possible n.  Stores the computed (m, n) in the DPLL's
 * dpll_data structure so set_rate() will not need to call this
 * (expensive) function again.  Returns ~0 if the target rate cannot
 * be rounded, or the rounded rate upon success.
 */
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
			   unsigned long *parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	int m, n, r, scaled_max_m;
	int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
	unsigned long scaled_rt_rp;
	unsigned long new_rate = 0;
	struct dpll_data *dd;
	unsigned long ref_rate;
	long delta;
	long prev_min_delta = LONG_MAX;
	const char *clk_name;

	if (!clk || !clk->dpll_data)
		return ~0;

	dd = clk->dpll_data;

	if (dd->max_rate && target_rate > dd->max_rate)
		target_rate = dd->max_rate;

	ref_rate = clk_hw_get_rate(dd->clk_ref);
	clk_name = clk_hw_get_name(hw);
	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
		 clk_name, target_rate);

	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;

	dd->last_rounded_rate = 0;

	for (n = dd->min_divider; n <= dd->max_divider; n++) {
		/* Is the (input clk, divider) pair valid for the DPLL? */
		r = _dpll_test_fint(clk, n);
		if (r == DPLL_FINT_UNDERFLOW)
			break;
		else if (r == DPLL_FINT_INVALID)
			continue;

		/* Compute the scaled DPLL multiplier, based on the divider */
		m = scaled_rt_rp * n;

		/*
		 * Since we're counting n up, a m overflow means we
		 * can bail out completely (since as n increases in
		 * the next iteration, there's no way that m can
		 * increase beyond the current m)
		 */
		if (m > scaled_max_m)
			break;

		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
				    ref_rate);

		/* m can't be set low enough for this n - try with a larger n */
		if (r == DPLL_MULT_UNDERFLOW)
			continue;

		/* skip rates above our target rate */
		delta = target_rate - new_rate;
		if (delta < 0)
			continue;

		if (delta < prev_min_delta) {
			prev_min_delta = delta;
			min_delta_m = m;
			min_delta_n = n;
		}

		pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
			 clk_name, m, n, new_rate);

		if (delta == 0)
			break;
	}

	if (prev_min_delta == LONG_MAX) {
		pr_debug("clock: %s: cannot round to rate %lu\n",
			 clk_name, target_rate);
		return ~0;
	}

	dd->last_rounded_m = min_delta_m;
	dd->last_rounded_n = min_delta_n;
	dd->last_rounded_rate = target_rate - prev_min_delta;

	return dd->last_rounded_rate;
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
0b96af68 PW	2	/*
	3	* OMAP2/3/4 DPLL clock functions
	4	*
	5	* Copyright (C) 2005-2008 Texas Instruments, Inc.
	6	* Copyright (C) 2004-2010 Nokia Corporation
	7	*
	8	* Contacts:
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Paul Walmsley
0b96af68 PW	11	*/
	12	#undef DEBUG
	13
	14	#include <linux/kernel.h>
	15	#include <linux/errno.h>
a53ad8ef	16	#include <linux/clk.h>
32cc0021	17	#include <linux/clk-provider.h>
0b96af68	18	#include <linux/io.h>
b138b028	19	#include <linux/clk/ti.h>
0b96af68 PW	20
	21	#include <asm/div64.h>
	22
0b96af68	23	#include "clock.h"
0b96af68 PW	24
0b96af68 PW	25	/* DPLL rate rounding: minimum DPLL multiplier, divider values */
93340a22	26	#define DPLL_MIN_MULTIPLIER 2
0b96af68 PW	27	#define DPLL_MIN_DIVIDER 1
	28
	29	/* Possible error results from _dpll_test_mult */
	30	#define DPLL_MULT_UNDERFLOW -1
	31
	32	/*
	33	* Scale factor to mitigate roundoff errors in DPLL rate rounding.
	34	* The higher the scale factor, the greater the risk of arithmetic overflow,
	35	* but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
	36	* must be a power of DPLL_SCALE_BASE.
	37	*/
	38	#define DPLL_SCALE_FACTOR 64
	39	#define DPLL_SCALE_BASE 2
	40	#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
	41	(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
	42
1194d7b8 JH	43	/*
	44	* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
	45	* From device data manual section 4.3 "DPLL and DLL Specifications".
	46	*/
	47	#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
	48	#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
0b96af68 PW	49
	50	/* _dpll_test_fint() return codes */
	51	#define DPLL_FINT_UNDERFLOW -1
	52	#define DPLL_FINT_INVALID -2
	53
	54	/* Private functions */
	55
	56	/*
	57	* _dpll_test_fint - test whether an Fint value is valid for the DPLL
	58	* @clk: DPLL struct clk to test
	59	* @n: divider value (N) to test
	60	*
	61	* Tests whether a particular divider @n will result in a valid DPLL
	62	* internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
	63	* Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
	64	* (assuming that it is counting N upwards), or -2 if the enclosing loop
	65	* should skip to the next iteration (again assuming N is increasing).
	66	*/
6340c872	67	static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
0b96af68 PW	68	{
0b96af68 PW	69	struct dpll_data *dd;
1194d7b8	70	long fint, fint_min, fint_max;
0b96af68 PW	71	int ret = 0;
	72
	73	dd = clk->dpll_data;
	74
	75	/* DPLL divider must result in a valid jitter correction val */
a53ad8ef	76	fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
0b96af68	77
a24886e2	78	if (dd->flags & DPLL_J_TYPE) {
1194d7b8 JH	79	fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
	80	fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
	81	} else {
f3b19aa5 TK	82	fint_min = ti_clk_get_features()->fint_min;
f3b19aa5 TK	83	fint_max = ti_clk_get_features()->fint_max;
1194d7b8 JH	84	}
1194d7b8 JH	85
a24886e2 TK	86	if (!fint_min \|\| !fint_max) {
	87	WARN(1, "No fint limits available!\n");
	88	return DPLL_FINT_INVALID;
1194d7b8 JH	89	}
1194d7b8 JH	90
f3b19aa5	91	if (fint < ti_clk_get_features()->fint_min) {
7852ec05 PW	92	pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
7852ec05 PW	93	n);
0b96af68 PW	94	dd->max_divider = n;
0b96af68 PW	95	ret = DPLL_FINT_UNDERFLOW;
f3b19aa5	96	} else if (fint > ti_clk_get_features()->fint_max) {
7852ec05 PW	97	pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
7852ec05 PW	98	n);
0b96af68 PW	99	dd->min_divider = n;
0b96af68 PW	100	ret = DPLL_FINT_INVALID;
f3b19aa5 TK	101	} else if (fint > ti_clk_get_features()->fint_band1_max &&
f3b19aa5 TK	102	fint < ti_clk_get_features()->fint_band2_min) {
1194d7b8 JH	103	pr_debug("rejecting n=%d due to Fint failure\n", n);
1194d7b8 JH	104	ret = DPLL_FINT_INVALID;
0b96af68 PW	105	}
	106
	107	return ret;
	108	}
	109
	110	static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
	111	unsigned int m, unsigned int n)
	112	{
	113	unsigned long long num;
	114
	115	num = (unsigned long long)parent_rate * m;
	116	do_div(num, n);
	117	return num;
	118	}
	119
	120	/*
	121	* _dpll_test_mult - test a DPLL multiplier value
	122	* @m: pointer to the DPLL m (multiplier) value under test
	123	* @n: current DPLL n (divider) value under test
	124	* @new_rate: pointer to storage for the resulting rounded rate
	125	* @target_rate: the desired DPLL rate
	126	* @parent_rate: the DPLL's parent clock rate
	127	*
	128	* This code tests a DPLL multiplier value, ensuring that the
	129	* resulting rate will not be higher than the target_rate, and that
	130	* the multiplier value itself is valid for the DPLL. Initially, the
	131	* integer pointed to by the m argument should be prescaled by
	132	* multiplying by DPLL_SCALE_FACTOR. The code will replace this with
	133	* a non-scaled m upon return. This non-scaled m will result in a
	134	* new_rate as close as possible to target_rate (but not greater than
	135	* target_rate) given the current (parent_rate, n, prescaled m)
	136	* triple. Returns DPLL_MULT_UNDERFLOW in the event that the
	137	* non-scaled m attempted to underflow, which can allow the calling
	138	* function to bail out early; or 0 upon success.
	139	*/
	140	static int _dpll_test_mult(int m, int n, unsigned long new_rate,
	141	unsigned long target_rate,
	142	unsigned long parent_rate)
	143	{
	144	int r = 0, carry = 0;
	145
	146	/* Unscale m and round if necessary */
	147	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
	148	carry = 1;
	149	m = (m / DPLL_SCALE_FACTOR) + carry;
	150
	151	/*
	152	* The new rate must be <= the target rate to avoid programming
	153	* a rate that is impossible for the hardware to handle
	154	*/
	155	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
	156	if (*new_rate > target_rate) {
	157	(*m)--;
	158	*new_rate = 0;
	159	}
	160
	161	/* Guard against m underflow */
	162	if (*m < DPLL_MIN_MULTIPLIER) {
	163	*m = DPLL_MIN_MULTIPLIER;
	164	*new_rate = 0;
	165	r = DPLL_MULT_UNDERFLOW;
	166	}
	167
	168	if (*new_rate == 0)
169	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
170
171	return r;
172	}
173
5f84aeb6 TK	174	/**
	175	* _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
	176	* @v: bitfield value of the DPLL enable
	177	*
	178	* Checks given DPLL enable bitfield to see whether the DPLL is in bypass
	179	* mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
	180	*/
	181	static int _omap2_dpll_is_in_bypass(u32 v)
	182	{
512d91cb TK	183	u8 mask, val;
512d91cb TK	184
f3b19aa5	185	mask = ti_clk_get_features()->dpll_bypass_vals;
512d91cb TK	186
	187	/*
	188	* Each set bit in the mask corresponds to a bypass value equal
	189	* to the bitshift. Go through each set-bit in the mask and
	190	* compare against the given register value.
	191	*/
	192	while (mask) {
	193	val = __ffs(mask);
	194	mask ^= (1 << val);
	195	if (v == val)
5f84aeb6 TK	196	return 1;
	197	}
	198
	199	return 0;
	200	}
	201
0b96af68	202	/* Public functions */
32cc0021 MT	203	u8 omap2_init_dpll_parent(struct clk_hw *hw)
	204	{
	205	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
0b96af68 PW	206	u32 v;
	207	struct dpll_data *dd;
	208
	209	dd = clk->dpll_data;
	210	if (!dd)
32cc0021	211	return -EINVAL;
0b96af68	212
6c0afb50	213	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
0b96af68 PW	214	v &= dd->enable_mask;
	215	v >>= __ffs(dd->enable_mask);
	216
241d3a8d	217	/* Reparent the struct clk in case the dpll is in bypass */
5f84aeb6 TK	218	if (_omap2_dpll_is_in_bypass(v))
	219	return 1;
	220
32cc0021	221	return 0;
0b96af68 PW	222	}
	223
	224	/**
	225	* omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
	226	* @clk: struct clk * of a DPLL
	227	*
	228	* DPLLs can be locked or bypassed - basically, enabled or disabled.
	229	* When locked, the DPLL output depends on the M and N values. When
	230	* bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
	231	* or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
	232	* 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
	233	* (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
	234	* Returns the current DPLL CLKOUT rate (not CLKOUTX2) if the DPLL is
	235	* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
	236	* if the clock @clk is not a DPLL.
	237	*/
32cc0021	238	unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
0b96af68	239	{
df976f5d	240	u64 dpll_clk;
0b96af68 PW	241	u32 dpll_mult, dpll_div, v;
	242	struct dpll_data *dd;
	243
	244	dd = clk->dpll_data;
	245	if (!dd)
	246	return 0;
	247
	248	/* Return bypass rate if DPLL is bypassed */
6c0afb50	249	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
0b96af68 PW	250	v &= dd->enable_mask;
	251	v >>= __ffs(dd->enable_mask);
	252
5f84aeb6	253	if (_omap2_dpll_is_in_bypass(v))
b6f51284	254	return clk_hw_get_rate(dd->clk_bypass);
0b96af68	255
6c0afb50	256	v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
0b96af68 PW	257	dpll_mult = v & dd->mult_mask;
	258	dpll_mult >>= __ffs(dd->mult_mask);
	259	dpll_div = v & dd->div1_mask;
	260	dpll_div >>= __ffs(dd->div1_mask);
	261
b6f51284	262	dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
0b96af68 PW	263	do_div(dpll_clk, dpll_div + 1);
	264
	265	return dpll_clk;
	266	}
	267
	268	/* DPLL rate rounding code */
	269
0b96af68 PW	270	/**
	271	* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
	272	* @clk: struct clk * for a DPLL
	273	* @target_rate: desired DPLL clock rate
	274	*
241d3a8d PW	275	* Given a DPLL and a desired target rate, round the target rate to a
	276	* possible, programmable rate for this DPLL. Attempts to select the
	277	* minimum possible n. Stores the computed (m, n) in the DPLL's
	278	* dpll_data structure so set_rate() will not need to call this
	279	* (expensive) function again. Returns ~0 if the target rate cannot
	280	* be rounded, or the rounded rate upon success.
0b96af68	281	*/
32cc0021	282	long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
b138b028	283	unsigned long *parent_rate)
32cc0021 MT	284	{
32cc0021 MT	285	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
241d3a8d	286	int m, n, r, scaled_max_m;
0a263444	287	int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
241d3a8d PW	288	unsigned long scaled_rt_rp;
241d3a8d PW	289	unsigned long new_rate = 0;
0b96af68	290	struct dpll_data *dd;
5dcc3b97	291	unsigned long ref_rate;
0a263444 PW	292	long delta;
0a263444 PW	293	long prev_min_delta = LONG_MAX;
5dcc3b97	294	const char *clk_name;
0b96af68 PW	295
	296	if (!clk \|\| !clk->dpll_data)
	297	return ~0;
	298
	299	dd = clk->dpll_data;
	300
c5cc2a0b TK	301	if (dd->max_rate && target_rate > dd->max_rate)
	302	target_rate = dd->max_rate;
	303
b6f51284	304	ref_rate = clk_hw_get_rate(dd->clk_ref);
a53ad8ef	305	clk_name = clk_hw_get_name(hw);
0cc1d944	306	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
5dcc3b97	307	clk_name, target_rate);
0b96af68	308
5dcc3b97	309	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
0b96af68 PW	310	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
	311
	312	dd->last_rounded_rate = 0;
	313
	314	for (n = dd->min_divider; n <= dd->max_divider; n++) {
0b96af68 PW	315	/* Is the (input clk, divider) pair valid for the DPLL? */
	316	r = _dpll_test_fint(clk, n);
	317	if (r == DPLL_FINT_UNDERFLOW)
	318	break;
	319	else if (r == DPLL_FINT_INVALID)
	320	continue;
	321
	322	/* Compute the scaled DPLL multiplier, based on the divider */
	323	m = scaled_rt_rp * n;
	324
	325	/*
	326	* Since we're counting n up, a m overflow means we
	327	* can bail out completely (since as n increases in
	328	* the next iteration, there's no way that m can
	329	* increase beyond the current m)
	330	*/
	331	if (m > scaled_max_m)
	332	break;
	333
	334	r = _dpll_test_mult(&m, n, &new_rate, target_rate,
5dcc3b97	335	ref_rate);
0b96af68 PW	336
	337	/* m can't be set low enough for this n - try with a larger n */
	338	if (r == DPLL_MULT_UNDERFLOW)
	339	continue;
	340
0a263444 PW	341	/* skip rates above our target rate */
	342	delta = target_rate - new_rate;
	343	if (delta < 0)
	344	continue;
	345
	346	if (delta < prev_min_delta) {
	347	prev_min_delta = delta;
	348	min_delta_m = m;
	349	min_delta_n = n;
	350	}
	351
0cc1d944	352	pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
5dcc3b97	353	clk_name, m, n, new_rate);
0b96af68	354
0a263444	355	if (delta == 0)
241d3a8d	356	break;
0b96af68 PW	357	}
0b96af68 PW	358
0a263444	359	if (prev_min_delta == LONG_MAX) {
0cc1d944	360	pr_debug("clock: %s: cannot round to rate %lu\n",
5dcc3b97	361	clk_name, target_rate);
0b96af68 PW	362	return ~0;
	363	}
	364
0a263444 PW	365	dd->last_rounded_m = min_delta_m;
	366	dd->last_rounded_n = min_delta_n;
	367	dd->last_rounded_rate = target_rate - prev_min_delta;
	368
	369	return dd->last_rounded_rate;
0b96af68	370	}