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c82f8957 TK |
1 | /* |
2 | * TI Clock driver internal definitions | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments, Inc | |
5 | * Tero Kristo (t-kristo@ti.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | #ifndef __DRIVERS_CLK_TI_CLOCK__ | |
17 | #define __DRIVERS_CLK_TI_CLOCK__ | |
18 | ||
6dbde947 TK |
19 | struct clk_omap_divider { |
20 | struct clk_hw hw; | |
6c0afb50 | 21 | struct clk_omap_reg reg; |
6dbde947 TK |
22 | u8 shift; |
23 | u8 width; | |
24 | u8 flags; | |
25 | const struct clk_div_table *table; | |
26 | }; | |
27 | ||
28 | #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) | |
29 | ||
d83bc5b6 TK |
30 | struct clk_omap_mux { |
31 | struct clk_hw hw; | |
6c0afb50 | 32 | struct clk_omap_reg reg; |
d83bc5b6 TK |
33 | u32 *table; |
34 | u32 mask; | |
35 | u8 shift; | |
36 | u8 flags; | |
37 | }; | |
38 | ||
39 | #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) | |
40 | ||
c82f8957 TK |
41 | enum { |
42 | TI_CLK_FIXED, | |
43 | TI_CLK_MUX, | |
44 | TI_CLK_DIVIDER, | |
45 | TI_CLK_COMPOSITE, | |
46 | TI_CLK_FIXED_FACTOR, | |
47 | TI_CLK_GATE, | |
48 | TI_CLK_DPLL, | |
49 | }; | |
50 | ||
51 | /* Global flags */ | |
52 | #define CLKF_INDEX_POWER_OF_TWO (1 << 0) | |
53 | #define CLKF_INDEX_STARTS_AT_ONE (1 << 1) | |
54 | #define CLKF_SET_RATE_PARENT (1 << 2) | |
55 | #define CLKF_OMAP3 (1 << 3) | |
56 | #define CLKF_AM35XX (1 << 4) | |
57 | ||
58 | /* Gate flags */ | |
59 | #define CLKF_SET_BIT_TO_DISABLE (1 << 5) | |
60 | #define CLKF_INTERFACE (1 << 6) | |
61 | #define CLKF_SSI (1 << 7) | |
62 | #define CLKF_DSS (1 << 8) | |
63 | #define CLKF_HSOTGUSB (1 << 9) | |
64 | #define CLKF_WAIT (1 << 10) | |
65 | #define CLKF_NO_WAIT (1 << 11) | |
66 | #define CLKF_HSDIV (1 << 12) | |
67 | #define CLKF_CLKDM (1 << 13) | |
68 | ||
69 | /* DPLL flags */ | |
70 | #define CLKF_LOW_POWER_STOP (1 << 5) | |
71 | #define CLKF_LOCK (1 << 6) | |
72 | #define CLKF_LOW_POWER_BYPASS (1 << 7) | |
73 | #define CLKF_PER (1 << 8) | |
74 | #define CLKF_CORE (1 << 9) | |
75 | #define CLKF_J_TYPE (1 << 10) | |
76 | ||
77 | #define CLK(dev, con, ck) \ | |
78 | { \ | |
79 | .lk = { \ | |
80 | .dev_id = dev, \ | |
81 | .con_id = con, \ | |
82 | }, \ | |
83 | .clk = ck, \ | |
84 | } | |
85 | ||
86 | struct ti_clk { | |
87 | const char *name; | |
88 | const char *clkdm_name; | |
89 | int type; | |
90 | void *data; | |
91 | struct ti_clk *patch; | |
92 | struct clk *clk; | |
93 | }; | |
94 | ||
95 | struct ti_clk_alias { | |
96 | struct ti_clk *clk; | |
97 | struct clk_lookup lk; | |
98 | struct list_head link; | |
99 | }; | |
100 | ||
101 | struct ti_clk_fixed { | |
102 | u32 frequency; | |
103 | u16 flags; | |
104 | }; | |
105 | ||
106 | struct ti_clk_mux { | |
107 | u8 bit_shift; | |
108 | int num_parents; | |
109 | u16 reg; | |
110 | u8 module; | |
ce382d47 | 111 | const char * const *parents; |
c82f8957 TK |
112 | u16 flags; |
113 | }; | |
114 | ||
115 | struct ti_clk_divider { | |
116 | const char *parent; | |
117 | u8 bit_shift; | |
118 | u16 max_div; | |
119 | u16 reg; | |
120 | u8 module; | |
121 | int *dividers; | |
122 | int num_dividers; | |
123 | u16 flags; | |
124 | }; | |
125 | ||
126 | struct ti_clk_fixed_factor { | |
127 | const char *parent; | |
128 | u16 div; | |
129 | u16 mult; | |
130 | u16 flags; | |
131 | }; | |
132 | ||
133 | struct ti_clk_gate { | |
134 | const char *parent; | |
135 | u8 bit_shift; | |
136 | u16 reg; | |
137 | u8 module; | |
138 | u16 flags; | |
139 | }; | |
140 | ||
141 | struct ti_clk_composite { | |
142 | struct ti_clk_divider *divider; | |
143 | struct ti_clk_mux *mux; | |
144 | struct ti_clk_gate *gate; | |
145 | u16 flags; | |
146 | }; | |
147 | ||
148 | struct ti_clk_clkdm_gate { | |
149 | const char *parent; | |
150 | u16 flags; | |
151 | }; | |
152 | ||
153 | struct ti_clk_dpll { | |
154 | int num_parents; | |
155 | u16 control_reg; | |
156 | u16 idlest_reg; | |
157 | u16 autoidle_reg; | |
158 | u16 mult_div1_reg; | |
159 | u8 module; | |
160 | const char **parents; | |
161 | u16 flags; | |
162 | u8 modes; | |
163 | u32 mult_mask; | |
164 | u32 div1_mask; | |
165 | u32 enable_mask; | |
166 | u32 autoidle_mask; | |
167 | u32 freqsel_mask; | |
168 | u32 idlest_mask; | |
169 | u32 dco_mask; | |
170 | u32 sddiv_mask; | |
171 | u16 max_multiplier; | |
172 | u16 max_divider; | |
ed405a23 | 173 | u8 min_divider; |
c82f8957 TK |
174 | u8 auto_recal_bit; |
175 | u8 recal_en_bit; | |
176 | u8 recal_st_bit; | |
177 | }; | |
178 | ||
a3314e9c TK |
179 | /* Composite clock component types */ |
180 | enum { | |
181 | CLK_COMPONENT_TYPE_GATE = 0, | |
182 | CLK_COMPONENT_TYPE_DIVIDER, | |
183 | CLK_COMPONENT_TYPE_MUX, | |
184 | CLK_COMPONENT_TYPE_MAX, | |
185 | }; | |
186 | ||
187 | /** | |
188 | * struct ti_dt_clk - OMAP DT clock alias declarations | |
189 | * @lk: clock lookup definition | |
190 | * @node_name: clock DT node to map to | |
191 | */ | |
192 | struct ti_dt_clk { | |
193 | struct clk_lookup lk; | |
194 | char *node_name; | |
195 | }; | |
196 | ||
197 | #define DT_CLK(dev, con, name) \ | |
198 | { \ | |
199 | .lk = { \ | |
200 | .dev_id = dev, \ | |
201 | .con_id = con, \ | |
202 | }, \ | |
203 | .node_name = name, \ | |
204 | } | |
205 | ||
88a17252 TK |
206 | /* CLKCTRL type definitions */ |
207 | struct omap_clkctrl_div_data { | |
208 | const int *dividers; | |
209 | int max_div; | |
210 | }; | |
211 | ||
212 | struct omap_clkctrl_bit_data { | |
213 | u8 bit; | |
214 | u8 type; | |
215 | const char * const *parents; | |
216 | const void *data; | |
217 | }; | |
218 | ||
219 | struct omap_clkctrl_reg_data { | |
220 | u16 offset; | |
221 | const struct omap_clkctrl_bit_data *bit_data; | |
222 | u16 flags; | |
223 | const char *parent; | |
224 | }; | |
225 | ||
226 | struct omap_clkctrl_data { | |
227 | u32 addr; | |
228 | const struct omap_clkctrl_reg_data *regs; | |
229 | }; | |
230 | ||
1c881b5a TK |
231 | extern const struct omap_clkctrl_data omap4_clkctrl_data[]; |
232 | ||
88a17252 TK |
233 | #define CLKF_SW_SUP BIT(0) |
234 | #define CLKF_HW_SUP BIT(1) | |
235 | #define CLKF_NO_IDLEST BIT(2) | |
236 | ||
a3314e9c TK |
237 | typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); |
238 | ||
f187616b | 239 | struct clk *ti_clk_register_gate(struct ti_clk *setup); |
06524fa4 | 240 | struct clk *ti_clk_register_interface(struct ti_clk *setup); |
7c18a65c | 241 | struct clk *ti_clk_register_mux(struct ti_clk *setup); |
d96f774b | 242 | struct clk *ti_clk_register_divider(struct ti_clk *setup); |
b26bcf9b | 243 | struct clk *ti_clk_register_composite(struct ti_clk *setup); |
ed405a23 | 244 | struct clk *ti_clk_register_dpll(struct ti_clk *setup); |
21f0bf2d TK |
245 | struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, |
246 | const char *con); | |
247 | int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); | |
c17435c5 | 248 | void ti_clk_add_aliases(void); |
7c18a65c | 249 | |
d96f774b | 250 | struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup); |
f187616b | 251 | struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup); |
7c18a65c TK |
252 | struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); |
253 | ||
4f6be565 TK |
254 | int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, |
255 | u8 flags, u8 *width, | |
256 | const struct clk_div_table **table); | |
257 | ||
c82f8957 TK |
258 | void ti_clk_patch_legacy_clks(struct ti_clk **patch); |
259 | struct clk *ti_clk_register_clk(struct ti_clk *setup); | |
260 | int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); | |
261 | ||
6c0afb50 TK |
262 | int ti_clk_get_reg_addr(struct device_node *node, int index, |
263 | struct clk_omap_reg *reg); | |
a3314e9c TK |
264 | void ti_dt_clocks_register(struct ti_dt_clk *oclks); |
265 | int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, | |
266 | ti_of_clk_init_cb_t func); | |
267 | int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); | |
268 | ||
a53ad8ef | 269 | void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw); |
bf22bae7 | 270 | int of_ti_clk_autoidle_setup(struct device_node *node); |
a5aa8a60 | 271 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); |
bf22bae7 | 272 | |
0565fb16 | 273 | extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; |
59245ce0 | 274 | extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; |
9f37e90e | 275 | extern const struct clk_hw_omap_ops clkhwops_wait; |
ef14db09 TK |
276 | extern const struct clk_hw_omap_ops clkhwops_iclk; |
277 | extern const struct clk_hw_omap_ops clkhwops_iclk_wait; | |
d5a04ddd | 278 | extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; |
f2671d5c TK |
279 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; |
280 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; | |
281 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; | |
282 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; | |
c9a58b0a TK |
283 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; |
284 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; | |
59245ce0 | 285 | |
a3314e9c TK |
286 | extern const struct clk_ops ti_clk_divider_ops; |
287 | extern const struct clk_ops ti_clk_mux_ops; | |
9a00fa68 | 288 | extern const struct clk_ops omap_gate_clk_ops; |
a3314e9c | 289 | |
2e1a294c | 290 | void omap2_init_clk_clkdm(struct clk_hw *hw); |
bd86cfdc TK |
291 | int omap2_clkops_enable_clkdm(struct clk_hw *hw); |
292 | void omap2_clkops_disable_clkdm(struct clk_hw *hw); | |
293 | ||
9f37e90e TK |
294 | int omap2_dflt_clk_enable(struct clk_hw *hw); |
295 | void omap2_dflt_clk_disable(struct clk_hw *hw); | |
296 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw); | |
a3314e9c | 297 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
6c0afb50 | 298 | struct clk_omap_reg *other_reg, |
a3314e9c TK |
299 | u8 *other_bit); |
300 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, | |
6c0afb50 | 301 | struct clk_omap_reg *idlest_reg, |
a3314e9c TK |
302 | u8 *idlest_bit, u8 *idlest_val); |
303 | ||
304 | void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); | |
305 | void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); | |
9f37e90e | 306 | |
b138b028 | 307 | u8 omap2_init_dpll_parent(struct clk_hw *hw); |
0565fb16 TK |
308 | int omap3_noncore_dpll_enable(struct clk_hw *hw); |
309 | void omap3_noncore_dpll_disable(struct clk_hw *hw); | |
310 | int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); | |
311 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, | |
312 | unsigned long parent_rate); | |
313 | int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, | |
314 | unsigned long rate, | |
315 | unsigned long parent_rate, | |
316 | u8 index); | |
4d341056 SB |
317 | int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, |
318 | struct clk_rate_request *req); | |
0565fb16 TK |
319 | long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, |
320 | unsigned long *parent_rate); | |
321 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, | |
322 | unsigned long parent_rate); | |
323 | ||
035cd485 RW |
324 | /* |
325 | * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks | |
326 | * that are sourced by DPLL5, and both of these require this clock | |
327 | * to be at 120 MHz for proper operation. | |
328 | */ | |
329 | #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000 | |
330 | ||
0565fb16 TK |
331 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); |
332 | int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, | |
333 | unsigned long parent_rate); | |
334 | int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, | |
335 | unsigned long parent_rate, u8 index); | |
035cd485 RW |
336 | int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate, |
337 | unsigned long parent_rate); | |
0565fb16 | 338 | void omap3_clk_lock_dpll5(void); |
b138b028 | 339 | |
59245ce0 TK |
340 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
341 | unsigned long parent_rate); | |
342 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, | |
343 | unsigned long target_rate, | |
344 | unsigned long *parent_rate); | |
4d341056 SB |
345 | int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, |
346 | struct clk_rate_request *req); | |
59245ce0 | 347 | |
e9e63088 TK |
348 | extern struct ti_clk_ll_ops *ti_clk_ll_ops; |
349 | ||
c82f8957 | 350 | #endif |