[mirror_ubuntu-artful-kernel.git] / drivers / clk / ti / clock.h

/*
 * TI Clock driver internal definitions
 *
 * Copyright (C) 2014 Texas Instruments, Inc
 *     Tero Kristo (t-kristo@ti.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */
#ifndef __DRIVERS_CLK_TI_CLOCK__
#define __DRIVERS_CLK_TI_CLOCK__

struct clk_omap_divider {
	struct clk_hw		hw;
	struct clk_omap_reg	reg;
	u8			shift;
	u8			width;
	u8			flags;
	const struct clk_div_table	*table;
};

#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)

struct clk_omap_mux {
	struct clk_hw		hw;
	struct clk_omap_reg	reg;
	u32			*table;
	u32			mask;
	u8			shift;
	u8			flags;
};

#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)

enum {
	TI_CLK_FIXED,
	TI_CLK_MUX,
	TI_CLK_DIVIDER,
	TI_CLK_COMPOSITE,
	TI_CLK_FIXED_FACTOR,
	TI_CLK_GATE,
	TI_CLK_DPLL,
};

/* Global flags */
#define CLKF_INDEX_POWER_OF_TWO		(1 << 0)
#define CLKF_INDEX_STARTS_AT_ONE	(1 << 1)
#define CLKF_SET_RATE_PARENT		(1 << 2)
#define CLKF_OMAP3			(1 << 3)
#define CLKF_AM35XX			(1 << 4)

/* Gate flags */
#define CLKF_SET_BIT_TO_DISABLE		(1 << 5)
#define CLKF_INTERFACE			(1 << 6)
#define CLKF_SSI			(1 << 7)
#define CLKF_DSS			(1 << 8)
#define CLKF_HSOTGUSB			(1 << 9)
#define CLKF_WAIT			(1 << 10)
#define CLKF_NO_WAIT			(1 << 11)
#define CLKF_HSDIV			(1 << 12)
#define CLKF_CLKDM			(1 << 13)

/* DPLL flags */
#define CLKF_LOW_POWER_STOP		(1 << 5)
#define CLKF_LOCK			(1 << 6)
#define CLKF_LOW_POWER_BYPASS		(1 << 7)
#define CLKF_PER			(1 << 8)
#define CLKF_CORE			(1 << 9)
#define CLKF_J_TYPE			(1 << 10)

#define CLK(dev, con, ck)		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
		},			\
		.clk = ck,		\
	}

struct ti_clk {
	const char *name;
	const char *clkdm_name;
	int type;
	void *data;
	struct ti_clk *patch;
	struct clk *clk;
};

struct ti_clk_alias {
	struct ti_clk *clk;
	struct clk_lookup lk;
	struct list_head link;
};

struct ti_clk_fixed {
	u32 frequency;
	u16 flags;
};

struct ti_clk_mux {
	u8 bit_shift;
	int num_parents;
	u16 reg;
	u8 module;
	const char * const *parents;
	u16 flags;
};

struct ti_clk_divider {
	const char *parent;
	u8 bit_shift;
	u16 max_div;
	u16 reg;
	u8 module;
	int *dividers;
	int num_dividers;
	u16 flags;
};

struct ti_clk_fixed_factor {
	const char *parent;
	u16 div;
	u16 mult;
	u16 flags;
};

struct ti_clk_gate {
	const char *parent;
	u8 bit_shift;
	u16 reg;
	u8 module;
	u16 flags;
};

struct ti_clk_composite {
	struct ti_clk_divider *divider;
	struct ti_clk_mux *mux;
	struct ti_clk_gate *gate;
	u16 flags;
};

struct ti_clk_clkdm_gate {
	const char *parent;
	u16 flags;
};

struct ti_clk_dpll {
	int num_parents;
	u16 control_reg;
	u16 idlest_reg;
	u16 autoidle_reg;
	u16 mult_div1_reg;
	u8 module;
	const char **parents;
	u16 flags;
	u8 modes;
	u32 mult_mask;
	u32 div1_mask;
	u32 enable_mask;
	u32 autoidle_mask;
	u32 freqsel_mask;
	u32 idlest_mask;
	u32 dco_mask;
	u32 sddiv_mask;
	u16 max_multiplier;
	u16 max_divider;
	u8 min_divider;
	u8 auto_recal_bit;
	u8 recal_en_bit;
	u8 recal_st_bit;
};

/* Composite clock component types */
enum {
	CLK_COMPONENT_TYPE_GATE = 0,
	CLK_COMPONENT_TYPE_DIVIDER,
	CLK_COMPONENT_TYPE_MUX,
	CLK_COMPONENT_TYPE_MAX,
};

/**
 * struct ti_dt_clk - OMAP DT clock alias declarations
 * @lk: clock lookup definition
 * @node_name: clock DT node to map to
 */
struct ti_dt_clk {
	struct clk_lookup		lk;
	char				*node_name;
};

#define DT_CLK(dev, con, name)		\
	{				\
		.lk = {			\
			.dev_id = dev,	\
			.con_id = con,	\
		},			\
		.node_name = name,	\
	}

/* CLKCTRL type definitions */
struct omap_clkctrl_div_data {
	const int *dividers;
	int max_div;
};

struct omap_clkctrl_bit_data {
	u8 bit;
	u8 type;
	const char * const *parents;
	const void *data;
};

struct omap_clkctrl_reg_data {
	u16 offset;
	const struct omap_clkctrl_bit_data *bit_data;
	u16 flags;
	const char *parent;
};

struct omap_clkctrl_data {
	u32 addr;
	const struct omap_clkctrl_reg_data *regs;
};

#define CLKF_SW_SUP	BIT(0)
#define CLKF_HW_SUP	BIT(1)
#define CLKF_NO_IDLEST	BIT(2)

typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);

struct clk *ti_clk_register_gate(struct ti_clk *setup);
struct clk *ti_clk_register_interface(struct ti_clk *setup);
struct clk *ti_clk_register_mux(struct ti_clk *setup);
struct clk *ti_clk_register_divider(struct ti_clk *setup);
struct clk *ti_clk_register_composite(struct ti_clk *setup);
struct clk *ti_clk_register_dpll(struct ti_clk *setup);
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
			    const char *con);
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
void ti_clk_add_aliases(void);

struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);

int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
			      u8 flags, u8 *width,
			      const struct clk_div_table **table);

void ti_clk_patch_legacy_clks(struct ti_clk **patch);
struct clk *ti_clk_register_clk(struct ti_clk *setup);
int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);

int ti_clk_get_reg_addr(struct device_node *node, int index,
			struct clk_omap_reg *reg);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
		      ti_of_clk_init_cb_t func);
int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);

void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
int of_ti_clk_autoidle_setup(struct device_node *node);
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);

extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
extern const struct clk_hw_omap_ops clkhwops_wait;
extern const struct clk_hw_omap_ops clkhwops_iclk;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;

extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;
extern const struct clk_ops omap_gate_clk_ops;

void omap2_init_clk_clkdm(struct clk_hw *hw);
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);

int omap2_dflt_clk_enable(struct clk_hw *hw);
void omap2_dflt_clk_disable(struct clk_hw *hw);
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
				   struct clk_omap_reg *other_reg,
				   u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
				struct clk_omap_reg *idlest_reg,
				u8 *idlest_bit, u8 *idlest_val);

void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);

u8 omap2_init_dpll_parent(struct clk_hw *hw);
int omap3_noncore_dpll_enable(struct clk_hw *hw);
void omap3_noncore_dpll_disable(struct clk_hw *hw);
int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate);
int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
					   unsigned long rate,
					   unsigned long parent_rate,
					   u8 index);
int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req);
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
			   unsigned long *parent_rate);
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
				    unsigned long parent_rate);

/*
 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
 * that are sourced by DPLL5, and both of these require this clock
 * to be at 120 MHz for proper operation.
 */
#define OMAP3_DPLL5_FREQ_FOR_USBHOST	120000000

unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
			 unsigned long parent_rate);
int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate, u8 index);
int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
			 unsigned long parent_rate);
void omap3_clk_lock_dpll5(void);

unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
					 unsigned long parent_rate);
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
				    unsigned long target_rate,
				    unsigned long *parent_rate);
int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req);

extern struct ti_clk_ll_ops *ti_clk_ll_ops;

#endif
Commit	Line	Data
c82f8957 TK	1	/*
	2	* TI Clock driver internal definitions
	3	*
	4	* Copyright (C) 2014 Texas Instruments, Inc
	5	* Tero Kristo (t-kristo@ti.com)
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation version 2.
	10	*
	11	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	12	* kind, whether express or implied; without even the implied warranty
	13	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16	#ifndef __DRIVERS_CLK_TI_CLOCK__
	17	#define __DRIVERS_CLK_TI_CLOCK__
	18
6dbde947 TK	19	struct clk_omap_divider {
6dbde947 TK	20	struct clk_hw hw;
6c0afb50	21	struct clk_omap_reg reg;
6dbde947 TK	22	u8 shift;
	23	u8 width;
	24	u8 flags;
	25	const struct clk_div_table *table;
	26	};
	27
	28	#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
	29
d83bc5b6 TK	30	struct clk_omap_mux {
d83bc5b6 TK	31	struct clk_hw hw;
6c0afb50	32	struct clk_omap_reg reg;
d83bc5b6 TK	33	u32 *table;
	34	u32 mask;
	35	u8 shift;
	36	u8 flags;
	37	};
	38
	39	#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
	40
c82f8957 TK	41	enum {
	42	TI_CLK_FIXED,
	43	TI_CLK_MUX,
	44	TI_CLK_DIVIDER,
	45	TI_CLK_COMPOSITE,
	46	TI_CLK_FIXED_FACTOR,
	47	TI_CLK_GATE,
	48	TI_CLK_DPLL,
	49	};
	50
	51	/* Global flags */
	52	#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
	53	#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
	54	#define CLKF_SET_RATE_PARENT (1 << 2)
	55	#define CLKF_OMAP3 (1 << 3)
	56	#define CLKF_AM35XX (1 << 4)
	57
	58	/* Gate flags */
	59	#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
	60	#define CLKF_INTERFACE (1 << 6)
	61	#define CLKF_SSI (1 << 7)
	62	#define CLKF_DSS (1 << 8)
	63	#define CLKF_HSOTGUSB (1 << 9)
	64	#define CLKF_WAIT (1 << 10)
	65	#define CLKF_NO_WAIT (1 << 11)
	66	#define CLKF_HSDIV (1 << 12)
	67	#define CLKF_CLKDM (1 << 13)
	68
	69	/* DPLL flags */
	70	#define CLKF_LOW_POWER_STOP (1 << 5)
	71	#define CLKF_LOCK (1 << 6)
	72	#define CLKF_LOW_POWER_BYPASS (1 << 7)
	73	#define CLKF_PER (1 << 8)
	74	#define CLKF_CORE (1 << 9)
	75	#define CLKF_J_TYPE (1 << 10)
	76
	77	#define CLK(dev, con, ck) \
	78	{ \
	79	.lk = { \
	80	.dev_id = dev, \
	81	.con_id = con, \
	82	}, \
	83	.clk = ck, \
	84	}
	85
	86	struct ti_clk {
	87	const char *name;
	88	const char *clkdm_name;
	89	int type;
	90	void *data;
	91	struct ti_clk *patch;
	92	struct clk *clk;
	93	};
	94
	95	struct ti_clk_alias {
	96	struct ti_clk *clk;
	97	struct clk_lookup lk;
	98	struct list_head link;
	99	};
	100
	101	struct ti_clk_fixed {
	102	u32 frequency;
	103	u16 flags;
	104	};
105
106	struct ti_clk_mux {
107	u8 bit_shift;
108	int num_parents;
109	u16 reg;
110	u8 module;
ce382d47	111	const char * const *parents;
c82f8957 TK	112	u16 flags;
	113	};
	114
	115	struct ti_clk_divider {
	116	const char *parent;
	117	u8 bit_shift;
	118	u16 max_div;
	119	u16 reg;
	120	u8 module;
	121	int *dividers;
	122	int num_dividers;
	123	u16 flags;
	124	};
	125
	126	struct ti_clk_fixed_factor {
	127	const char *parent;
	128	u16 div;
	129	u16 mult;
	130	u16 flags;
	131	};
	132
	133	struct ti_clk_gate {
	134	const char *parent;
	135	u8 bit_shift;
	136	u16 reg;
	137	u8 module;
	138	u16 flags;
	139	};
	140
	141	struct ti_clk_composite {
	142	struct ti_clk_divider *divider;
	143	struct ti_clk_mux *mux;
	144	struct ti_clk_gate *gate;
	145	u16 flags;
	146	};
	147
	148	struct ti_clk_clkdm_gate {
	149	const char *parent;
	150	u16 flags;
	151	};
	152
	153	struct ti_clk_dpll {
	154	int num_parents;
	155	u16 control_reg;
	156	u16 idlest_reg;
	157	u16 autoidle_reg;
	158	u16 mult_div1_reg;
	159	u8 module;
	160	const char **parents;
	161	u16 flags;
	162	u8 modes;
	163	u32 mult_mask;
	164	u32 div1_mask;
	165	u32 enable_mask;
	166	u32 autoidle_mask;
	167	u32 freqsel_mask;
	168	u32 idlest_mask;
	169	u32 dco_mask;
	170	u32 sddiv_mask;
	171	u16 max_multiplier;
	172	u16 max_divider;
ed405a23	173	u8 min_divider;
c82f8957 TK	174	u8 auto_recal_bit;
	175	u8 recal_en_bit;
	176	u8 recal_st_bit;
	177	};
	178
a3314e9c TK	179	/* Composite clock component types */
	180	enum {
	181	CLK_COMPONENT_TYPE_GATE = 0,
	182	CLK_COMPONENT_TYPE_DIVIDER,
	183	CLK_COMPONENT_TYPE_MUX,
	184	CLK_COMPONENT_TYPE_MAX,
	185	};
	186
	187	/**
	188	* struct ti_dt_clk - OMAP DT clock alias declarations
	189	* @lk: clock lookup definition
	190	* @node_name: clock DT node to map to
	191	*/
	192	struct ti_dt_clk {
	193	struct clk_lookup lk;
	194	char *node_name;
	195	};
	196
	197	#define DT_CLK(dev, con, name) \
	198	{ \
	199	.lk = { \
	200	.dev_id = dev, \
	201	.con_id = con, \
	202	}, \
	203	.node_name = name, \
	204	}
	205
88a17252 TK	206	/* CLKCTRL type definitions */
	207	struct omap_clkctrl_div_data {
	208	const int *dividers;
	209	int max_div;
	210	};
	211
	212	struct omap_clkctrl_bit_data {
	213	u8 bit;
	214	u8 type;
	215	const char * const *parents;
	216	const void *data;
	217	};
	218
	219	struct omap_clkctrl_reg_data {
	220	u16 offset;
	221	const struct omap_clkctrl_bit_data *bit_data;
	222	u16 flags;
	223	const char *parent;
	224	};
	225
	226	struct omap_clkctrl_data {
	227	u32 addr;
	228	const struct omap_clkctrl_reg_data *regs;
	229	};
	230
	231	#define CLKF_SW_SUP BIT(0)
	232	#define CLKF_HW_SUP BIT(1)
	233	#define CLKF_NO_IDLEST BIT(2)
	234
a3314e9c TK	235	typedef void (ti_of_clk_init_cb_t)(struct clk_hw , struct device_node *);
a3314e9c TK	236
f187616b	237	struct clk ti_clk_register_gate(struct ti_clk setup);
06524fa4	238	struct clk ti_clk_register_interface(struct ti_clk setup);
7c18a65c	239	struct clk ti_clk_register_mux(struct ti_clk setup);
d96f774b	240	struct clk ti_clk_register_divider(struct ti_clk setup);
b26bcf9b	241	struct clk ti_clk_register_composite(struct ti_clk setup);
ed405a23	242	struct clk ti_clk_register_dpll(struct ti_clk setup);
21f0bf2d TK	243	struct clk ti_clk_register(struct device dev, struct clk_hw *hw,
	244	const char *con);
	245	int ti_clk_add_alias(struct device dev, struct clk clk, const char *con);
c17435c5	246	void ti_clk_add_aliases(void);
7c18a65c	247
d96f774b	248	struct clk_hw ti_clk_build_component_div(struct ti_clk_divider setup);
f187616b	249	struct clk_hw ti_clk_build_component_gate(struct ti_clk_gate setup);
7c18a65c TK	250	struct clk_hw ti_clk_build_component_mux(struct ti_clk_mux setup);
7c18a65c TK	251
4f6be565 TK	252	int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
	253	u8 flags, u8 *width,
	254	const struct clk_div_table **table);
	255
c82f8957 TK	256	void ti_clk_patch_legacy_clks(struct ti_clk **patch);
	257	struct clk ti_clk_register_clk(struct ti_clk setup);
	258	int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
	259
6c0afb50 TK	260	int ti_clk_get_reg_addr(struct device_node *node, int index,
6c0afb50 TK	261	struct clk_omap_reg *reg);
a3314e9c TK	262	void ti_dt_clocks_register(struct ti_dt_clk *oclks);
	263	int ti_clk_retry_init(struct device_node node, struct clk_hw hw,
	264	ti_of_clk_init_cb_t func);
	265	int ti_clk_add_component(struct device_node node, struct clk_hw hw, int type);
	266
a53ad8ef	267	void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
bf22bae7	268	int of_ti_clk_autoidle_setup(struct device_node *node);
a5aa8a60	269	void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
bf22bae7	270
0565fb16	271	extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
59245ce0	272	extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
9f37e90e	273	extern const struct clk_hw_omap_ops clkhwops_wait;
ef14db09 TK	274	extern const struct clk_hw_omap_ops clkhwops_iclk;
ef14db09 TK	275	extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
d5a04ddd	276	extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
f2671d5c TK	277	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
	278	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
	279	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
	280	extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
c9a58b0a TK	281	extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
c9a58b0a TK	282	extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
59245ce0	283
a3314e9c TK	284	extern const struct clk_ops ti_clk_divider_ops;
a3314e9c TK	285	extern const struct clk_ops ti_clk_mux_ops;
9a00fa68	286	extern const struct clk_ops omap_gate_clk_ops;
a3314e9c	287
2e1a294c	288	void omap2_init_clk_clkdm(struct clk_hw *hw);
bd86cfdc TK	289	int omap2_clkops_enable_clkdm(struct clk_hw *hw);
	290	void omap2_clkops_disable_clkdm(struct clk_hw *hw);
	291
9f37e90e TK	292	int omap2_dflt_clk_enable(struct clk_hw *hw);
	293	void omap2_dflt_clk_disable(struct clk_hw *hw);
	294	int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
a3314e9c	295	void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
6c0afb50	296	struct clk_omap_reg *other_reg,
a3314e9c TK	297	u8 *other_bit);
a3314e9c TK	298	void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
6c0afb50	299	struct clk_omap_reg *idlest_reg,
a3314e9c TK	300	u8 idlest_bit, u8 idlest_val);
	301
	302	void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
	303	void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
9f37e90e	304
b138b028	305	u8 omap2_init_dpll_parent(struct clk_hw *hw);
0565fb16 TK	306	int omap3_noncore_dpll_enable(struct clk_hw *hw);
	307	void omap3_noncore_dpll_disable(struct clk_hw *hw);
	308	int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
	309	int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
	310	unsigned long parent_rate);
	311	int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
	312	unsigned long rate,
	313	unsigned long parent_rate,
	314	u8 index);
4d341056 SB	315	int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
4d341056 SB	316	struct clk_rate_request *req);
0565fb16 TK	317	long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
	318	unsigned long *parent_rate);
	319	unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
	320	unsigned long parent_rate);
	321
035cd485 RW	322	/*
	323	* OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
	324	* that are sourced by DPLL5, and both of these require this clock
	325	* to be at 120 MHz for proper operation.
	326	*/
	327	#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
	328
0565fb16 TK	329	unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
	330	int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
	331	unsigned long parent_rate);
	332	int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
	333	unsigned long parent_rate, u8 index);
035cd485 RW	334	int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
035cd485 RW	335	unsigned long parent_rate);
0565fb16	336	void omap3_clk_lock_dpll5(void);
b138b028	337
59245ce0 TK	338	unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
	339	unsigned long parent_rate);
	340	long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
	341	unsigned long target_rate,
	342	unsigned long *parent_rate);
4d341056 SB	343	int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
4d341056 SB	344	struct clk_rate_request *req);
59245ce0	345
e9e63088 TK	346	extern struct ti_clk_ll_ops *ti_clk_ll_ops;
e9e63088 TK	347
c82f8957	348	#endif