[mirror_ubuntu-focal-kernel.git] / drivers / clk / ti / divider.c

/*
 * TI Divider Clock
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"

#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__

#define div_mask(d)	((1 << ((d)->width)) - 1)

static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
{
	unsigned int maxdiv = 0;
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div > maxdiv)
			maxdiv = clkt->div;
	return maxdiv;
}

static unsigned int _get_maxdiv(struct clk_omap_divider *divider)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return div_mask(divider);
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << div_mask(divider);
	if (divider->table)
		return _get_table_maxdiv(divider->table);
	return div_mask(divider) + 1;
}

static unsigned int _get_table_div(const struct clk_div_table *table,
				   unsigned int val)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->val == val)
			return clkt->div;
	return 0;
}

static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return val;
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return 1 << val;
	if (divider->table)
		return _get_table_div(divider->table, val);
	return val + 1;
}

static unsigned int _get_table_val(const struct clk_div_table *table,
				   unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return clkt->val;
	return 0;
}

static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
{
	if (divider->flags & CLK_DIVIDER_ONE_BASED)
		return div;
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return __ffs(div);
	if (divider->table)
		return  _get_table_val(divider->table, div);
	return div - 1;
}

static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
	unsigned int div, val;

	val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
	val &= div_mask(divider);

	div = _get_div(divider, val);
	if (!div) {
		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
		     "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
		     clk_hw_get_name(hw));
		return parent_rate;
	}

	return DIV_ROUND_UP(parent_rate, div);
}

/*
 * The reverse of DIV_ROUND_UP: The maximum number which
 * divided by m is r
 */
#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)

static bool _is_valid_table_div(const struct clk_div_table *table,
				unsigned int div)
{
	const struct clk_div_table *clkt;

	for (clkt = table; clkt->div; clkt++)
		if (clkt->div == div)
			return true;
	return false;
}

static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
{
	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
		return is_power_of_2(div);
	if (divider->table)
		return _is_valid_table_div(divider->table, div);
	return true;
}

static int _div_round_up(const struct clk_div_table *table,
			 unsigned long parent_rate, unsigned long rate)
{
	const struct clk_div_table *clkt;
	int up = INT_MAX;
	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);

	for (clkt = table; clkt->div; clkt++) {
		if (clkt->div == div)
			return clkt->div;
		else if (clkt->div < div)
			continue;

		if ((clkt->div - div) < (up - div))
			up = clkt->div;
	}

	return up;
}

static int _div_round(const struct clk_div_table *table,
		      unsigned long parent_rate, unsigned long rate)
{
	if (!table)
		return DIV_ROUND_UP(parent_rate, rate);

	return _div_round_up(table, parent_rate, rate);
}

static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
				  unsigned long *best_parent_rate)
{
	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
	int i, bestdiv = 0;
	unsigned long parent_rate, best = 0, now, maxdiv;
	unsigned long parent_rate_saved = *best_parent_rate;

	if (!rate)
		rate = 1;

	maxdiv = _get_maxdiv(divider);

	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
		parent_rate = *best_parent_rate;
		bestdiv = _div_round(divider->table, parent_rate, rate);
		bestdiv = bestdiv == 0 ? 1 : bestdiv;
		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
		return bestdiv;
	}

	/*
	 * The maximum divider we can use without overflowing
	 * unsigned long in rate * i below
	 */
	maxdiv = min(ULONG_MAX / rate, maxdiv);

	for (i = 1; i <= maxdiv; i++) {
		if (!_is_valid_div(divider, i))
			continue;
		if (rate * i == parent_rate_saved) {
			/*
			 * It's the most ideal case if the requested rate can be
			 * divided from parent clock without needing to change
			 * parent rate, so return the divider immediately.
			 */
			*best_parent_rate = parent_rate_saved;
			return i;
		}
		parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
				MULT_ROUND_UP(rate, i));
		now = DIV_ROUND_UP(parent_rate, i);
		if (now <= rate && now > best) {
			bestdiv = i;
			best = now;
			*best_parent_rate = parent_rate;
		}
	}

	if (!bestdiv) {
		bestdiv = _get_maxdiv(divider);
		*best_parent_rate =
			clk_hw_round_rate(clk_hw_get_parent(hw), 1);
	}

	return bestdiv;
}

static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long *prate)
{
	int div;
	div = ti_clk_divider_bestdiv(hw, rate, prate);

	return DIV_ROUND_UP(*prate, div);
}

static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{
	struct clk_omap_divider *divider;
	unsigned int div, value;
	u32 val;

	if (!hw || !rate)
		return -EINVAL;

	divider = to_clk_omap_divider(hw);

	div = DIV_ROUND_UP(parent_rate, rate);
	value = _get_val(divider, div);

	if (value > div_mask(divider))
		value = div_mask(divider);

	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
		val = div_mask(divider) << (divider->shift + 16);
	} else {
		val = ti_clk_ll_ops->clk_readl(&divider->reg);
		val &= ~(div_mask(divider) << divider->shift);
	}
	val |= value << divider->shift;
	ti_clk_ll_ops->clk_writel(val, &divider->reg);

	ti_clk_latch(&divider->reg, divider->latch);

	return 0;
}

/**
 * clk_divider_save_context - Save the divider value
 * @hw: pointer  struct clk_hw
 *
 * Save the divider value
 */
static int clk_divider_save_context(struct clk_hw *hw)
{
	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
	u32 val;

	val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
	divider->context = val & div_mask(divider);

	return 0;
}

/**
 * clk_divider_restore_context - restore the saved the divider value
 * @hw: pointer  struct clk_hw
 *
 * Restore the saved the divider value
 */
static void clk_divider_restore_context(struct clk_hw *hw)
{
	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
	u32 val;

	val = ti_clk_ll_ops->clk_readl(&divider->reg);
	val &= ~(div_mask(divider) << divider->shift);
	val |= divider->context << divider->shift;
	ti_clk_ll_ops->clk_writel(val, &divider->reg);
}

const struct clk_ops ti_clk_divider_ops = {
	.recalc_rate = ti_clk_divider_recalc_rate,
	.round_rate = ti_clk_divider_round_rate,
	.set_rate = ti_clk_divider_set_rate,
	.save_context = clk_divider_save_context,
	.restore_context = clk_divider_restore_context,
};

static struct clk *_register_divider(struct device *dev, const char *name,
				     const char *parent_name,
				     unsigned long flags,
				     struct clk_omap_reg *reg,
				     u8 shift, u8 width, s8 latch,
				     u8 clk_divider_flags,
				     const struct clk_div_table *table)
{
	struct clk_omap_divider *div;
	struct clk *clk;
	struct clk_init_data init;

	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
		if (width + shift > 16) {
			pr_warn("divider value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the divider */
	div = kzalloc(sizeof(*div), GFP_KERNEL);
	if (!div)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &ti_clk_divider_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);

	/* struct clk_divider assignments */
	memcpy(&div->reg, reg, sizeof(*reg));
	div->shift = shift;
	div->width = width;
	div->latch = latch;
	div->flags = clk_divider_flags;
	div->hw.init = &init;
	div->table = table;

	/* register the clock */
	clk = ti_clk_register(dev, &div->hw, name);

	if (IS_ERR(clk))
		kfree(div);

	return clk;
}

int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
			      u8 flags, u8 *width,
			      const struct clk_div_table **table)
{
	int valid_div = 0;
	u32 val;
	int div;
	int i;
	struct clk_div_table *tmp;

	if (!div_table) {
		if (flags & CLKF_INDEX_STARTS_AT_ONE)
			val = 1;
		else
			val = 0;

		div = 1;

		while (div < max_div) {
			if (flags & CLKF_INDEX_POWER_OF_TWO)
				div <<= 1;
			else
				div++;
			val++;
		}

		*width = fls(val);
		*table = NULL;

		return 0;
	}

	i = 0;

	while (!num_dividers || i < num_dividers) {
		if (div_table[i] == -1)
			break;
		if (div_table[i])
			valid_div++;
		i++;
	}

	num_dividers = i;

	tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
	if (!tmp) {
		*table = ERR_PTR(-ENOMEM);
		return -ENOMEM;
	}

	valid_div = 0;
	*width = 0;

	for (i = 0; i < num_dividers; i++)
		if (div_table[i] > 0) {
			tmp[valid_div].div = div_table[i];
			tmp[valid_div].val = i;
			valid_div++;
			*width = i;
		}

	*width = fls(*width);
	*table = tmp;

	return 0;
}

static const struct clk_div_table *
_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
{
	const struct clk_div_table *table = NULL;

	ti_clk_parse_divider_data(setup->dividers, setup->num_dividers,
				  setup->max_div, setup->flags, width,
				  &table);

	return table;
}

struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
{
	struct clk_omap_divider *div;
	struct clk_omap_reg *reg;
	int ret;

	if (!setup)
		return NULL;

	div = kzalloc(sizeof(*div), GFP_KERNEL);
	if (!div)
		return ERR_PTR(-ENOMEM);

	reg = (struct clk_omap_reg *)&div->reg;
	reg->index = setup->module;
	reg->offset = setup->reg;

	if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
		div->flags |= CLK_DIVIDER_ONE_BASED;

	if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
		div->flags |= CLK_DIVIDER_POWER_OF_TWO;

	div->table = _get_div_table_from_setup(setup, &div->width);
	if (IS_ERR(div->table)) {
		ret = PTR_ERR(div->table);
		kfree(div);
		return ERR_PTR(ret);
	}


	div->shift = setup->bit_shift;
	div->latch = -EINVAL;

	return &div->hw;
}

struct clk *ti_clk_register_divider(struct ti_clk *setup)
{
	struct ti_clk_divider *div = setup->data;
	struct clk_omap_reg reg = {
		.index = div->module,
		.offset = div->reg,
	};
	u8 width;
	u32 flags = 0;
	u8 div_flags = 0;
	const struct clk_div_table *table;
	struct clk *clk;

	if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
		div_flags |= CLK_DIVIDER_ONE_BASED;

	if (div->flags & CLKF_INDEX_POWER_OF_TWO)
		div_flags |= CLK_DIVIDER_POWER_OF_TWO;

	if (div->flags & CLKF_SET_RATE_PARENT)
		flags |= CLK_SET_RATE_PARENT;

	table = _get_div_table_from_setup(div, &width);
	if (IS_ERR(table))
		return (struct clk *)table;

	clk = _register_divider(NULL, setup->name, div->parent,
				flags, &reg, div->bit_shift,
				width, -EINVAL, div_flags, table);

	if (IS_ERR(clk))
		kfree(table);

	return clk;
}

static struct clk_div_table *
__init ti_clk_get_div_table(struct device_node *node)
{
	struct clk_div_table *table;
	const __be32 *divspec;
	u32 val;
	u32 num_div;
	u32 valid_div;
	int i;

	divspec = of_get_property(node, "ti,dividers", &num_div);

	if (!divspec)
		return NULL;

	num_div /= 4;

	valid_div = 0;

	/* Determine required size for divider table */
	for (i = 0; i < num_div; i++) {
		of_property_read_u32_index(node, "ti,dividers", i, &val);
		if (val)
			valid_div++;
	}

	if (!valid_div) {
		pr_err("no valid dividers for %pOFn table\n", node);
		return ERR_PTR(-EINVAL);
	}

	table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);

	if (!table)
		return ERR_PTR(-ENOMEM);

	valid_div = 0;

	for (i = 0; i < num_div; i++) {
		of_property_read_u32_index(node, "ti,dividers", i, &val);
		if (val) {
			table[valid_div].div = val;
			table[valid_div].val = i;
			valid_div++;
		}
	}

	return table;
}

static int _get_divider_width(struct device_node *node,
			      const struct clk_div_table *table,
			      u8 flags)
{
	u32 min_div;
	u32 max_div;
	u32 val = 0;
	u32 div;

	if (!table) {
		/* Clk divider table not provided, determine min/max divs */
		if (of_property_read_u32(node, "ti,min-div", &min_div))
			min_div = 1;

		if (of_property_read_u32(node, "ti,max-div", &max_div)) {
			pr_err("no max-div for %pOFn!\n", node);
			return -EINVAL;
		}

		/* Determine bit width for the field */
		if (flags & CLK_DIVIDER_ONE_BASED)
			val = 1;

		div = min_div;

		while (div < max_div) {
			if (flags & CLK_DIVIDER_POWER_OF_TWO)
				div <<= 1;
			else
				div++;
			val++;
		}
	} else {
		div = 0;

		while (table[div].div) {
			val = table[div].val;
			div++;
		}
	}

	return fls(val);
}

static int __init ti_clk_divider_populate(struct device_node *node,
	struct clk_omap_reg *reg, const struct clk_div_table **table,
	u32 *flags, u8 *div_flags, u8 *width, u8 *shift, s8 *latch)
{
	u32 val;
	int ret;

	ret = ti_clk_get_reg_addr(node, 0, reg);
	if (ret)
		return ret;

	if (!of_property_read_u32(node, "ti,bit-shift", &val))
		*shift = val;
	else
		*shift = 0;

	if (latch) {
		if (!of_property_read_u32(node, "ti,latch-bit", &val))
			*latch = val;
		else
			*latch = -EINVAL;
	}

	*flags = 0;
	*div_flags = 0;

	if (of_property_read_bool(node, "ti,index-starts-at-one"))
		*div_flags |= CLK_DIVIDER_ONE_BASED;

	if (of_property_read_bool(node, "ti,index-power-of-two"))
		*div_flags |= CLK_DIVIDER_POWER_OF_TWO;

	if (of_property_read_bool(node, "ti,set-rate-parent"))
		*flags |= CLK_SET_RATE_PARENT;

	*table = ti_clk_get_div_table(node);

	if (IS_ERR(*table))
		return PTR_ERR(*table);

	*width = _get_divider_width(node, *table, *div_flags);

	return 0;
}

/**
 * of_ti_divider_clk_setup - Setup function for simple div rate clock
 * @node: device node for this clock
 *
 * Sets up a basic divider clock.
 */
static void __init of_ti_divider_clk_setup(struct device_node *node)
{
	struct clk *clk;
	const char *parent_name;
	struct clk_omap_reg reg;
	u8 clk_divider_flags = 0;
	u8 width = 0;
	u8 shift = 0;
	s8 latch = -EINVAL;
	const struct clk_div_table *table = NULL;
	u32 flags = 0;

	parent_name = of_clk_get_parent_name(node, 0);

	if (ti_clk_divider_populate(node, &reg, &table, &flags,
				    &clk_divider_flags, &width, &shift, &latch))
		goto cleanup;

	clk = _register_divider(NULL, node->name, parent_name, flags, &reg,
				shift, width, latch, clk_divider_flags, table);

	if (!IS_ERR(clk)) {
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
		of_ti_clk_autoidle_setup(node);
		return;
	}

cleanup:
	kfree(table);
}
CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);

static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
{
	struct clk_omap_divider *div;
	u32 val;

	div = kzalloc(sizeof(*div), GFP_KERNEL);
	if (!div)
		return;

	if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
				    &div->flags, &div->width, &div->shift,
				    NULL) < 0)
		goto cleanup;

	if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
		return;

cleanup:
	kfree(div->table);
	kfree(div);
}
CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
	       of_ti_composite_divider_clk_setup);
Commit	Line	Data
b4761198 TK	1	/*
	2	* TI Divider Clock
	3	*
	4	* Copyright (C) 2013 Texas Instruments, Inc.
	5	*
	6	* Tero Kristo <t-kristo@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/clk-provider.h>
	19	#include <linux/slab.h>
	20	#include <linux/err.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/clk/ti.h>
d96f774b	24	#include "clock.h"
b4761198 TK	25
	26	#undef pr_fmt
	27	#define pr_fmt(fmt) "%s: " fmt, __func__
	28
b4761198 TK	29	#define div_mask(d) ((1 << ((d)->width)) - 1)
	30
	31	static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
	32	{
	33	unsigned int maxdiv = 0;
	34	const struct clk_div_table *clkt;
	35
	36	for (clkt = table; clkt->div; clkt++)
	37	if (clkt->div > maxdiv)
	38	maxdiv = clkt->div;
	39	return maxdiv;
	40	}
	41
6dbde947	42	static unsigned int _get_maxdiv(struct clk_omap_divider *divider)
b4761198 TK	43	{
	44	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	45	return div_mask(divider);
	46	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	47	return 1 << div_mask(divider);
	48	if (divider->table)
	49	return _get_table_maxdiv(divider->table);
	50	return div_mask(divider) + 1;
	51	}
	52
	53	static unsigned int _get_table_div(const struct clk_div_table *table,
	54	unsigned int val)
	55	{
	56	const struct clk_div_table *clkt;
	57
	58	for (clkt = table; clkt->div; clkt++)
	59	if (clkt->val == val)
	60	return clkt->div;
	61	return 0;
	62	}
	63
6dbde947	64	static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
b4761198 TK	65	{
	66	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	67	return val;
	68	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	69	return 1 << val;
	70	if (divider->table)
	71	return _get_table_div(divider->table, val);
	72	return val + 1;
	73	}
	74
	75	static unsigned int _get_table_val(const struct clk_div_table *table,
	76	unsigned int div)
	77	{
	78	const struct clk_div_table *clkt;
	79
	80	for (clkt = table; clkt->div; clkt++)
	81	if (clkt->div == div)
	82	return clkt->val;
	83	return 0;
	84	}
	85
6dbde947	86	static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
b4761198 TK	87	{
	88	if (divider->flags & CLK_DIVIDER_ONE_BASED)
	89	return div;
	90	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	91	return __ffs(div);
	92	if (divider->table)
	93	return _get_table_val(divider->table, div);
	94	return div - 1;
	95	}
	96
	97	static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
	98	unsigned long parent_rate)
	99	{
6dbde947	100	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
b4761198 TK	101	unsigned int div, val;
b4761198 TK	102
6c0afb50	103	val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
b4761198 TK	104	val &= div_mask(divider);
	105
	106	div = _get_div(divider, val);
	107	if (!div) {
	108	WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
	109	"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
a53ad8ef	110	clk_hw_get_name(hw));
b4761198 TK	111	return parent_rate;
	112	}
	113
7e50e7e1	114	return DIV_ROUND_UP(parent_rate, div);
b4761198 TK	115	}
	116
	117	/*
	118	* The reverse of DIV_ROUND_UP: The maximum number which
	119	* divided by m is r
	120	*/
	121	#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
	122
	123	static bool _is_valid_table_div(const struct clk_div_table *table,
	124	unsigned int div)
	125	{
	126	const struct clk_div_table *clkt;
	127
	128	for (clkt = table; clkt->div; clkt++)
	129	if (clkt->div == div)
	130	return true;
	131	return false;
	132	}
	133
6dbde947	134	static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
b4761198 TK	135	{
	136	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
	137	return is_power_of_2(div);
	138	if (divider->table)
	139	return _is_valid_table_div(divider->table, div);
	140	return true;
	141	}
	142
ced30683 K	143	static int _div_round_up(const struct clk_div_table *table,
	144	unsigned long parent_rate, unsigned long rate)
	145	{
	146	const struct clk_div_table *clkt;
	147	int up = INT_MAX;
	148	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
	149
	150	for (clkt = table; clkt->div; clkt++) {
	151	if (clkt->div == div)
	152	return clkt->div;
	153	else if (clkt->div < div)
	154	continue;
	155
	156	if ((clkt->div - div) < (up - div))
	157	up = clkt->div;
	158	}
	159
	160	return up;
	161	}
	162
	163	static int _div_round(const struct clk_div_table *table,
	164	unsigned long parent_rate, unsigned long rate)
	165	{
	166	if (!table)
	167	return DIV_ROUND_UP(parent_rate, rate);
	168
	169	return _div_round_up(table, parent_rate, rate);
	170	}
	171
b4761198 TK	172	static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
	173	unsigned long *best_parent_rate)
	174	{
6dbde947	175	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
b4761198 TK	176	int i, bestdiv = 0;
	177	unsigned long parent_rate, best = 0, now, maxdiv;
	178	unsigned long parent_rate_saved = *best_parent_rate;
	179
	180	if (!rate)
	181	rate = 1;
	182
	183	maxdiv = _get_maxdiv(divider);
	184
98d8a60e	185	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
b4761198	186	parent_rate = *best_parent_rate;
ced30683	187	bestdiv = _div_round(divider->table, parent_rate, rate);
b4761198 TK	188	bestdiv = bestdiv == 0 ? 1 : bestdiv;
	189	bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
	190	return bestdiv;
	191	}
	192
	193	/*
	194	* The maximum divider we can use without overflowing
	195	* unsigned long in rate * i below
	196	*/
	197	maxdiv = min(ULONG_MAX / rate, maxdiv);
	198
	199	for (i = 1; i <= maxdiv; i++) {
	200	if (!_is_valid_div(divider, i))
	201	continue;
	202	if (rate * i == parent_rate_saved) {
	203	/*
	204	* It's the most ideal case if the requested rate can be
	205	* divided from parent clock without needing to change
	206	* parent rate, so return the divider immediately.
	207	*/
	208	*best_parent_rate = parent_rate_saved;
	209	return i;
	210	}
a53ad8ef	211	parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
b4761198	212	MULT_ROUND_UP(rate, i));
7e50e7e1	213	now = DIV_ROUND_UP(parent_rate, i);
b4761198 TK	214	if (now <= rate && now > best) {
	215	bestdiv = i;
	216	best = now;
	217	*best_parent_rate = parent_rate;
	218	}
	219	}
	220
	221	if (!bestdiv) {
	222	bestdiv = _get_maxdiv(divider);
	223	*best_parent_rate =
a53ad8ef	224	clk_hw_round_rate(clk_hw_get_parent(hw), 1);
b4761198 TK	225	}
	226
	227	return bestdiv;
	228	}
	229
	230	static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
	231	unsigned long *prate)
	232	{
	233	int div;
	234	div = ti_clk_divider_bestdiv(hw, rate, prate);
	235
7e50e7e1	236	return DIV_ROUND_UP(*prate, div);
b4761198 TK	237	}
	238
	239	static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
	240	unsigned long parent_rate)
	241	{
6dbde947	242	struct clk_omap_divider *divider;
b4761198	243	unsigned int div, value;
b4761198 TK	244	u32 val;
b4761198 TK	245
2f103251 NM	246	if (!hw \|\| !rate)
	247	return -EINVAL;
	248
6dbde947	249	divider = to_clk_omap_divider(hw);
2f103251	250
7e50e7e1	251	div = DIV_ROUND_UP(parent_rate, rate);
b4761198 TK	252	value = _get_val(divider, div);
	253
	254	if (value > div_mask(divider))
	255	value = div_mask(divider);
	256
b4761198 TK	257	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
	258	val = div_mask(divider) << (divider->shift + 16);
	259	} else {
6c0afb50	260	val = ti_clk_ll_ops->clk_readl(&divider->reg);
b4761198 TK	261	val &= ~(div_mask(divider) << divider->shift);
	262	}
	263	val \|= value << divider->shift;
6c0afb50	264	ti_clk_ll_ops->clk_writel(val, &divider->reg);
b4761198	265
b44a0300 TK	266	ti_clk_latch(&divider->reg, divider->latch);
b44a0300 TK	267
b4761198 TK	268	return 0;
	269	}
	270
d6e7bbc1 RD	271	/**
	272	* clk_divider_save_context - Save the divider value
	273	* @hw: pointer struct clk_hw
	274	*
	275	* Save the divider value
	276	*/
	277	static int clk_divider_save_context(struct clk_hw *hw)
	278	{
	279	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
	280	u32 val;
	281
	282	val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
	283	divider->context = val & div_mask(divider);
	284
	285	return 0;
	286	}
	287
	288	/**
	289	* clk_divider_restore_context - restore the saved the divider value
	290	* @hw: pointer struct clk_hw
	291	*
	292	* Restore the saved the divider value
	293	*/
	294	static void clk_divider_restore_context(struct clk_hw *hw)
	295	{
	296	struct clk_omap_divider *divider = to_clk_omap_divider(hw);
	297	u32 val;
	298
	299	val = ti_clk_ll_ops->clk_readl(&divider->reg);
	300	val &= ~(div_mask(divider) << divider->shift);
	301	val \|= divider->context << divider->shift;
	302	ti_clk_ll_ops->clk_writel(val, &divider->reg);
	303	}
	304
b4761198 TK	305	const struct clk_ops ti_clk_divider_ops = {
	306	.recalc_rate = ti_clk_divider_recalc_rate,
	307	.round_rate = ti_clk_divider_round_rate,
	308	.set_rate = ti_clk_divider_set_rate,
d6e7bbc1 RD	309	.save_context = clk_divider_save_context,
d6e7bbc1 RD	310	.restore_context = clk_divider_restore_context,
b4761198 TK	311	};
	312
	313	static struct clk _register_divider(struct device dev, const char *name,
	314	const char *parent_name,
6c0afb50 TK	315	unsigned long flags,
6c0afb50 TK	316	struct clk_omap_reg *reg,
b44a0300 TK	317	u8 shift, u8 width, s8 latch,
b44a0300 TK	318	u8 clk_divider_flags,
167af5ef	319	const struct clk_div_table *table)
b4761198	320	{
6dbde947	321	struct clk_omap_divider *div;
b4761198 TK	322	struct clk *clk;
	323	struct clk_init_data init;
	324
	325	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
	326	if (width + shift > 16) {
	327	pr_warn("divider value exceeds LOWORD field\n");
	328	return ERR_PTR(-EINVAL);
	329	}
	330	}
	331
	332	/* allocate the divider */
	333	div = kzalloc(sizeof(*div), GFP_KERNEL);
f80c8a29	334	if (!div)
b4761198	335	return ERR_PTR(-ENOMEM);
b4761198 TK	336
	337	init.name = name;
	338	init.ops = &ti_clk_divider_ops;
	339	init.flags = flags \| CLK_IS_BASIC;
	340	init.parent_names = (parent_name ? &parent_name : NULL);
	341	init.num_parents = (parent_name ? 1 : 0);
	342
	343	/* struct clk_divider assignments */
6c0afb50	344	memcpy(&div->reg, reg, sizeof(*reg));
b4761198 TK	345	div->shift = shift;
b4761198 TK	346	div->width = width;
b44a0300	347	div->latch = latch;
b4761198	348	div->flags = clk_divider_flags;
b4761198 TK	349	div->hw.init = &init;
	350	div->table = table;
	351
	352	/* register the clock */
1ae79c46	353	clk = ti_clk_register(dev, &div->hw, name);
b4761198 TK	354
	355	if (IS_ERR(clk))
	356	kfree(div);
	357
	358	return clk;
	359	}
	360
4f6be565 TK	361	int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
	362	u8 flags, u8 *width,
	363	const struct clk_div_table **table)
d96f774b TK	364	{
d96f774b TK	365	int valid_div = 0;
d96f774b	366	u32 val;
4f6be565 TK	367	int div;
	368	int i;
	369	struct clk_div_table *tmp;
d96f774b	370
4f6be565	371	if (!div_table) {
d96f774b TK	372	if (flags & CLKF_INDEX_STARTS_AT_ONE)
	373	val = 1;
	374	else
	375	val = 0;
	376
	377	div = 1;
	378
4f6be565	379	while (div < max_div) {
d96f774b TK	380	if (flags & CLKF_INDEX_POWER_OF_TWO)
	381	div <<= 1;
	382	else
	383	div++;
	384	val++;
	385	}
	386
	387	*width = fls(val);
4f6be565	388	*table = NULL;
d96f774b	389
4f6be565	390	return 0;
d96f774b TK	391	}
d96f774b TK	392
4f6be565 TK	393	i = 0;
	394
	395	while (!num_dividers \|\| i < num_dividers) {
	396	if (div_table[i] == -1)
	397	break;
	398	if (div_table[i])
d96f774b	399	valid_div++;
4f6be565 TK	400	i++;
4f6be565 TK	401	}
d96f774b	402
4f6be565 TK	403	num_dividers = i;
4f6be565 TK	404
6396bb22	405	tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
303aef8b DC	406	if (!tmp) {
303aef8b DC	407	*table = ERR_PTR(-ENOMEM);
4f6be565	408	return -ENOMEM;
303aef8b	409	}
d96f774b TK	410
	411	valid_div = 0;
	412	*width = 0;
	413
4f6be565 TK	414	for (i = 0; i < num_dividers; i++)
	415	if (div_table[i] > 0) {
	416	tmp[valid_div].div = div_table[i];
	417	tmp[valid_div].val = i;
d96f774b TK	418	valid_div++;
	419	*width = i;
	420	}
	421
	422	width = fls(width);
4f6be565 TK	423	*table = tmp;
	424
	425	return 0;
	426	}
	427
	428	static const struct clk_div_table *
	429	_get_div_table_from_setup(struct ti_clk_divider setup, u8 width)
	430	{
	431	const struct clk_div_table *table = NULL;
	432
	433	ti_clk_parse_divider_data(setup->dividers, setup->num_dividers,
	434	setup->max_div, setup->flags, width,
	435	&table);
d96f774b TK	436
	437	return table;
	438	}
	439
	440	struct clk_hw ti_clk_build_component_div(struct ti_clk_divider setup)
	441	{
6dbde947	442	struct clk_omap_divider *div;
d96f774b	443	struct clk_omap_reg *reg;
303aef8b	444	int ret;
d96f774b TK	445
	446	if (!setup)
	447	return NULL;
	448
	449	div = kzalloc(sizeof(*div), GFP_KERNEL);
	450	if (!div)
	451	return ERR_PTR(-ENOMEM);
	452
	453	reg = (struct clk_omap_reg *)&div->reg;
	454	reg->index = setup->module;
	455	reg->offset = setup->reg;
	456
	457	if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
	458	div->flags \|= CLK_DIVIDER_ONE_BASED;
	459
	460	if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
	461	div->flags \|= CLK_DIVIDER_POWER_OF_TWO;
	462
	463	div->table = _get_div_table_from_setup(setup, &div->width);
303aef8b DC	464	if (IS_ERR(div->table)) {
	465	ret = PTR_ERR(div->table);
	466	kfree(div);
	467	return ERR_PTR(ret);
	468	}
	469
d96f774b TK	470
d96f774b TK	471	div->shift = setup->bit_shift;
b44a0300	472	div->latch = -EINVAL;
d96f774b TK	473
	474	return &div->hw;
	475	}
	476
	477	struct clk ti_clk_register_divider(struct ti_clk setup)
	478	{
3417f352 AB	479	struct ti_clk_divider *div = setup->data;
	480	struct clk_omap_reg reg = {
	481	.index = div->module,
	482	.offset = div->reg,
	483	};
d96f774b TK	484	u8 width;
	485	u32 flags = 0;
	486	u8 div_flags = 0;
4f6be565	487	const struct clk_div_table *table;
d96f774b TK	488	struct clk *clk;
d96f774b TK	489
d96f774b TK	490	if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
	491	div_flags \|= CLK_DIVIDER_ONE_BASED;
	492
	493	if (div->flags & CLKF_INDEX_POWER_OF_TWO)
	494	div_flags \|= CLK_DIVIDER_POWER_OF_TWO;
	495
	496	if (div->flags & CLKF_SET_RATE_PARENT)
	497	flags \|= CLK_SET_RATE_PARENT;
	498
	499	table = _get_div_table_from_setup(div, &width);
	500	if (IS_ERR(table))
	501	return (struct clk *)table;
	502
	503	clk = _register_divider(NULL, setup->name, div->parent,
3417f352	504	flags, &reg, div->bit_shift,
b44a0300	505	width, -EINVAL, div_flags, table);
d96f774b TK	506
	507	if (IS_ERR(clk))
	508	kfree(table);
	509
	510	return clk;
	511	}
	512
e8627a9e BW	513	static struct clk_div_table *
e8627a9e BW	514	__init ti_clk_get_div_table(struct device_node *node)
b4761198 TK	515	{
	516	struct clk_div_table *table;
	517	const __be32 *divspec;
	518	u32 val;
	519	u32 num_div;
	520	u32 valid_div;
	521	int i;
	522
	523	divspec = of_get_property(node, "ti,dividers", &num_div);
	524
	525	if (!divspec)
	526	return NULL;
	527
	528	num_div /= 4;
	529
	530	valid_div = 0;
	531
	532	/* Determine required size for divider table */
	533	for (i = 0; i < num_div; i++) {
	534	of_property_read_u32_index(node, "ti,dividers", i, &val);
	535	if (val)
	536	valid_div++;
	537	}
	538
	539	if (!valid_div) {
e665f029	540	pr_err("no valid dividers for %pOFn table\n", node);
b4761198 TK	541	return ERR_PTR(-EINVAL);
	542	}
	543
6396bb22	544	table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
b4761198 TK	545
	546	if (!table)
	547	return ERR_PTR(-ENOMEM);
	548
	549	valid_div = 0;
	550
	551	for (i = 0; i < num_div; i++) {
	552	of_property_read_u32_index(node, "ti,dividers", i, &val);
	553	if (val) {
	554	table[valid_div].div = val;
	555	table[valid_div].val = i;
	556	valid_div++;
	557	}
	558	}
	559
	560	return table;
	561	}
	562
	563	static int _get_divider_width(struct device_node *node,
	564	const struct clk_div_table *table,
	565	u8 flags)
	566	{
	567	u32 min_div;
	568	u32 max_div;
	569	u32 val = 0;
	570	u32 div;
	571
	572	if (!table) {
	573	/* Clk divider table not provided, determine min/max divs */
	574	if (of_property_read_u32(node, "ti,min-div", &min_div))
	575	min_div = 1;
	576
	577	if (of_property_read_u32(node, "ti,max-div", &max_div)) {
e665f029	578	pr_err("no max-div for %pOFn!\n", node);
b4761198 TK	579	return -EINVAL;
	580	}
	581
	582	/* Determine bit width for the field */
	583	if (flags & CLK_DIVIDER_ONE_BASED)
	584	val = 1;
	585
	586	div = min_div;
	587
	588	while (div < max_div) {
	589	if (flags & CLK_DIVIDER_POWER_OF_TWO)
	590	div <<= 1;
	591	else
	592	div++;
	593	val++;
	594	}
	595	} else {
	596	div = 0;
	597
	598	while (table[div].div) {
	599	val = table[div].val;
	600	div++;
	601	}
	602	}
	603
	604	return fls(val);
	605	}
	606
	607	static int __init ti_clk_divider_populate(struct device_node *node,
6c0afb50	608	struct clk_omap_reg reg, const struct clk_div_table *table,
b44a0300	609	u32 flags, u8 div_flags, u8 width, u8 shift, s8 *latch)
b4761198 TK	610	{
b4761198 TK	611	u32 val;
6c0afb50	612	int ret;
b4761198	613
6c0afb50 TK	614	ret = ti_clk_get_reg_addr(node, 0, reg);
	615	if (ret)
	616	return ret;
b4761198 TK	617
	618	if (!of_property_read_u32(node, "ti,bit-shift", &val))
	619	*shift = val;
	620	else
	621	*shift = 0;
	622
b44a0300 TK	623	if (latch) {
	624	if (!of_property_read_u32(node, "ti,latch-bit", &val))
	625	*latch = val;
	626	else
	627	*latch = -EINVAL;
	628	}
	629
b4761198 TK	630	*flags = 0;
	631	*div_flags = 0;
	632
	633	if (of_property_read_bool(node, "ti,index-starts-at-one"))
	634	*div_flags \|= CLK_DIVIDER_ONE_BASED;
	635
	636	if (of_property_read_bool(node, "ti,index-power-of-two"))
	637	*div_flags \|= CLK_DIVIDER_POWER_OF_TWO;
	638
	639	if (of_property_read_bool(node, "ti,set-rate-parent"))
	640	*flags \|= CLK_SET_RATE_PARENT;
	641
	642	*table = ti_clk_get_div_table(node);
	643
	644	if (IS_ERR(*table))
	645	return PTR_ERR(*table);
	646
	647	width = _get_divider_width(node, table, *div_flags);
	648
	649	return 0;
	650	}
	651
	652	/**
	653	* of_ti_divider_clk_setup - Setup function for simple div rate clock
	654	* @node: device node for this clock
	655	*
	656	* Sets up a basic divider clock.
	657	*/
	658	static void __init of_ti_divider_clk_setup(struct device_node *node)
	659	{
	660	struct clk *clk;
	661	const char *parent_name;
6c0afb50	662	struct clk_omap_reg reg;
b4761198 TK	663	u8 clk_divider_flags = 0;
	664	u8 width = 0;
	665	u8 shift = 0;
b44a0300	666	s8 latch = -EINVAL;
b4761198 TK	667	const struct clk_div_table *table = NULL;
	668	u32 flags = 0;
	669
	670	parent_name = of_clk_get_parent_name(node, 0);
	671
	672	if (ti_clk_divider_populate(node, &reg, &table, &flags,
b44a0300	673	&clk_divider_flags, &width, &shift, &latch))
b4761198 TK	674	goto cleanup;
b4761198 TK	675
6c0afb50	676	clk = _register_divider(NULL, node->name, parent_name, flags, &reg,
b44a0300	677	shift, width, latch, clk_divider_flags, table);
b4761198 TK	678
	679	if (!IS_ERR(clk)) {
	680	of_clk_add_provider(node, of_clk_src_simple_get, clk);
	681	of_ti_clk_autoidle_setup(node);
	682	return;
	683	}
	684
	685	cleanup:
	686	kfree(table);
	687	}
	688	CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
	689
	690	static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
	691	{
6dbde947	692	struct clk_omap_divider *div;
b4761198 TK	693	u32 val;
	694
	695	div = kzalloc(sizeof(*div), GFP_KERNEL);
	696	if (!div)
	697	return;
	698
	699	if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
b44a0300 TK	700	&div->flags, &div->width, &div->shift,
b44a0300 TK	701	NULL) < 0)
b4761198 TK	702	goto cleanup;
	703
	704	if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
	705	return;
	706
	707	cleanup:
	708	kfree(div->table);
	709	kfree(div);
	710	}
	711	CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
	712	of_ti_composite_divider_clk_setup);