[mirror_ubuntu-jammy-kernel.git] / drivers / clk / ti / gate.c

/*
 * OMAP gate clock support
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>

#include "clock.h"

#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__

static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);

static const struct clk_ops omap_gate_clkdm_clk_ops = {
	.init		= &omap2_init_clk_clkdm,
	.enable		= &omap2_clkops_enable_clkdm,
	.disable	= &omap2_clkops_disable_clkdm,
	.restore_context = clk_gate_restore_context,
};

const struct clk_ops omap_gate_clk_ops = {
	.init		= &omap2_init_clk_clkdm,
	.enable		= &omap2_dflt_clk_enable,
	.disable	= &omap2_dflt_clk_disable,
	.is_enabled	= &omap2_dflt_clk_is_enabled,
	.restore_context = clk_gate_restore_context,
};

static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
	.init		= &omap2_init_clk_clkdm,
	.enable		= &omap36xx_gate_clk_enable_with_hsdiv_restore,
	.disable	= &omap2_dflt_clk_disable,
	.is_enabled	= &omap2_dflt_clk_is_enabled,
	.restore_context = clk_gate_restore_context,
};

/**
 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
 *         from HSDivider PWRDN problem Implements Errata ID: i556.
 * @clk: DPLL output struct clk
 *
 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
 * valueafter their respective PWRDN bits are set.  Any dummy write
 * (Any other value different from the Read value) to the
 * corresponding CM_CLKSEL register will refresh the dividers.
 */
static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
{
	struct clk_omap_divider *parent;
	struct clk_hw *parent_hw;
	u32 dummy_v, orig_v;
	int ret;

	/* Clear PWRDN bit of HSDIVIDER */
	ret = omap2_dflt_clk_enable(hw);

	/* Parent is the x2 node, get parent of parent for the m2 div */
	parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
	parent = to_clk_omap_divider(parent_hw);

	/* Restore the dividers */
	if (!ret) {
		orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
		dummy_v = orig_v;

		/* Write any other value different from the Read value */
		dummy_v ^= (1 << parent->shift);
		ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);

		/* Write the original divider */
		ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
	}

	return ret;
}

static struct clk *_register_gate(struct device *dev, const char *name,
				  const char *parent_name, unsigned long flags,
				  struct clk_omap_reg *reg, u8 bit_idx,
				  u8 clk_gate_flags, const struct clk_ops *ops,
				  const struct clk_hw_omap_ops *hw_ops)
{
	struct clk_init_data init = { NULL };
	struct clk_hw_omap *clk_hw;
	struct clk *clk;

	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	if (!clk_hw)
		return ERR_PTR(-ENOMEM);

	clk_hw->hw.init = &init;

	init.name = name;
	init.ops = ops;

	memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
	clk_hw->enable_bit = bit_idx;
	clk_hw->ops = hw_ops;

	clk_hw->flags = clk_gate_flags;

	init.parent_names = &parent_name;
	init.num_parents = 1;

	init.flags = flags;

	clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);

	if (IS_ERR(clk))
		kfree(clk_hw);

	return clk;
}

static void __init _of_ti_gate_clk_setup(struct device_node *node,
					 const struct clk_ops *ops,
					 const struct clk_hw_omap_ops *hw_ops)
{
	struct clk *clk;
	const char *parent_name;
	struct clk_omap_reg reg;
	u8 enable_bit = 0;
	u32 val;
	u32 flags = 0;
	u8 clk_gate_flags = 0;

	if (ops != &omap_gate_clkdm_clk_ops) {
		if (ti_clk_get_reg_addr(node, 0, &reg))
			return;

		if (!of_property_read_u32(node, "ti,bit-shift", &val))
			enable_bit = val;
	}

	if (of_clk_get_parent_count(node) != 1) {
		pr_err("%pOFn must have 1 parent\n", node);
		return;
	}

	parent_name = of_clk_get_parent_name(node, 0);

	if (of_property_read_bool(node, "ti,set-rate-parent"))
		flags |= CLK_SET_RATE_PARENT;

	if (of_property_read_bool(node, "ti,set-bit-to-disable"))
		clk_gate_flags |= INVERT_ENABLE;

	clk = _register_gate(NULL, node->name, parent_name, flags, &reg,
			     enable_bit, clk_gate_flags, ops, hw_ops);

	if (!IS_ERR(clk))
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
}

static void __init
_of_ti_composite_gate_clk_setup(struct device_node *node,
				const struct clk_hw_omap_ops *hw_ops)
{
	struct clk_hw_omap *gate;
	u32 val = 0;

	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	if (!gate)
		return;

	if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
		goto cleanup;

	of_property_read_u32(node, "ti,bit-shift", &val);

	gate->enable_bit = val;
	gate->ops = hw_ops;

	if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
		return;

cleanup:
	kfree(gate);
}

static void __init
of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
{
	_of_ti_composite_gate_clk_setup(node, NULL);
}
CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
	       of_ti_composite_no_wait_gate_clk_setup);

#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
{
	_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
}
CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
	       of_ti_composite_interface_clk_setup);
#endif

static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
{
	_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
}
CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
	       of_ti_composite_gate_clk_setup);


static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
}
CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
	       of_ti_clkdm_gate_clk_setup);

static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
			      &clkhwops_wait);
}
CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
	       of_ti_hsdiv_gate_clk_setup);

static void __init of_ti_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
}
CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);

static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
}
CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
	       of_ti_wait_gate_clk_setup);

#ifdef CONFIG_ARCH_OMAP3
static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
			      &clkhwops_am35xx_ipss_module_wait);
}
CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
	       of_ti_am35xx_gate_clk_setup);

static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
			      &clkhwops_omap3430es2_dss_usbhost_wait);
}
CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
	       of_ti_dss_gate_clk_setup);
#endif
Commit	Line	Data
f60b1ea5 TK	1	/*
	2	* OMAP gate clock support
	3	*
	4	* Copyright (C) 2013 Texas Instruments, Inc.
	5	*
	6	* Tero Kristo <t-kristo@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/clk-provider.h>
	19	#include <linux/slab.h>
	20	#include <linux/io.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/clk/ti.h>
	24
f187616b TK	25	#include "clock.h"
f187616b TK	26
f60b1ea5 TK	27	#undef pr_fmt
	28	#define pr_fmt(fmt) "%s: " fmt, __func__
	29
	30	static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
	31
	32	static const struct clk_ops omap_gate_clkdm_clk_ops = {
	33	.init = &omap2_init_clk_clkdm,
	34	.enable = &omap2_clkops_enable_clkdm,
	35	.disable = &omap2_clkops_disable_clkdm,
d6e7bbc1	36	.restore_context = clk_gate_restore_context,
f60b1ea5 TK	37	};
f60b1ea5 TK	38
9a00fa68	39	const struct clk_ops omap_gate_clk_ops = {
f60b1ea5 TK	40	.init = &omap2_init_clk_clkdm,
	41	.enable = &omap2_dflt_clk_enable,
	42	.disable = &omap2_dflt_clk_disable,
	43	.is_enabled = &omap2_dflt_clk_is_enabled,
d6e7bbc1	44	.restore_context = clk_gate_restore_context,
f60b1ea5 TK	45	};
	46
	47	static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
	48	.init = &omap2_init_clk_clkdm,
	49	.enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
	50	.disable = &omap2_dflt_clk_disable,
	51	.is_enabled = &omap2_dflt_clk_is_enabled,
d6e7bbc1	52	.restore_context = clk_gate_restore_context,
f60b1ea5 TK	53	};
	54
	55	/**
	56	* omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
	57	* from HSDivider PWRDN problem Implements Errata ID: i556.
	58	* @clk: DPLL output struct clk
	59	*
	60	* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
	61	* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
	62	* valueafter their respective PWRDN bits are set. Any dummy write
	63	* (Any other value different from the Read value) to the
	64	* corresponding CM_CLKSEL register will refresh the dividers.
	65	*/
a53ad8ef	66	static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
f60b1ea5	67	{
6dbde947	68	struct clk_omap_divider *parent;
f60b1ea5 TK	69	struct clk_hw *parent_hw;
	70	u32 dummy_v, orig_v;
	71	int ret;
	72
	73	/* Clear PWRDN bit of HSDIVIDER */
a53ad8ef	74	ret = omap2_dflt_clk_enable(hw);
f60b1ea5 TK	75
f60b1ea5 TK	76	/* Parent is the x2 node, get parent of parent for the m2 div */
a53ad8ef	77	parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
6dbde947	78	parent = to_clk_omap_divider(parent_hw);
f60b1ea5 TK	79
	80	/* Restore the dividers */
	81	if (!ret) {
6c0afb50	82	orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
f60b1ea5 TK	83	dummy_v = orig_v;
	84
	85	/* Write any other value different from the Read value */
	86	dummy_v ^= (1 << parent->shift);
6c0afb50	87	ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
f60b1ea5 TK	88
f60b1ea5 TK	89	/* Write the original divider */
6c0afb50	90	ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
f60b1ea5 TK	91	}
	92
	93	return ret;
	94	}
	95
f187616b TK	96	static struct clk _register_gate(struct device dev, const char *name,
f187616b TK	97	const char *parent_name, unsigned long flags,
6c0afb50	98	struct clk_omap_reg *reg, u8 bit_idx,
f187616b TK	99	u8 clk_gate_flags, const struct clk_ops *ops,
f187616b TK	100	const struct clk_hw_omap_ops *hw_ops)
f60b1ea5	101	{
f60b1ea5 TK	102	struct clk_init_data init = { NULL };
f60b1ea5 TK	103	struct clk_hw_omap *clk_hw;
f187616b	104	struct clk *clk;
f60b1ea5 TK	105
	106	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	107	if (!clk_hw)
f187616b	108	return ERR_PTR(-ENOMEM);
f60b1ea5 TK	109
	110	clk_hw->hw.init = &init;
	111
f187616b	112	init.name = name;
f60b1ea5 TK	113	init.ops = ops;
f60b1ea5 TK	114
6c0afb50	115	memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
f187616b TK	116	clk_hw->enable_bit = bit_idx;
f187616b TK	117	clk_hw->ops = hw_ops;
f60b1ea5	118
c91f0780	119	clk_hw->flags = clk_gate_flags;
f187616b TK	120
	121	init.parent_names = &parent_name;
	122	init.num_parents = 1;
	123
	124	init.flags = flags;
	125
ead47825	126	clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
f187616b TK	127
	128	if (IS_ERR(clk))
	129	kfree(clk_hw);
	130
	131	return clk;
	132	}
	133
f187616b TK	134	static void __init _of_ti_gate_clk_setup(struct device_node *node,
	135	const struct clk_ops *ops,
	136	const struct clk_hw_omap_ops *hw_ops)
	137	{
	138	struct clk *clk;
	139	const char *parent_name;
6c0afb50	140	struct clk_omap_reg reg;
f187616b TK	141	u8 enable_bit = 0;
	142	u32 val;
	143	u32 flags = 0;
	144	u8 clk_gate_flags = 0;
	145
	146	if (ops != &omap_gate_clkdm_clk_ops) {
6c0afb50	147	if (ti_clk_get_reg_addr(node, 0, &reg))
f187616b TK	148	return;
	149
	150	if (!of_property_read_u32(node, "ti,bit-shift", &val))
	151	enable_bit = val;
	152	}
f60b1ea5 TK	153
f60b1ea5 TK	154	if (of_clk_get_parent_count(node) != 1) {
e665f029	155	pr_err("%pOFn must have 1 parent\n", node);
f187616b	156	return;
f60b1ea5 TK	157	}
	158
	159	parent_name = of_clk_get_parent_name(node, 0);
f60b1ea5 TK	160
f60b1ea5 TK	161	if (of_property_read_bool(node, "ti,set-rate-parent"))
f187616b	162	flags \|= CLK_SET_RATE_PARENT;
f60b1ea5 TK	163
f60b1ea5 TK	164	if (of_property_read_bool(node, "ti,set-bit-to-disable"))
f187616b	165	clk_gate_flags \|= INVERT_ENABLE;
f60b1ea5	166
6c0afb50	167	clk = _register_gate(NULL, node->name, parent_name, flags, &reg,
f187616b	168	enable_bit, clk_gate_flags, ops, hw_ops);
f60b1ea5	169
f187616b	170	if (!IS_ERR(clk))
f60b1ea5	171	of_clk_add_provider(node, of_clk_src_simple_get, clk);
f60b1ea5 TK	172	}
	173
	174	static void __init
	175	_of_ti_composite_gate_clk_setup(struct device_node *node,
	176	const struct clk_hw_omap_ops *hw_ops)
	177	{
	178	struct clk_hw_omap *gate;
	179	u32 val = 0;
	180
	181	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	182	if (!gate)
	183	return;
	184
6c0afb50	185	if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
f60b1ea5 TK	186	goto cleanup;
	187
	188	of_property_read_u32(node, "ti,bit-shift", &val);
	189
	190	gate->enable_bit = val;
	191	gate->ops = hw_ops;
f60b1ea5 TK	192
	193	if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
	194	return;
	195
	196	cleanup:
	197	kfree(gate);
	198	}
	199
	200	static void __init
	201	of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
	202	{
	203	_of_ti_composite_gate_clk_setup(node, NULL);
	204	}
	205	CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
	206	of_ti_composite_no_wait_gate_clk_setup);
	207
b3654d70	208	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
f60b1ea5 TK	209	static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
	210	{
	211	_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
	212	}
	213	CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
	214	of_ti_composite_interface_clk_setup);
	215	#endif
	216
	217	static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
	218	{
	219	_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
	220	}
	221	CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
	222	of_ti_composite_gate_clk_setup);
	223
	224
	225	static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
	226	{
	227	_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
	228	}
	229	CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
	230	of_ti_clkdm_gate_clk_setup);
	231
	232	static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
	233	{
	234	_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
	235	&clkhwops_wait);
	236	}
	237	CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
	238	of_ti_hsdiv_gate_clk_setup);
	239
	240	static void __init of_ti_gate_clk_setup(struct device_node *node)
	241	{
	242	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
	243	}
826d8958	244	CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
f60b1ea5 TK	245
	246	static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
	247	{
	248	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
	249	}
	250	CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
	251	of_ti_wait_gate_clk_setup);
	252
	253	#ifdef CONFIG_ARCH_OMAP3
	254	static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
	255	{
	256	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
	257	&clkhwops_am35xx_ipss_module_wait);
	258	}
	259	CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
	260	of_ti_am35xx_gate_clk_setup);
	261
	262	static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
	263	{
	264	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
	265	&clkhwops_omap3430es2_dss_usbhost_wait);
	266	}
	267	CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
	268	of_ti_dss_gate_clk_setup);
	269	#endif