[mirror_ubuntu-jammy-kernel.git] / drivers / clk / ti / gate.c

/*
 * OMAP gate clock support
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>

#include "clock.h"

#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__

static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);

static const struct clk_ops omap_gate_clkdm_clk_ops = {
	.init		= &omap2_init_clk_clkdm,
	.enable		= &omap2_clkops_enable_clkdm,
	.disable	= &omap2_clkops_disable_clkdm,
};

const struct clk_ops omap_gate_clk_ops = {
	.init		= &omap2_init_clk_clkdm,
	.enable		= &omap2_dflt_clk_enable,
	.disable	= &omap2_dflt_clk_disable,
	.is_enabled	= &omap2_dflt_clk_is_enabled,
};

static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
	.init		= &omap2_init_clk_clkdm,
	.enable		= &omap36xx_gate_clk_enable_with_hsdiv_restore,
	.disable	= &omap2_dflt_clk_disable,
	.is_enabled	= &omap2_dflt_clk_is_enabled,
};

/**
 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
 *         from HSDivider PWRDN problem Implements Errata ID: i556.
 * @clk: DPLL output struct clk
 *
 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
 * valueafter their respective PWRDN bits are set.  Any dummy write
 * (Any other value different from the Read value) to the
 * corresponding CM_CLKSEL register will refresh the dividers.
 */
static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
{
	struct clk_omap_divider *parent;
	struct clk_hw *parent_hw;
	u32 dummy_v, orig_v;
	int ret;

	/* Clear PWRDN bit of HSDIVIDER */
	ret = omap2_dflt_clk_enable(hw);

	/* Parent is the x2 node, get parent of parent for the m2 div */
	parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
	parent = to_clk_omap_divider(parent_hw);

	/* Restore the dividers */
	if (!ret) {
		orig_v = ti_clk_ll_ops->clk_readl(parent->reg);
		dummy_v = orig_v;

		/* Write any other value different from the Read value */
		dummy_v ^= (1 << parent->shift);
		ti_clk_ll_ops->clk_writel(dummy_v, parent->reg);

		/* Write the original divider */
		ti_clk_ll_ops->clk_writel(orig_v, parent->reg);
	}

	return ret;
}

static struct clk *_register_gate(struct device *dev, const char *name,
				  const char *parent_name, unsigned long flags,
				  void __iomem *reg, u8 bit_idx,
				  u8 clk_gate_flags, const struct clk_ops *ops,
				  const struct clk_hw_omap_ops *hw_ops)
{
	struct clk_init_data init = { NULL };
	struct clk_hw_omap *clk_hw;
	struct clk *clk;

	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	if (!clk_hw)
		return ERR_PTR(-ENOMEM);

	clk_hw->hw.init = &init;

	init.name = name;
	init.ops = ops;

	clk_hw->enable_reg = reg;
	clk_hw->enable_bit = bit_idx;
	clk_hw->ops = hw_ops;

	clk_hw->flags = clk_gate_flags;

	init.parent_names = &parent_name;
	init.num_parents = 1;

	init.flags = flags;

	clk = ti_clk_register(NULL, &clk_hw->hw, name);

	if (IS_ERR(clk))
		kfree(clk_hw);

	return clk;
}

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
struct clk *ti_clk_register_gate(struct ti_clk *setup)
{
	const struct clk_ops *ops = &omap_gate_clk_ops;
	const struct clk_hw_omap_ops *hw_ops = NULL;
	u32 reg;
	struct clk_omap_reg *reg_setup;
	u32 flags = 0;
	u8 clk_gate_flags = 0;
	struct ti_clk_gate *gate;

	gate = setup->data;

	if (gate->flags & CLKF_INTERFACE)
		return ti_clk_register_interface(setup);

	reg_setup = (struct clk_omap_reg *)&reg;

	if (gate->flags & CLKF_SET_RATE_PARENT)
		flags |= CLK_SET_RATE_PARENT;

	if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
		clk_gate_flags |= INVERT_ENABLE;

	if (gate->flags & CLKF_HSDIV) {
		ops = &omap_gate_clk_hsdiv_restore_ops;
		hw_ops = &clkhwops_wait;
	}

	if (gate->flags & CLKF_DSS)
		hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;

	if (gate->flags & CLKF_WAIT)
		hw_ops = &clkhwops_wait;

	if (gate->flags & CLKF_CLKDM)
		ops = &omap_gate_clkdm_clk_ops;

	if (gate->flags & CLKF_AM35XX)
		hw_ops = &clkhwops_am35xx_ipss_module_wait;

	reg_setup->index = gate->module;
	reg_setup->offset = gate->reg;

	return _register_gate(NULL, setup->name, gate->parent, flags,
			      (void __iomem *)reg, gate->bit_shift,
			      clk_gate_flags, ops, hw_ops);
}

struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
{
	struct clk_hw_omap *gate;
	struct clk_omap_reg *reg;
	const struct clk_hw_omap_ops *ops = &clkhwops_wait;

	if (!setup)
		return NULL;

	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	if (!gate)
		return ERR_PTR(-ENOMEM);

	reg = (struct clk_omap_reg *)&gate->enable_reg;
	reg->index = setup->module;
	reg->offset = setup->reg;

	gate->enable_bit = setup->bit_shift;

	if (setup->flags & CLKF_NO_WAIT)
		ops = NULL;

	if (setup->flags & CLKF_INTERFACE)
		ops = &clkhwops_iclk_wait;

	gate->ops = ops;

	return &gate->hw;
}
#endif

static void __init _of_ti_gate_clk_setup(struct device_node *node,
					 const struct clk_ops *ops,
					 const struct clk_hw_omap_ops *hw_ops)
{
	struct clk *clk;
	const char *parent_name;
	void __iomem *reg = NULL;
	u8 enable_bit = 0;
	u32 val;
	u32 flags = 0;
	u8 clk_gate_flags = 0;

	if (ops != &omap_gate_clkdm_clk_ops) {
		reg = ti_clk_get_reg_addr(node, 0);
		if (IS_ERR(reg))
			return;

		if (!of_property_read_u32(node, "ti,bit-shift", &val))
			enable_bit = val;
	}

	if (of_clk_get_parent_count(node) != 1) {
		pr_err("%s must have 1 parent\n", node->name);
		return;
	}

	parent_name = of_clk_get_parent_name(node, 0);

	if (of_property_read_bool(node, "ti,set-rate-parent"))
		flags |= CLK_SET_RATE_PARENT;

	if (of_property_read_bool(node, "ti,set-bit-to-disable"))
		clk_gate_flags |= INVERT_ENABLE;

	clk = _register_gate(NULL, node->name, parent_name, flags, reg,
			     enable_bit, clk_gate_flags, ops, hw_ops);

	if (!IS_ERR(clk))
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
}

static void __init
_of_ti_composite_gate_clk_setup(struct device_node *node,
				const struct clk_hw_omap_ops *hw_ops)
{
	struct clk_hw_omap *gate;
	u32 val = 0;

	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	if (!gate)
		return;

	gate->enable_reg = ti_clk_get_reg_addr(node, 0);
	if (IS_ERR(gate->enable_reg))
		goto cleanup;

	of_property_read_u32(node, "ti,bit-shift", &val);

	gate->enable_bit = val;
	gate->ops = hw_ops;

	if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
		return;

cleanup:
	kfree(gate);
}

static void __init
of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
{
	_of_ti_composite_gate_clk_setup(node, NULL);
}
CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
	       of_ti_composite_no_wait_gate_clk_setup);

#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
{
	_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
}
CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
	       of_ti_composite_interface_clk_setup);
#endif

static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
{
	_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
}
CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
	       of_ti_composite_gate_clk_setup);


static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
}
CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
	       of_ti_clkdm_gate_clk_setup);

static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
			      &clkhwops_wait);
}
CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
	       of_ti_hsdiv_gate_clk_setup);

static void __init of_ti_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
}
CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);

static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
}
CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
	       of_ti_wait_gate_clk_setup);

#ifdef CONFIG_ARCH_OMAP3
static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
			      &clkhwops_am35xx_ipss_module_wait);
}
CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
	       of_ti_am35xx_gate_clk_setup);

static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
{
	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
			      &clkhwops_omap3430es2_dss_usbhost_wait);
}
CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
	       of_ti_dss_gate_clk_setup);
#endif
Commit	Line	Data
f60b1ea5 TK	1	/*
	2	* OMAP gate clock support
	3	*
	4	* Copyright (C) 2013 Texas Instruments, Inc.
	5	*
	6	* Tero Kristo <t-kristo@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/clk-provider.h>
	19	#include <linux/slab.h>
	20	#include <linux/io.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/clk/ti.h>
	24
f187616b TK	25	#include "clock.h"
f187616b TK	26
f60b1ea5 TK	27	#undef pr_fmt
	28	#define pr_fmt(fmt) "%s: " fmt, __func__
	29
	30	static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
	31
	32	static const struct clk_ops omap_gate_clkdm_clk_ops = {
	33	.init = &omap2_init_clk_clkdm,
	34	.enable = &omap2_clkops_enable_clkdm,
	35	.disable = &omap2_clkops_disable_clkdm,
	36	};
	37
9a00fa68	38	const struct clk_ops omap_gate_clk_ops = {
f60b1ea5 TK	39	.init = &omap2_init_clk_clkdm,
	40	.enable = &omap2_dflt_clk_enable,
	41	.disable = &omap2_dflt_clk_disable,
	42	.is_enabled = &omap2_dflt_clk_is_enabled,
	43	};
	44
	45	static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
	46	.init = &omap2_init_clk_clkdm,
	47	.enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
	48	.disable = &omap2_dflt_clk_disable,
	49	.is_enabled = &omap2_dflt_clk_is_enabled,
	50	};
	51
	52	/**
	53	* omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
	54	* from HSDivider PWRDN problem Implements Errata ID: i556.
	55	* @clk: DPLL output struct clk
	56	*
	57	* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
	58	* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
	59	* valueafter their respective PWRDN bits are set. Any dummy write
	60	* (Any other value different from the Read value) to the
	61	* corresponding CM_CLKSEL register will refresh the dividers.
	62	*/
a53ad8ef	63	static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
f60b1ea5	64	{
6dbde947	65	struct clk_omap_divider *parent;
f60b1ea5 TK	66	struct clk_hw *parent_hw;
	67	u32 dummy_v, orig_v;
	68	int ret;
	69
	70	/* Clear PWRDN bit of HSDIVIDER */
a53ad8ef	71	ret = omap2_dflt_clk_enable(hw);
f60b1ea5 TK	72
f60b1ea5 TK	73	/* Parent is the x2 node, get parent of parent for the m2 div */
a53ad8ef	74	parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
6dbde947	75	parent = to_clk_omap_divider(parent_hw);
f60b1ea5 TK	76
	77	/* Restore the dividers */
	78	if (!ret) {
	79	orig_v = ti_clk_ll_ops->clk_readl(parent->reg);
	80	dummy_v = orig_v;
	81
	82	/* Write any other value different from the Read value */
	83	dummy_v ^= (1 << parent->shift);
	84	ti_clk_ll_ops->clk_writel(dummy_v, parent->reg);
	85
	86	/* Write the original divider */
	87	ti_clk_ll_ops->clk_writel(orig_v, parent->reg);
	88	}
	89
	90	return ret;
	91	}
	92
f187616b TK	93	static struct clk _register_gate(struct device dev, const char *name,
	94	const char *parent_name, unsigned long flags,
	95	void __iomem *reg, u8 bit_idx,
	96	u8 clk_gate_flags, const struct clk_ops *ops,
	97	const struct clk_hw_omap_ops *hw_ops)
f60b1ea5	98	{
f60b1ea5 TK	99	struct clk_init_data init = { NULL };
f60b1ea5 TK	100	struct clk_hw_omap *clk_hw;
f187616b	101	struct clk *clk;
f60b1ea5 TK	102
	103	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
	104	if (!clk_hw)
f187616b	105	return ERR_PTR(-ENOMEM);
f60b1ea5 TK	106
	107	clk_hw->hw.init = &init;
	108
f187616b	109	init.name = name;
f60b1ea5 TK	110	init.ops = ops;
f60b1ea5 TK	111
f187616b TK	112	clk_hw->enable_reg = reg;
	113	clk_hw->enable_bit = bit_idx;
	114	clk_hw->ops = hw_ops;
f60b1ea5	115
c91f0780	116	clk_hw->flags = clk_gate_flags;
f187616b TK	117
	118	init.parent_names = &parent_name;
	119	init.num_parents = 1;
	120
	121	init.flags = flags;
	122
1ae79c46	123	clk = ti_clk_register(NULL, &clk_hw->hw, name);
f187616b TK	124
	125	if (IS_ERR(clk))
	126	kfree(clk_hw);
	127
	128	return clk;
	129	}
	130
6793a30a	131	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
f187616b TK	132	struct clk ti_clk_register_gate(struct ti_clk setup)
	133	{
	134	const struct clk_ops *ops = &omap_gate_clk_ops;
	135	const struct clk_hw_omap_ops *hw_ops = NULL;
	136	u32 reg;
	137	struct clk_omap_reg *reg_setup;
	138	u32 flags = 0;
	139	u8 clk_gate_flags = 0;
	140	struct ti_clk_gate *gate;
	141
	142	gate = setup->data;
	143
06524fa4 TK	144	if (gate->flags & CLKF_INTERFACE)
	145	return ti_clk_register_interface(setup);
	146
f187616b TK	147	reg_setup = (struct clk_omap_reg *)®
	148
	149	if (gate->flags & CLKF_SET_RATE_PARENT)
	150	flags \|= CLK_SET_RATE_PARENT;
	151
	152	if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
	153	clk_gate_flags \|= INVERT_ENABLE;
	154
	155	if (gate->flags & CLKF_HSDIV) {
	156	ops = &omap_gate_clk_hsdiv_restore_ops;
	157	hw_ops = &clkhwops_wait;
f60b1ea5 TK	158	}
f60b1ea5 TK	159
f187616b TK	160	if (gate->flags & CLKF_DSS)
	161	hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
	162
	163	if (gate->flags & CLKF_WAIT)
	164	hw_ops = &clkhwops_wait;
	165
	166	if (gate->flags & CLKF_CLKDM)
	167	ops = &omap_gate_clkdm_clk_ops;
	168
	169	if (gate->flags & CLKF_AM35XX)
	170	hw_ops = &clkhwops_am35xx_ipss_module_wait;
f60b1ea5	171
f187616b TK	172	reg_setup->index = gate->module;
	173	reg_setup->offset = gate->reg;
	174
	175	return _register_gate(NULL, setup->name, gate->parent, flags,
	176	(void __iomem *)reg, gate->bit_shift,
	177	clk_gate_flags, ops, hw_ops);
	178	}
	179
	180	struct clk_hw ti_clk_build_component_gate(struct ti_clk_gate setup)
	181	{
	182	struct clk_hw_omap *gate;
	183	struct clk_omap_reg *reg;
	184	const struct clk_hw_omap_ops *ops = &clkhwops_wait;
	185
	186	if (!setup)
	187	return NULL;
	188
	189	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	190	if (!gate)
	191	return ERR_PTR(-ENOMEM);
	192
	193	reg = (struct clk_omap_reg *)&gate->enable_reg;
	194	reg->index = setup->module;
	195	reg->offset = setup->reg;
	196
	197	gate->enable_bit = setup->bit_shift;
	198
	199	if (setup->flags & CLKF_NO_WAIT)
	200	ops = NULL;
	201
	202	if (setup->flags & CLKF_INTERFACE)
	203	ops = &clkhwops_iclk_wait;
	204
	205	gate->ops = ops;
f187616b TK	206
	207	return &gate->hw;
	208	}
6793a30a	209	#endif
f187616b TK	210
	211	static void __init _of_ti_gate_clk_setup(struct device_node *node,
	212	const struct clk_ops *ops,
	213	const struct clk_hw_omap_ops *hw_ops)
	214	{
	215	struct clk *clk;
	216	const char *parent_name;
	217	void __iomem *reg = NULL;
	218	u8 enable_bit = 0;
	219	u32 val;
	220	u32 flags = 0;
	221	u8 clk_gate_flags = 0;
	222
	223	if (ops != &omap_gate_clkdm_clk_ops) {
	224	reg = ti_clk_get_reg_addr(node, 0);
c807dbed	225	if (IS_ERR(reg))
f187616b TK	226	return;
	227
	228	if (!of_property_read_u32(node, "ti,bit-shift", &val))
	229	enable_bit = val;
	230	}
f60b1ea5 TK	231
f60b1ea5 TK	232	if (of_clk_get_parent_count(node) != 1) {
f187616b TK	233	pr_err("%s must have 1 parent\n", node->name);
f187616b TK	234	return;
f60b1ea5 TK	235	}
	236
	237	parent_name = of_clk_get_parent_name(node, 0);
f60b1ea5 TK	238
f60b1ea5 TK	239	if (of_property_read_bool(node, "ti,set-rate-parent"))
f187616b	240	flags \|= CLK_SET_RATE_PARENT;
f60b1ea5 TK	241
f60b1ea5 TK	242	if (of_property_read_bool(node, "ti,set-bit-to-disable"))
f187616b	243	clk_gate_flags \|= INVERT_ENABLE;
f60b1ea5	244
f187616b TK	245	clk = _register_gate(NULL, node->name, parent_name, flags, reg,
f187616b TK	246	enable_bit, clk_gate_flags, ops, hw_ops);
f60b1ea5	247
f187616b	248	if (!IS_ERR(clk))
f60b1ea5	249	of_clk_add_provider(node, of_clk_src_simple_get, clk);
f60b1ea5 TK	250	}
	251
	252	static void __init
	253	_of_ti_composite_gate_clk_setup(struct device_node *node,
	254	const struct clk_hw_omap_ops *hw_ops)
	255	{
	256	struct clk_hw_omap *gate;
	257	u32 val = 0;
	258
	259	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
	260	if (!gate)
	261	return;
	262
	263	gate->enable_reg = ti_clk_get_reg_addr(node, 0);
c807dbed	264	if (IS_ERR(gate->enable_reg))
f60b1ea5 TK	265	goto cleanup;
	266
	267	of_property_read_u32(node, "ti,bit-shift", &val);
	268
	269	gate->enable_bit = val;
	270	gate->ops = hw_ops;
f60b1ea5 TK	271
	272	if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
	273	return;
	274
	275	cleanup:
	276	kfree(gate);
	277	}
	278
	279	static void __init
	280	of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
	281	{
	282	_of_ti_composite_gate_clk_setup(node, NULL);
	283	}
	284	CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
	285	of_ti_composite_no_wait_gate_clk_setup);
	286
b3654d70	287	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
f60b1ea5 TK	288	static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
	289	{
	290	_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
	291	}
	292	CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
	293	of_ti_composite_interface_clk_setup);
	294	#endif
	295
	296	static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
	297	{
	298	_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
	299	}
	300	CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
	301	of_ti_composite_gate_clk_setup);
	302
	303
	304	static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
	305	{
	306	_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
	307	}
	308	CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
	309	of_ti_clkdm_gate_clk_setup);
	310
	311	static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
	312	{
	313	_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
	314	&clkhwops_wait);
	315	}
	316	CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
	317	of_ti_hsdiv_gate_clk_setup);
	318
	319	static void __init of_ti_gate_clk_setup(struct device_node *node)
	320	{
	321	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
	322	}
826d8958	323	CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
f60b1ea5 TK	324
	325	static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
	326	{
	327	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
	328	}
	329	CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
	330	of_ti_wait_gate_clk_setup);
	331
	332	#ifdef CONFIG_ARCH_OMAP3
	333	static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
	334	{
	335	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
	336	&clkhwops_am35xx_ipss_module_wait);
	337	}
	338	CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
	339	of_ti_am35xx_gate_clk_setup);
	340
	341	static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
	342	{
	343	_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
	344	&clkhwops_omap3430es2_dss_usbhost_wait);
	345	}
	346	CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
	347	of_ti_dss_gate_clk_setup);
	348	#endif