[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / acpi_pm.c

/*
 * linux/drivers/clocksource/acpi_pm.c
 *
 * This file contains the ACPI PM based clocksource.
 *
 * This code was largely moved from the i386 timer_pm.c file
 * which was (C) Dominik Brodowski <linux@brodo.de> 2003
 * and contained the following comments:
 *
 * Driver to use the Power Management Timer (PMTMR) available in some
 * southbridges as primary timing source for the Linux kernel.
 *
 * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
 * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
 *
 * This file is licensed under the GPL v2.
 */

#include <linux/acpi_pmtmr.h>
#include <linux/clocksource.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <asm/io.h>

/*
 * The I/O port the PMTMR resides at.
 * The location is detected during setup_arch(),
 * in arch/i386/kernel/acpi/boot.c
 */
u32 pmtmr_ioport __read_mostly;

static inline u32 read_pmtmr(void)
{
	/* mask the output to 24 bits */
	return inl(pmtmr_ioport) & ACPI_PM_MASK;
}

u32 acpi_pm_read_verified(void)
{
	u32 v1 = 0, v2 = 0, v3 = 0;

	/*
	 * It has been reported that because of various broken
	 * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
	 * source is not latched, you must read it multiple
	 * times to ensure a safe value is read:
	 */
	do {
		v1 = read_pmtmr();
		v2 = read_pmtmr();
		v3 = read_pmtmr();
	} while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
			  || (v3 > v1 && v3 < v2)));

	return v2;
}

static cycle_t acpi_pm_read_slow(void)
{
	return (cycle_t)acpi_pm_read_verified();
}

static cycle_t acpi_pm_read(void)
{
	return (cycle_t)read_pmtmr();
}

static struct clocksource clocksource_acpi_pm = {
	.name		= "acpi_pm",
	.rating		= 200,
	.read		= acpi_pm_read,
	.mask		= (cycle_t)ACPI_PM_MASK,
	.mult		= 0, /*to be calculated*/
	.shift		= 22,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};


#ifdef CONFIG_PCI
static int __devinitdata acpi_pm_good;
static int __init acpi_pm_good_setup(char *__str)
{
	acpi_pm_good = 1;
	return 1;
}
__setup("acpi_pm_good", acpi_pm_good_setup);

static inline void acpi_pm_need_workaround(void)
{
	clocksource_acpi_pm.read = acpi_pm_read_slow;
	clocksource_acpi_pm.rating = 120;
}

/*
 * PIIX4 Errata:
 *
 * The power management timer may return improper results when read.
 * Although the timer value settles properly after incrementing,
 * while incrementing there is a 3 ns window every 69.8 ns where the
 * timer value is indeterminate (a 4.2% chance that the data will be
 * incorrect when read). As a result, the ACPI free running count up
 * timer specification is violated due to erroneous reads.
 */
static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
{
	if (acpi_pm_good)
		return;

	/* the bug has been fixed in PIIX4M */
	if (dev->revision < 3) {
		printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
		       " Due to workarounds for a bug,\n"
		       "* this clock source is slow. Consider trying"
		       " other clock sources\n");

		acpi_pm_need_workaround();
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
			acpi_pm_check_blacklist);

static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
{
	if (acpi_pm_good)
		return;

	printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
	       " workarounds for a bug,\n"
	       "* this clock source is slow. If you are sure your timer"
	       " does not have\n"
	       "* this bug, please use \"acpi_pm_good\" to disable the"
	       " workaround\n");

	acpi_pm_need_workaround();
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
			acpi_pm_check_graylist);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
			acpi_pm_check_graylist);
#endif

#ifndef CONFIG_X86_64
#include "mach_timer.h"
#define PMTMR_EXPECTED_RATE \
  ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
/*
 * Some boards have the PMTMR running way too fast. We check
 * the PMTMR rate against PIT channel 2 to catch these cases.
 */
static int verify_pmtmr_rate(void)
{
	cycle_t value1, value2;
	unsigned long count, delta;

	mach_prepare_counter();
	value1 = clocksource_acpi_pm.read();
	mach_countup(&count);
	value2 = clocksource_acpi_pm.read();
	delta = (value2 - value1) & ACPI_PM_MASK;

	/* Check that the PMTMR delta is within 5% of what we expect */
	if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 ||
	    delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
		printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% "
			"of normal - aborting.\n",
			100UL * delta / PMTMR_EXPECTED_RATE);
		return -1;
	}

	return 0;
}
#else
#define verify_pmtmr_rate() (0)
#endif

/* Number of monotonicity checks to perform during initialization */
#define ACPI_PM_MONOTONICITY_CHECKS 10

static int __init init_acpi_pm_clocksource(void)
{
	cycle_t value1, value2;
	unsigned int i, j, good = 0;

	if (!pmtmr_ioport)
		return -ENODEV;

	clocksource_acpi_pm.mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC,
						clocksource_acpi_pm.shift);

	/* "verify" this timing source: */
	for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
		value1 = clocksource_acpi_pm.read();
		for (i = 0; i < 10000; i++) {
			value2 = clocksource_acpi_pm.read();
			if (value2 == value1)
				continue;
			if (value2 > value1)
				good++;
				break;
			if ((value2 < value1) && ((value2) < 0xFFF))
				good++;
				break;
			printk(KERN_INFO "PM-Timer had inconsistent results:"
			       " 0x%#llx, 0x%#llx - aborting.\n",
			       value1, value2);
			return -EINVAL;
		}
		udelay(300 * i);
	}

	if (good != ACPI_PM_MONOTONICITY_CHECKS) {
		printk(KERN_INFO "PM-Timer failed consistency check "
		       " (0x%#llx) - aborting.\n", value1);
		return -ENODEV;
	}

	if (verify_pmtmr_rate() != 0)
		return -ENODEV;

	return clocksource_register(&clocksource_acpi_pm);
}

/* We use fs_initcall because we want the PCI fixups to have run
 * but we still need to load before device_initcall
 */
fs_initcall(init_acpi_pm_clocksource);

/*
 * Allow an override of the IOPort. Stupid BIOSes do not tell us about
 * the PMTimer, but we might know where it is.
 */
static int __init parse_pmtmr(char *arg)
{
	unsigned long base;

	if (strict_strtoul(arg, 16, &base))
		return -EINVAL;

	printk(KERN_INFO "PMTMR IOPort override: 0x%04x -> 0x%04lx\n",
	       (unsigned int)pmtmr_ioport, base);
	pmtmr_ioport = base;

	return 1;
}
__setup("pmtmr=", parse_pmtmr);
Commit	Line	Data
5d0cf410 JS	1	/*
	2	* linux/drivers/clocksource/acpi_pm.c
	3	*
	4	* This file contains the ACPI PM based clocksource.
	5	*
	6	* This code was largely moved from the i386 timer_pm.c file
	7	* which was (C) Dominik Brodowski <linux@brodo.de> 2003
	8	* and contained the following comments:
	9	*
	10	* Driver to use the Power Management Timer (PMTMR) available in some
	11	* southbridges as primary timing source for the Linux kernel.
	12	*
	13	* Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
	14	* timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
	15	*
	16	* This file is licensed under the GPL v2.
	17	*/
	18
d66bea57	19	#include <linux/acpi_pmtmr.h>
5d0cf410 JS	20	#include <linux/clocksource.h>
	21	#include <linux/errno.h>
	22	#include <linux/init.h>
	23	#include <linux/pci.h>
4ab6a219	24	#include <linux/delay.h>
5d0cf410 JS	25	#include <asm/io.h>
5d0cf410 JS	26
5d0cf410 JS	27	/*
	28	* The I/O port the PMTMR resides at.
	29	* The location is detected during setup_arch(),
8ce8e2f9	30	* in arch/i386/kernel/acpi/boot.c
5d0cf410	31	*/
7d622d47	32	u32 pmtmr_ioport __read_mostly;
5d0cf410	33
5d0cf410 JS	34	static inline u32 read_pmtmr(void)
	35	{
	36	/* mask the output to 24 bits */
	37	return inl(pmtmr_ioport) & ACPI_PM_MASK;
	38	}
	39
d66bea57	40	u32 acpi_pm_read_verified(void)
5d0cf410 JS	41	{
	42	u32 v1 = 0, v2 = 0, v3 = 0;
	43
	44	/*
	45	* It has been reported that because of various broken
	46	* chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
7d622d47	47	* source is not latched, you must read it multiple
5d0cf410 JS	48	* times to ensure a safe value is read:
	49	*/
	50	do {
	51	v1 = read_pmtmr();
	52	v2 = read_pmtmr();
	53	v3 = read_pmtmr();
78f32668 DW	54	} while (unlikely((v1 > v2 && v1 < v3) \|\| (v2 > v3 && v2 < v1)
78f32668 DW	55	\|\| (v3 > v1 && v3 < v2)));
5d0cf410	56
d66bea57 TG	57	return v2;
	58	}
	59
	60	static cycle_t acpi_pm_read_slow(void)
	61	{
	62	return (cycle_t)acpi_pm_read_verified();
5d0cf410 JS	63	}
	64
	65	static cycle_t acpi_pm_read(void)
	66	{
	67	return (cycle_t)read_pmtmr();
	68	}
	69
	70	static struct clocksource clocksource_acpi_pm = {
	71	.name = "acpi_pm",
	72	.rating = 200,
	73	.read = acpi_pm_read,
	74	.mask = (cycle_t)ACPI_PM_MASK,
7b0b8207	75	.mult = 0, /to be calculated/
5d0cf410	76	.shift = 22,
73b08d2a TG	77	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
73b08d2a TG	78
5d0cf410 JS	79	};
	80
	81
	82	#ifdef CONFIG_PCI
f5f1a24a	83	static int __devinitdata acpi_pm_good;
5d0cf410 JS	84	static int __init acpi_pm_good_setup(char *__str)
5d0cf410 JS	85	{
f5f1a24a DW	86	acpi_pm_good = 1;
f5f1a24a DW	87	return 1;
5d0cf410 JS	88	}
	89	__setup("acpi_pm_good", acpi_pm_good_setup);
	90
	91	static inline void acpi_pm_need_workaround(void)
	92	{
d66bea57	93	clocksource_acpi_pm.read = acpi_pm_read_slow;
1ff100d7	94	clocksource_acpi_pm.rating = 120;
5d0cf410 JS	95	}
	96
	97	/*
	98	* PIIX4 Errata:
	99	*
	100	* The power management timer may return improper results when read.
	101	* Although the timer value settles properly after incrementing,
	102	* while incrementing there is a 3 ns window every 69.8 ns where the
	103	* timer value is indeterminate (a 4.2% chance that the data will be
	104	* incorrect when read). As a result, the ACPI free running count up
	105	* timer specification is violated due to erroneous reads.
	106	*/
	107	static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
	108	{
5d0cf410 JS	109	if (acpi_pm_good)
	110	return;
	111
5d0cf410	112	/* the bug has been fixed in PIIX4M */
44c10138	113	if (dev->revision < 3) {
5d0cf410 JS	114	printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
	115	" Due to workarounds for a bug,\n"
	116	"* this clock source is slow. Consider trying"
	117	" other clock sources\n");
	118
	119	acpi_pm_need_workaround();
	120	}
	121	}
	122	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
	123	acpi_pm_check_blacklist);
	124
	125	static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
	126	{
	127	if (acpi_pm_good)
	128	return;
	129
	130	printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
	131	" workarounds for a bug,\n"
	132	"* this clock source is slow. If you are sure your timer"
	133	" does not have\n"
	134	"* this bug, please use \"acpi_pm_good\" to disable the"
	135	" workaround\n");
	136
	137	acpi_pm_need_workaround();
	138	}
	139	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
	140	acpi_pm_check_graylist);
78f32668 DW	141	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
78f32668 DW	142	acpi_pm_check_graylist);
5d0cf410 JS	143	#endif
5d0cf410 JS	144
562f9c57 JS	145	#ifndef CONFIG_X86_64
	146	#include "mach_timer.h"
	147	#define PMTMR_EXPECTED_RATE \
	148	((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
	149	/*
	150	* Some boards have the PMTMR running way too fast. We check
	151	* the PMTMR rate against PIT channel 2 to catch these cases.
	152	*/
	153	static int verify_pmtmr_rate(void)
	154	{
dfdf748a	155	cycle_t value1, value2;
562f9c57 JS	156	unsigned long count, delta;
	157
	158	mach_prepare_counter();
dfdf748a	159	value1 = clocksource_acpi_pm.read();
562f9c57	160	mach_countup(&count);
dfdf748a	161	value2 = clocksource_acpi_pm.read();
562f9c57 JS	162	delta = (value2 - value1) & ACPI_PM_MASK;
	163
	164	/* Check that the PMTMR delta is within 5% of what we expect */
	165	if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 \|\|
	166	delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
	167	printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% "
	168	"of normal - aborting.\n",
	169	100UL * delta / PMTMR_EXPECTED_RATE);
	170	return -1;
	171	}
	172
	173	return 0;
	174	}
	175	#else
	176	#define verify_pmtmr_rate() (0)
	177	#endif
5d0cf410	178
4ab6a219 DB	179	/* Number of monotonicity checks to perform during initialization */
	180	#define ACPI_PM_MONOTONICITY_CHECKS 10
	181
5d0cf410 JS	182	static int __init init_acpi_pm_clocksource(void)
5d0cf410 JS	183	{
dfdf748a	184	cycle_t value1, value2;
4ab6a219	185	unsigned int i, j, good = 0;
5d0cf410 JS	186
	187	if (!pmtmr_ioport)
	188	return -ENODEV;
	189
	190	clocksource_acpi_pm.mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC,
	191	clocksource_acpi_pm.shift);
	192
	193	/* "verify" this timing source: */
4ab6a219 DB	194	for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
	195	value1 = clocksource_acpi_pm.read();
	196	for (i = 0; i < 10000; i++) {
	197	value2 = clocksource_acpi_pm.read();
	198	if (value2 == value1)
	199	continue;
	200	if (value2 > value1)
	201	good++;
	202	break;
	203	if ((value2 < value1) && ((value2) < 0xFFF))
	204	good++;
	205	break;
	206	printk(KERN_INFO "PM-Timer had inconsistent results:"
	207	" 0x%#llx, 0x%#llx - aborting.\n",
	208	value1, value2);
	209	return -EINVAL;
	210	}
	211	udelay(300 * i);
	212	}
	213
	214	if (good != ACPI_PM_MONOTONICITY_CHECKS) {
	215	printk(KERN_INFO "PM-Timer failed consistency check "
	216	" (0x%#llx) - aborting.\n", value1);
	217	return -ENODEV;
5d0cf410	218	}
5d0cf410	219
562f9c57 JS	220	if (verify_pmtmr_rate() != 0)
	221	return -ENODEV;
	222
a2752549	223	return clocksource_register(&clocksource_acpi_pm);
5d0cf410 JS	224	}
5d0cf410 JS	225
6bb74df4 JS	226	/* We use fs_initcall because we want the PCI fixups to have run
	227	* but we still need to load before device_initcall
	228	*/
	229	fs_initcall(init_acpi_pm_clocksource);
6b148507 TG	230
	231	/*
	232	* Allow an override of the IOPort. Stupid BIOSes do not tell us about
	233	* the PMTimer, but we might know where it is.
	234	*/
	235	static int __init parse_pmtmr(char *arg)
	236	{
	237	unsigned long base;
	238
	239	if (strict_strtoul(arg, 16, &base))
	240	return -EINVAL;
	241
14351760	242	printk(KERN_INFO "PMTMR IOPort override: 0x%04x -> 0x%04lx\n",
38032f72	243	(unsigned int)pmtmr_ioport, base);
6b148507 TG	244	pmtmr_ioport = base;
	245
	246	return 1;
	247	}
	248	__setup("pmtmr=", parse_pmtmr);