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d8005e6b | 1 | /* |
c4c9a040 | 2 | * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) |
d8005e6b VG |
3 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
d8005e6b VG |
8 | */ |
9 | ||
c4c9a040 VG |
10 | /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be |
11 | * programmed to go from @count to @limit and optionally interrupt. | |
12 | * We've designated TIMER0 for clockevents and TIMER1 for clocksource | |
d8005e6b | 13 | * |
c4c9a040 VG |
14 | * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP) |
15 | * which are suitable for UP and SMP based clocksources respectively | |
d8005e6b VG |
16 | */ |
17 | ||
d8005e6b | 18 | #include <linux/interrupt.h> |
69fbd098 NC |
19 | #include <linux/clk.h> |
20 | #include <linux/clk-provider.h> | |
d8005e6b VG |
21 | #include <linux/clocksource.h> |
22 | #include <linux/clockchips.h> | |
eec3c58e | 23 | #include <linux/cpu.h> |
77c8d0d6 VG |
24 | #include <linux/of.h> |
25 | #include <linux/of_irq.h> | |
d8005e6b | 26 | |
b26c2e38 | 27 | #include <soc/arc/timers.h> |
2d7f5c48 | 28 | #include <soc/arc/mcip.h> |
72d72880 | 29 | |
d8005e6b | 30 | |
77c8d0d6 VG |
31 | static unsigned long arc_timer_freq; |
32 | ||
33 | static int noinline arc_get_timer_clk(struct device_node *node) | |
34 | { | |
35 | struct clk *clk; | |
36 | int ret; | |
37 | ||
38 | clk = of_clk_get(node, 0); | |
39 | if (IS_ERR(clk)) { | |
40 | pr_err("timer missing clk"); | |
41 | return PTR_ERR(clk); | |
42 | } | |
43 | ||
44 | ret = clk_prepare_enable(clk); | |
45 | if (ret) { | |
46 | pr_err("Couldn't enable parent clk\n"); | |
47 | return ret; | |
48 | } | |
49 | ||
50 | arc_timer_freq = clk_get_rate(clk); | |
51 | ||
52 | return 0; | |
53 | } | |
54 | ||
d8005e6b VG |
55 | /********** Clock Source Device *********/ |
56 | ||
04421420 | 57 | #ifdef CONFIG_ARC_TIMERS_64BIT |
72d72880 | 58 | |
e608b53e | 59 | static cycle_t arc_read_gfrc(struct clocksource *cs) |
72d72880 VG |
60 | { |
61 | unsigned long flags; | |
2cd690ea | 62 | u32 l, h; |
72d72880 VG |
63 | |
64 | local_irq_save(flags); | |
65 | ||
d584f0fb | 66 | __mcip_cmd(CMD_GFRC_READ_LO, 0); |
2cd690ea | 67 | l = read_aux_reg(ARC_REG_MCIP_READBACK); |
72d72880 | 68 | |
d584f0fb | 69 | __mcip_cmd(CMD_GFRC_READ_HI, 0); |
2cd690ea | 70 | h = read_aux_reg(ARC_REG_MCIP_READBACK); |
72d72880 VG |
71 | |
72 | local_irq_restore(flags); | |
73 | ||
2cd690ea | 74 | return (((cycle_t)h) << 32) | l; |
72d72880 VG |
75 | } |
76 | ||
e608b53e | 77 | static struct clocksource arc_counter_gfrc = { |
d584f0fb | 78 | .name = "ARConnect GFRC", |
72d72880 | 79 | .rating = 400, |
e608b53e | 80 | .read = arc_read_gfrc, |
72d72880 VG |
81 | .mask = CLOCKSOURCE_MASK(64), |
82 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
83 | }; | |
84 | ||
43d75604 | 85 | static int __init arc_cs_setup_gfrc(struct device_node *node) |
e608b53e | 86 | { |
ec7cb87b | 87 | struct mcip_bcr mp; |
e608b53e VG |
88 | int ret; |
89 | ||
ec7cb87b VG |
90 | READ_BCR(ARC_REG_MCIP_BCR, mp); |
91 | if (!mp.gfrc) { | |
92 | pr_warn("Global-64-bit-Ctr clocksource not detected"); | |
43d75604 | 93 | return -ENXIO; |
ec7cb87b | 94 | } |
e608b53e VG |
95 | |
96 | ret = arc_get_timer_clk(node); | |
97 | if (ret) | |
43d75604 | 98 | return ret; |
e608b53e | 99 | |
43d75604 | 100 | return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); |
e608b53e | 101 | } |
177cf6e5 | 102 | CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); |
e608b53e | 103 | |
aa93e8ef VG |
104 | #define AUX_RTC_CTRL 0x103 |
105 | #define AUX_RTC_LOW 0x104 | |
106 | #define AUX_RTC_HIGH 0x105 | |
107 | ||
e608b53e | 108 | static cycle_t arc_read_rtc(struct clocksource *cs) |
aa93e8ef VG |
109 | { |
110 | unsigned long status; | |
2cd690ea | 111 | u32 l, h; |
aa93e8ef | 112 | |
922cc171 VG |
113 | /* |
114 | * hardware has an internal state machine which tracks readout of | |
115 | * low/high and updates the CTRL.status if | |
116 | * - interrupt/exception taken between the two reads | |
117 | * - high increments after low has been read | |
118 | */ | |
119 | do { | |
2cd690ea VG |
120 | l = read_aux_reg(AUX_RTC_LOW); |
121 | h = read_aux_reg(AUX_RTC_HIGH); | |
922cc171 VG |
122 | status = read_aux_reg(AUX_RTC_CTRL); |
123 | } while (!(status & _BITUL(31))); | |
aa93e8ef | 124 | |
2cd690ea | 125 | return (((cycle_t)h) << 32) | l; |
aa93e8ef VG |
126 | } |
127 | ||
e608b53e | 128 | static struct clocksource arc_counter_rtc = { |
aa93e8ef VG |
129 | .name = "ARCv2 RTC", |
130 | .rating = 350, | |
e608b53e | 131 | .read = arc_read_rtc, |
aa93e8ef VG |
132 | .mask = CLOCKSOURCE_MASK(64), |
133 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
134 | }; | |
135 | ||
43d75604 | 136 | static int __init arc_cs_setup_rtc(struct device_node *node) |
d8005e6b | 137 | { |
ec7cb87b | 138 | struct bcr_timer timer; |
e608b53e VG |
139 | int ret; |
140 | ||
ec7cb87b VG |
141 | READ_BCR(ARC_REG_TIMERS_BCR, timer); |
142 | if (!timer.rtc) { | |
143 | pr_warn("Local-64-bit-Ctr clocksource not detected"); | |
43d75604 | 144 | return -ENXIO; |
ec7cb87b | 145 | } |
e608b53e VG |
146 | |
147 | /* Local to CPU hence not usable in SMP */ | |
ec7cb87b VG |
148 | if (IS_ENABLED(CONFIG_SMP)) { |
149 | pr_warn("Local-64-bit-Ctr not usable in SMP"); | |
43d75604 | 150 | return -EINVAL; |
ec7cb87b | 151 | } |
e608b53e VG |
152 | |
153 | ret = arc_get_timer_clk(node); | |
154 | if (ret) | |
43d75604 | 155 | return ret; |
d8005e6b | 156 | |
e608b53e VG |
157 | write_aux_reg(AUX_RTC_CTRL, 1); |
158 | ||
43d75604 | 159 | return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); |
d8005e6b | 160 | } |
177cf6e5 | 161 | CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); |
e608b53e VG |
162 | |
163 | #endif | |
d8005e6b | 164 | |
e608b53e VG |
165 | /* |
166 | * 32bit TIMER1 to keep counting monotonically and wraparound | |
167 | */ | |
168 | ||
169 | static cycle_t arc_read_timer1(struct clocksource *cs) | |
d8005e6b VG |
170 | { |
171 | return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); | |
172 | } | |
173 | ||
e608b53e | 174 | static struct clocksource arc_counter_timer1 = { |
d8005e6b VG |
175 | .name = "ARC Timer1", |
176 | .rating = 300, | |
e608b53e | 177 | .read = arc_read_timer1, |
d8005e6b VG |
178 | .mask = CLOCKSOURCE_MASK(32), |
179 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
180 | }; | |
181 | ||
43d75604 | 182 | static int __init arc_cs_setup_timer1(struct device_node *node) |
e608b53e VG |
183 | { |
184 | int ret; | |
185 | ||
186 | /* Local to CPU hence not usable in SMP */ | |
187 | if (IS_ENABLED(CONFIG_SMP)) | |
43d75604 | 188 | return -EINVAL; |
e608b53e VG |
189 | |
190 | ret = arc_get_timer_clk(node); | |
191 | if (ret) | |
43d75604 | 192 | return ret; |
e608b53e | 193 | |
b26c2e38 | 194 | write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); |
e608b53e VG |
195 | write_aux_reg(ARC_REG_TIMER1_CNT, 0); |
196 | write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); | |
197 | ||
43d75604 | 198 | return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); |
e608b53e | 199 | } |
aa93e8ef | 200 | |
d8005e6b VG |
201 | /********** Clock Event Device *********/ |
202 | ||
77c8d0d6 | 203 | static int arc_timer_irq; |
eec3c58e | 204 | |
d8005e6b | 205 | /* |
c9a98e18 | 206 | * Arm the timer to interrupt after @cycles |
d8005e6b VG |
207 | * The distinction for oneshot/periodic is done in arc_event_timer_ack() below |
208 | */ | |
c9a98e18 | 209 | static void arc_timer_event_setup(unsigned int cycles) |
d8005e6b | 210 | { |
c9a98e18 | 211 | write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); |
d8005e6b VG |
212 | write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ |
213 | ||
214 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); | |
215 | } | |
216 | ||
d8005e6b VG |
217 | |
218 | static int arc_clkevent_set_next_event(unsigned long delta, | |
219 | struct clock_event_device *dev) | |
220 | { | |
221 | arc_timer_event_setup(delta); | |
222 | return 0; | |
223 | } | |
224 | ||
aeec6cda | 225 | static int arc_clkevent_set_periodic(struct clock_event_device *dev) |
d8005e6b | 226 | { |
aeec6cda VK |
227 | /* |
228 | * At X Hz, 1 sec = 1000ms -> X cycles; | |
229 | * 10ms -> X / 100 cycles | |
230 | */ | |
77c8d0d6 | 231 | arc_timer_event_setup(arc_timer_freq / HZ); |
aeec6cda | 232 | return 0; |
d8005e6b VG |
233 | } |
234 | ||
235 | static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { | |
aeec6cda VK |
236 | .name = "ARC Timer0", |
237 | .features = CLOCK_EVT_FEAT_ONESHOT | | |
238 | CLOCK_EVT_FEAT_PERIODIC, | |
239 | .rating = 300, | |
aeec6cda VK |
240 | .set_next_event = arc_clkevent_set_next_event, |
241 | .set_state_periodic = arc_clkevent_set_periodic, | |
d8005e6b VG |
242 | }; |
243 | ||
244 | static irqreturn_t timer_irq_handler(int irq, void *dev_id) | |
245 | { | |
f8b34c3f VG |
246 | /* |
247 | * Note that generic IRQ core could have passed @evt for @dev_id if | |
248 | * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() | |
249 | */ | |
250 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); | |
aeec6cda | 251 | int irq_reenable = clockevent_state_periodic(evt); |
f8b34c3f VG |
252 | |
253 | /* | |
254 | * Any write to CTRL reg ACks the interrupt, we rewrite the | |
255 | * Count when [N]ot [H]alted bit. | |
256 | * And re-arm it if perioid by [I]nterrupt [E]nable bit | |
257 | */ | |
258 | write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); | |
259 | ||
260 | evt->event_handler(evt); | |
d8005e6b | 261 | |
d8005e6b VG |
262 | return IRQ_HANDLED; |
263 | } | |
264 | ||
ecd8081f AMG |
265 | |
266 | static int arc_timer_starting_cpu(unsigned int cpu) | |
eec3c58e NC |
267 | { |
268 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); | |
269 | ||
270 | evt->cpumask = cpumask_of(smp_processor_id()); | |
271 | ||
b26c2e38 | 272 | clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); |
ecd8081f AMG |
273 | enable_percpu_irq(arc_timer_irq, 0); |
274 | return 0; | |
eec3c58e NC |
275 | } |
276 | ||
ecd8081f AMG |
277 | static int arc_timer_dying_cpu(unsigned int cpu) |
278 | { | |
279 | disable_percpu_irq(arc_timer_irq); | |
280 | return 0; | |
281 | } | |
eec3c58e | 282 | |
d8005e6b | 283 | /* |
eec3c58e | 284 | * clockevent setup for boot CPU |
d8005e6b | 285 | */ |
43d75604 | 286 | static int __init arc_clockevent_setup(struct device_node *node) |
d8005e6b | 287 | { |
2d4899f6 | 288 | struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); |
eec3c58e | 289 | int ret; |
d8005e6b | 290 | |
77c8d0d6 | 291 | arc_timer_irq = irq_of_parse_and_map(node, 0); |
43d75604 DL |
292 | if (arc_timer_irq <= 0) { |
293 | pr_err("clockevent: missing irq"); | |
294 | return -EINVAL; | |
295 | } | |
77c8d0d6 VG |
296 | |
297 | ret = arc_get_timer_clk(node); | |
43d75604 DL |
298 | if (ret) { |
299 | pr_err("clockevent: missing clk"); | |
300 | return ret; | |
301 | } | |
77c8d0d6 | 302 | |
eec3c58e NC |
303 | /* Needs apriori irq_set_percpu_devid() done in intc map function */ |
304 | ret = request_percpu_irq(arc_timer_irq, timer_irq_handler, | |
305 | "Timer0 (per-cpu-tick)", evt); | |
43d75604 DL |
306 | if (ret) { |
307 | pr_err("clockevent: unable to request irq\n"); | |
308 | return ret; | |
309 | } | |
56957940 | 310 | |
ecd8081f AMG |
311 | ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, |
312 | "AP_ARC_TIMER_STARTING", | |
313 | arc_timer_starting_cpu, | |
314 | arc_timer_dying_cpu); | |
315 | if (ret) { | |
316 | pr_err("Failed to setup hotplug state"); | |
317 | return ret; | |
318 | } | |
43d75604 | 319 | return 0; |
d8005e6b | 320 | } |
e608b53e | 321 | |
43d75604 | 322 | static int __init arc_of_timer_init(struct device_node *np) |
e608b53e VG |
323 | { |
324 | static int init_count = 0; | |
43d75604 | 325 | int ret; |
e608b53e VG |
326 | |
327 | if (!init_count) { | |
328 | init_count = 1; | |
43d75604 | 329 | ret = arc_clockevent_setup(np); |
e608b53e | 330 | } else { |
43d75604 | 331 | ret = arc_cs_setup_timer1(np); |
e608b53e | 332 | } |
43d75604 DL |
333 | |
334 | return ret; | |
e608b53e | 335 | } |
177cf6e5 | 336 | CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); |