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Commit | Line | Data |
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8a4da6e3 MR |
1 | /* |
2 | * linux/drivers/clocksource/arm_arch_timer.c | |
3 | * | |
4 | * Copyright (C) 2011 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
f005bd7e MZ |
11 | |
12 | #define pr_fmt(fmt) "arm_arch_timer: " fmt | |
13 | ||
8a4da6e3 MR |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/cpu.h> | |
346e7480 | 19 | #include <linux/cpu_pm.h> |
8a4da6e3 | 20 | #include <linux/clockchips.h> |
7c8f1e78 | 21 | #include <linux/clocksource.h> |
8a4da6e3 MR |
22 | #include <linux/interrupt.h> |
23 | #include <linux/of_irq.h> | |
22006994 | 24 | #include <linux/of_address.h> |
8a4da6e3 | 25 | #include <linux/io.h> |
22006994 | 26 | #include <linux/slab.h> |
65cd4f6c | 27 | #include <linux/sched_clock.h> |
b09ca1ec | 28 | #include <linux/acpi.h> |
8a4da6e3 MR |
29 | |
30 | #include <asm/arch_timer.h> | |
8266891e | 31 | #include <asm/virt.h> |
8a4da6e3 MR |
32 | |
33 | #include <clocksource/arm_arch_timer.h> | |
34 | ||
3f968fa1 FW |
35 | #undef pr_fmt |
36 | #define pr_fmt(fmt) "arch_timer: " fmt | |
37 | ||
22006994 SB |
38 | #define CNTTIDR 0x08 |
39 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
40 | ||
e392d603 RM |
41 | #define CNTACR(n) (0x40 + ((n) * 4)) |
42 | #define CNTACR_RPCT BIT(0) | |
43 | #define CNTACR_RVCT BIT(1) | |
44 | #define CNTACR_RFRQ BIT(2) | |
45 | #define CNTACR_RVOFF BIT(3) | |
46 | #define CNTACR_RWVT BIT(4) | |
47 | #define CNTACR_RWPT BIT(5) | |
48 | ||
22006994 SB |
49 | #define CNTVCT_LO 0x08 |
50 | #define CNTVCT_HI 0x0c | |
51 | #define CNTFRQ 0x10 | |
52 | #define CNTP_TVAL 0x28 | |
53 | #define CNTP_CTL 0x2c | |
54 | #define CNTV_TVAL 0x38 | |
55 | #define CNTV_CTL 0x3c | |
56 | ||
22006994 SB |
57 | static unsigned arch_timers_present __initdata; |
58 | ||
59 | static void __iomem *arch_counter_base; | |
60 | ||
61 | struct arch_timer { | |
62 | void __iomem *base; | |
63 | struct clock_event_device evt; | |
64 | }; | |
65 | ||
66 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
67 | ||
8a4da6e3 | 68 | static u32 arch_timer_rate; |
5d38740d | 69 | static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI]; |
8a4da6e3 MR |
70 | |
71 | static struct clock_event_device __percpu *arch_timer_evt; | |
72 | ||
5d38740d | 73 | static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI; |
82a56194 | 74 | static bool arch_timer_c3stop; |
22006994 | 75 | static bool arch_timer_mem_use_virtual; |
d8ec7595 | 76 | static bool arch_counter_suspend_stop; |
83f3444f | 77 | static bool vdso_default = true; |
8a4da6e3 | 78 | |
46fd5c6b WD |
79 | static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); |
80 | ||
81 | static int __init early_evtstrm_cfg(char *buf) | |
82 | { | |
83 | return strtobool(buf, &evtstrm_enable); | |
84 | } | |
85 | early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); | |
86 | ||
8a4da6e3 MR |
87 | /* |
88 | * Architected system timer support. | |
89 | */ | |
90 | ||
5271a34c MZ |
91 | static __always_inline |
92 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
93 | struct clock_event_device *clk) | |
94 | { | |
95 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
96 | struct arch_timer *timer = to_arch_timer(clk); | |
97 | switch (reg) { | |
98 | case ARCH_TIMER_REG_CTRL: | |
99 | writel_relaxed(val, timer->base + CNTP_CTL); | |
100 | break; | |
101 | case ARCH_TIMER_REG_TVAL: | |
102 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
103 | break; | |
104 | } | |
105 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
106 | struct arch_timer *timer = to_arch_timer(clk); | |
107 | switch (reg) { | |
108 | case ARCH_TIMER_REG_CTRL: | |
109 | writel_relaxed(val, timer->base + CNTV_CTL); | |
110 | break; | |
111 | case ARCH_TIMER_REG_TVAL: | |
112 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
113 | break; | |
114 | } | |
115 | } else { | |
116 | arch_timer_reg_write_cp15(access, reg, val); | |
117 | } | |
118 | } | |
119 | ||
120 | static __always_inline | |
121 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
122 | struct clock_event_device *clk) | |
123 | { | |
124 | u32 val; | |
125 | ||
126 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
127 | struct arch_timer *timer = to_arch_timer(clk); | |
128 | switch (reg) { | |
129 | case ARCH_TIMER_REG_CTRL: | |
130 | val = readl_relaxed(timer->base + CNTP_CTL); | |
131 | break; | |
132 | case ARCH_TIMER_REG_TVAL: | |
133 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
134 | break; | |
135 | } | |
136 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
137 | struct arch_timer *timer = to_arch_timer(clk); | |
138 | switch (reg) { | |
139 | case ARCH_TIMER_REG_CTRL: | |
140 | val = readl_relaxed(timer->base + CNTV_CTL); | |
141 | break; | |
142 | case ARCH_TIMER_REG_TVAL: | |
143 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
144 | break; | |
145 | } | |
146 | } else { | |
147 | val = arch_timer_reg_read_cp15(access, reg); | |
148 | } | |
149 | ||
150 | return val; | |
151 | } | |
152 | ||
d7765b0c MZ |
153 | /* |
154 | * Default to cp15 based access because arm64 uses this function for | |
155 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
156 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
157 | * if we don't have the cp15 accessors we won't have a problem. | |
158 | */ | |
159 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
160 | ||
161 | static u64 arch_counter_read(struct clocksource *cs) | |
162 | { | |
163 | return arch_timer_read_counter(); | |
164 | } | |
165 | ||
166 | static u64 arch_counter_read_cc(const struct cyclecounter *cc) | |
167 | { | |
168 | return arch_timer_read_counter(); | |
169 | } | |
170 | ||
171 | static struct clocksource clocksource_counter = { | |
172 | .name = "arch_sys_counter", | |
173 | .rating = 400, | |
174 | .read = arch_counter_read, | |
175 | .mask = CLOCKSOURCE_MASK(56), | |
176 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
177 | }; | |
178 | ||
179 | static struct cyclecounter cyclecounter = { | |
180 | .read = arch_counter_read_cc, | |
181 | .mask = CLOCKSOURCE_MASK(56), | |
182 | }; | |
183 | ||
ea36ec17 MZ |
184 | struct ate_acpi_oem_info { |
185 | char oem_id[ACPI_OEM_ID_SIZE + 1]; | |
186 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; | |
187 | u32 oem_revision; | |
188 | }; | |
189 | ||
f6dc1576 | 190 | #ifdef CONFIG_FSL_ERRATUM_A008585 |
70d016c2 DT |
191 | /* |
192 | * The number of retries is an arbitrary value well beyond the highest number | |
193 | * of iterations the loop has been observed to take. | |
194 | */ | |
195 | #define __fsl_a008585_read_reg(reg) ({ \ | |
196 | u64 _old, _new; \ | |
197 | int _retries = 200; \ | |
198 | \ | |
199 | do { \ | |
200 | _old = read_sysreg(reg); \ | |
201 | _new = read_sysreg(reg); \ | |
202 | _retries--; \ | |
203 | } while (unlikely(_old != _new) && _retries); \ | |
204 | \ | |
205 | WARN_ON_ONCE(!_retries); \ | |
206 | _new; \ | |
207 | }) | |
208 | ||
209 | static u32 notrace fsl_a008585_read_cntp_tval_el0(void) | |
f6dc1576 SW |
210 | { |
211 | return __fsl_a008585_read_reg(cntp_tval_el0); | |
212 | } | |
213 | ||
70d016c2 | 214 | static u32 notrace fsl_a008585_read_cntv_tval_el0(void) |
f6dc1576 SW |
215 | { |
216 | return __fsl_a008585_read_reg(cntv_tval_el0); | |
217 | } | |
218 | ||
70d016c2 | 219 | static u64 notrace fsl_a008585_read_cntvct_el0(void) |
f6dc1576 SW |
220 | { |
221 | return __fsl_a008585_read_reg(cntvct_el0); | |
222 | } | |
70d016c2 DT |
223 | #endif |
224 | ||
cc104462 DT |
225 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
226 | /* | |
227 | * Verify whether the value of the second read is larger than the first by | |
228 | * less than 32 is the only way to confirm the value is correct, so clear the | |
229 | * lower 5 bits to check whether the difference is greater than 32 or not. | |
230 | * Theoretically the erratum should not occur more than twice in succession | |
231 | * when reading the system counter, but it is possible that some interrupts | |
232 | * may lead to more than twice read errors, triggering the warning, so setting | |
233 | * the number of retries far beyond the number of iterations the loop has been | |
234 | * observed to take. | |
235 | */ | |
236 | #define __hisi_161010101_read_reg(reg) ({ \ | |
237 | u64 _old, _new; \ | |
238 | int _retries = 50; \ | |
239 | \ | |
240 | do { \ | |
241 | _old = read_sysreg(reg); \ | |
242 | _new = read_sysreg(reg); \ | |
243 | _retries--; \ | |
244 | } while (unlikely((_new - _old) >> 5) && _retries); \ | |
245 | \ | |
246 | WARN_ON_ONCE(!_retries); \ | |
247 | _new; \ | |
248 | }) | |
249 | ||
250 | static u32 notrace hisi_161010101_read_cntp_tval_el0(void) | |
251 | { | |
252 | return __hisi_161010101_read_reg(cntp_tval_el0); | |
253 | } | |
254 | ||
255 | static u32 notrace hisi_161010101_read_cntv_tval_el0(void) | |
256 | { | |
257 | return __hisi_161010101_read_reg(cntv_tval_el0); | |
258 | } | |
259 | ||
260 | static u64 notrace hisi_161010101_read_cntvct_el0(void) | |
261 | { | |
262 | return __hisi_161010101_read_reg(cntvct_el0); | |
263 | } | |
bde4b58c MZ |
264 | |
265 | static struct ate_acpi_oem_info hisi_161010101_oem_info[] = { | |
266 | /* | |
267 | * Note that trailing spaces are required to properly match | |
268 | * the OEM table information. | |
269 | */ | |
270 | { | |
271 | .oem_id = "HISI ", | |
272 | .oem_table_id = "HIP05 ", | |
273 | .oem_revision = 0, | |
274 | }, | |
275 | { | |
276 | .oem_id = "HISI ", | |
277 | .oem_table_id = "HIP06 ", | |
278 | .oem_revision = 0, | |
279 | }, | |
280 | { | |
281 | .oem_id = "HISI ", | |
282 | .oem_table_id = "HIP07 ", | |
283 | .oem_revision = 0, | |
284 | }, | |
285 | { /* Sentinel indicating the end of the OEM array */ }, | |
286 | }; | |
cc104462 DT |
287 | #endif |
288 | ||
47f291e2 MZ |
289 | #ifdef CONFIG_ARM64_ERRATUM_858921 |
290 | static u64 notrace arm64_858921_read_cntvct_el0(void) | |
291 | { | |
292 | u64 old, new; | |
293 | ||
294 | old = read_sysreg(cntvct_el0); | |
295 | new = read_sysreg(cntvct_el0); | |
296 | return (((old ^ new) >> 32) & 1) ? old : new; | |
297 | } | |
298 | #endif | |
299 | ||
70d016c2 | 300 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
2c80d34c MZ |
301 | DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, |
302 | timer_unstable_counter_workaround); | |
70d016c2 DT |
303 | EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); |
304 | ||
305 | DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); | |
306 | EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled); | |
307 | ||
4b76f7fb MZ |
308 | static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, |
309 | struct clock_event_device *clk) | |
310 | { | |
311 | unsigned long ctrl; | |
312 | u64 cval = evt + arch_counter_get_cntvct(); | |
313 | ||
314 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
315 | ctrl |= ARCH_TIMER_CTRL_ENABLE; | |
316 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
317 | ||
318 | if (access == ARCH_TIMER_PHYS_ACCESS) | |
319 | write_sysreg(cval, cntp_cval_el0); | |
320 | else | |
321 | write_sysreg(cval, cntv_cval_el0); | |
322 | ||
323 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
324 | } | |
325 | ||
326 | static int erratum_set_next_event_tval_virt(unsigned long evt, | |
327 | struct clock_event_device *clk) | |
328 | { | |
329 | erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk); | |
330 | return 0; | |
331 | } | |
332 | ||
333 | static int erratum_set_next_event_tval_phys(unsigned long evt, | |
334 | struct clock_event_device *clk) | |
335 | { | |
336 | erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk); | |
337 | return 0; | |
338 | } | |
339 | ||
70d016c2 DT |
340 | static const struct arch_timer_erratum_workaround ool_workarounds[] = { |
341 | #ifdef CONFIG_FSL_ERRATUM_A008585 | |
342 | { | |
63d321a7 | 343 | .match_type = ate_match_dt, |
70d016c2 | 344 | .id = "fsl,erratum-a008585", |
63d321a7 | 345 | .desc = "Freescale erratum a005858", |
70d016c2 DT |
346 | .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, |
347 | .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, | |
348 | .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, | |
5d9decde MZ |
349 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
350 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
70d016c2 DT |
351 | }, |
352 | #endif | |
cc104462 DT |
353 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
354 | { | |
63d321a7 | 355 | .match_type = ate_match_dt, |
cc104462 | 356 | .id = "hisilicon,erratum-161010101", |
63d321a7 | 357 | .desc = "HiSilicon erratum 161010101", |
cc104462 DT |
358 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, |
359 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
360 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
5d9decde MZ |
361 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
362 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
cc104462 | 363 | }, |
bde4b58c MZ |
364 | { |
365 | .match_type = ate_match_acpi_oem_info, | |
366 | .id = hisi_161010101_oem_info, | |
367 | .desc = "HiSilicon erratum 161010101", | |
368 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, | |
369 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
370 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
371 | .set_next_event_phys = erratum_set_next_event_tval_phys, | |
372 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
373 | }, | |
cc104462 | 374 | #endif |
47f291e2 MZ |
375 | #ifdef CONFIG_ARM64_ERRATUM_858921 |
376 | { | |
377 | .match_type = ate_match_local_cap_id, | |
378 | .id = (void *)ARM64_WORKAROUND_858921, | |
379 | .desc = "ARM erratum 858921", | |
380 | .read_cntvct_el0 = arm64_858921_read_cntvct_el0, | |
381 | }, | |
382 | #endif | |
70d016c2 | 383 | }; |
63d321a7 MZ |
384 | |
385 | typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, | |
386 | const void *); | |
387 | ||
388 | static | |
389 | bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa, | |
390 | const void *arg) | |
391 | { | |
392 | const struct device_node *np = arg; | |
393 | ||
394 | return of_property_read_bool(np, wa->id); | |
395 | } | |
396 | ||
6d0a425d MZ |
397 | static |
398 | bool arch_timer_check_global_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
399 | const void *arg) | |
400 | { | |
401 | return cpus_have_cap((uintptr_t)wa->id); | |
402 | } | |
403 | ||
4e7813c2 MZ |
404 | static |
405 | bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
406 | const void *arg) | |
407 | { | |
408 | return this_cpu_has_cap((uintptr_t)wa->id); | |
409 | } | |
410 | ||
ea36ec17 MZ |
411 | |
412 | static | |
413 | bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa, | |
414 | const void *arg) | |
415 | { | |
416 | static const struct ate_acpi_oem_info empty_oem_info = {}; | |
417 | const struct ate_acpi_oem_info *info = wa->id; | |
418 | const struct acpi_table_header *table = arg; | |
419 | ||
420 | /* Iterate over the ACPI OEM info array, looking for a match */ | |
421 | while (memcmp(info, &empty_oem_info, sizeof(*info))) { | |
422 | if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) && | |
423 | !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && | |
424 | info->oem_revision == table->oem_revision) | |
425 | return true; | |
426 | ||
427 | info++; | |
428 | } | |
429 | ||
430 | return false; | |
431 | } | |
432 | ||
63d321a7 MZ |
433 | static const struct arch_timer_erratum_workaround * |
434 | arch_timer_iterate_errata(enum arch_timer_erratum_match_type type, | |
435 | ate_match_fn_t match_fn, | |
436 | void *arg) | |
437 | { | |
438 | int i; | |
439 | ||
440 | for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { | |
441 | if (ool_workarounds[i].match_type != type) | |
442 | continue; | |
443 | ||
444 | if (match_fn(&ool_workarounds[i], arg)) | |
445 | return &ool_workarounds[i]; | |
446 | } | |
447 | ||
448 | return NULL; | |
449 | } | |
450 | ||
451 | static | |
2c80d34c MZ |
452 | void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa, |
453 | bool local) | |
63d321a7 | 454 | { |
2c80d34c MZ |
455 | int i; |
456 | ||
457 | if (local) { | |
458 | __this_cpu_write(timer_unstable_counter_workaround, wa); | |
459 | } else { | |
460 | for_each_possible_cpu(i) | |
461 | per_cpu(timer_unstable_counter_workaround, i) = wa; | |
462 | } | |
463 | ||
63d321a7 | 464 | static_branch_enable(&arch_timer_read_ool_enabled); |
83f3444f MZ |
465 | |
466 | /* | |
467 | * Don't use the vdso fastpath if errata require using the | |
468 | * out-of-line counter accessor. We may change our mind pretty | |
469 | * late in the game (with a per-CPU erratum, for example), so | |
470 | * change both the default value and the vdso itself. | |
471 | */ | |
472 | if (wa->read_cntvct_el0) { | |
473 | clocksource_counter.archdata.vdso_direct = false; | |
474 | vdso_default = false; | |
475 | } | |
63d321a7 MZ |
476 | } |
477 | ||
478 | static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type, | |
479 | void *arg) | |
480 | { | |
481 | const struct arch_timer_erratum_workaround *wa; | |
482 | ate_match_fn_t match_fn = NULL; | |
4e7813c2 | 483 | bool local = false; |
63d321a7 MZ |
484 | |
485 | switch (type) { | |
486 | case ate_match_dt: | |
487 | match_fn = arch_timer_check_dt_erratum; | |
488 | break; | |
6d0a425d MZ |
489 | case ate_match_global_cap_id: |
490 | match_fn = arch_timer_check_global_cap_erratum; | |
491 | break; | |
4e7813c2 MZ |
492 | case ate_match_local_cap_id: |
493 | match_fn = arch_timer_check_local_cap_erratum; | |
494 | local = true; | |
495 | break; | |
ea36ec17 MZ |
496 | case ate_match_acpi_oem_info: |
497 | match_fn = arch_timer_check_acpi_oem_erratum; | |
498 | break; | |
df611637 | 499 | default: |
500 | pr_err("arch_timer: Unknown erratum workaround type specified.\n"); | |
501 | return; | |
63d321a7 MZ |
502 | } |
503 | ||
504 | wa = arch_timer_iterate_errata(type, match_fn, arg); | |
505 | if (!wa) | |
506 | return; | |
507 | ||
4e7813c2 | 508 | if (static_branch_unlikely(&arch_timer_read_ool_enabled)) { |
2c80d34c MZ |
509 | const struct arch_timer_erratum_workaround *__wa; |
510 | __wa = __this_cpu_read(timer_unstable_counter_workaround); | |
511 | if (__wa && wa != __wa) | |
4e7813c2 | 512 | pr_warn("Can't enable workaround for %s (clashes with %s\n)", |
2c80d34c MZ |
513 | wa->desc, __wa->desc); |
514 | ||
515 | if (__wa) | |
516 | return; | |
4e7813c2 MZ |
517 | } |
518 | ||
2c80d34c | 519 | arch_timer_enable_workaround(wa, local); |
4e7813c2 MZ |
520 | pr_info("Enabling %s workaround for %s\n", |
521 | local ? "local" : "global", wa->desc); | |
63d321a7 MZ |
522 | } |
523 | ||
5d9decde MZ |
524 | #define erratum_handler(fn, r, ...) \ |
525 | ({ \ | |
526 | bool __val; \ | |
2c80d34c MZ |
527 | if (needs_unstable_timer_counter_workaround()) { \ |
528 | const struct arch_timer_erratum_workaround *__wa; \ | |
529 | __wa = __this_cpu_read(timer_unstable_counter_workaround); \ | |
530 | if (__wa && __wa->fn) { \ | |
531 | r = __wa->fn(__VA_ARGS__); \ | |
532 | __val = true; \ | |
533 | } else { \ | |
534 | __val = false; \ | |
535 | } \ | |
5d9decde MZ |
536 | } else { \ |
537 | __val = false; \ | |
538 | } \ | |
539 | __val; \ | |
540 | }) | |
541 | ||
83f3444f MZ |
542 | static bool arch_timer_this_cpu_has_cntvct_wa(void) |
543 | { | |
544 | const struct arch_timer_erratum_workaround *wa; | |
545 | ||
546 | wa = __this_cpu_read(timer_unstable_counter_workaround); | |
547 | return wa && wa->read_cntvct_el0; | |
548 | } | |
63d321a7 MZ |
549 | #else |
550 | #define arch_timer_check_ool_workaround(t,a) do { } while(0) | |
4b76f7fb MZ |
551 | #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;}) |
552 | #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;}) | |
5d9decde | 553 | #define erratum_handler(fn, r, ...) ({false;}) |
83f3444f | 554 | #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) |
70d016c2 | 555 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ |
f6dc1576 | 556 | |
e09f3cc0 | 557 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
558 | struct clock_event_device *evt) |
559 | { | |
560 | unsigned long ctrl; | |
cfb6d656 | 561 | |
60faddf6 | 562 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
563 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
564 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 565 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
566 | evt->event_handler(evt); |
567 | return IRQ_HANDLED; | |
568 | } | |
569 | ||
570 | return IRQ_NONE; | |
571 | } | |
572 | ||
573 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
574 | { | |
575 | struct clock_event_device *evt = dev_id; | |
576 | ||
577 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
578 | } | |
579 | ||
580 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
581 | { | |
582 | struct clock_event_device *evt = dev_id; | |
583 | ||
584 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
585 | } | |
586 | ||
22006994 SB |
587 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
588 | { | |
589 | struct clock_event_device *evt = dev_id; | |
590 | ||
591 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
592 | } | |
593 | ||
594 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
595 | { | |
596 | struct clock_event_device *evt = dev_id; | |
597 | ||
598 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
599 | } | |
600 | ||
46c5bfdd VK |
601 | static __always_inline int timer_shutdown(const int access, |
602 | struct clock_event_device *clk) | |
8a4da6e3 MR |
603 | { |
604 | unsigned long ctrl; | |
46c5bfdd VK |
605 | |
606 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
607 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; | |
608 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
609 | ||
610 | return 0; | |
8a4da6e3 MR |
611 | } |
612 | ||
46c5bfdd | 613 | static int arch_timer_shutdown_virt(struct clock_event_device *clk) |
8a4da6e3 | 614 | { |
46c5bfdd | 615 | return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk); |
8a4da6e3 MR |
616 | } |
617 | ||
46c5bfdd | 618 | static int arch_timer_shutdown_phys(struct clock_event_device *clk) |
8a4da6e3 | 619 | { |
46c5bfdd | 620 | return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); |
8a4da6e3 MR |
621 | } |
622 | ||
46c5bfdd | 623 | static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) |
22006994 | 624 | { |
46c5bfdd | 625 | return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); |
8a4da6e3 MR |
626 | } |
627 | ||
46c5bfdd | 628 | static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) |
22006994 | 629 | { |
46c5bfdd | 630 | return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); |
22006994 SB |
631 | } |
632 | ||
60faddf6 | 633 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 634 | struct clock_event_device *clk) |
8a4da6e3 MR |
635 | { |
636 | unsigned long ctrl; | |
60faddf6 | 637 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
638 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
639 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
640 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
641 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
642 | } |
643 | ||
644 | static int arch_timer_set_next_event_virt(unsigned long evt, | |
60faddf6 | 645 | struct clock_event_device *clk) |
8a4da6e3 | 646 | { |
5d9decde MZ |
647 | int ret; |
648 | ||
649 | if (erratum_handler(set_next_event_virt, ret, evt, clk)) | |
650 | return ret; | |
4b76f7fb | 651 | |
60faddf6 | 652 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
653 | return 0; |
654 | } | |
655 | ||
656 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 657 | struct clock_event_device *clk) |
8a4da6e3 | 658 | { |
5d9decde MZ |
659 | int ret; |
660 | ||
661 | if (erratum_handler(set_next_event_phys, ret, evt, clk)) | |
662 | return ret; | |
4b76f7fb | 663 | |
60faddf6 | 664 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
665 | return 0; |
666 | } | |
667 | ||
22006994 SB |
668 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
669 | struct clock_event_device *clk) | |
8a4da6e3 | 670 | { |
22006994 SB |
671 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
672 | return 0; | |
673 | } | |
674 | ||
675 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
676 | struct clock_event_device *clk) | |
677 | { | |
678 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
679 | return 0; | |
680 | } | |
681 | ||
cfb6d656 TG |
682 | static void __arch_timer_setup(unsigned type, |
683 | struct clock_event_device *clk) | |
22006994 SB |
684 | { |
685 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
686 | ||
ebcb3a17 | 687 | if (type == ARCH_TIMER_TYPE_CP15) { |
82a56194 LP |
688 | if (arch_timer_c3stop) |
689 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
690 | clk->name = "arch_sys_timer"; |
691 | clk->rating = 450; | |
692 | clk->cpumask = cpumask_of(smp_processor_id()); | |
f81f03fa MZ |
693 | clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; |
694 | switch (arch_timer_uses_ppi) { | |
5d38740d | 695 | case ARCH_TIMER_VIRT_PPI: |
46c5bfdd | 696 | clk->set_state_shutdown = arch_timer_shutdown_virt; |
cf8c5009 | 697 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; |
22006994 | 698 | clk->set_next_event = arch_timer_set_next_event_virt; |
f81f03fa | 699 | break; |
5d38740d FW |
700 | case ARCH_TIMER_PHYS_SECURE_PPI: |
701 | case ARCH_TIMER_PHYS_NONSECURE_PPI: | |
702 | case ARCH_TIMER_HYP_PPI: | |
46c5bfdd | 703 | clk->set_state_shutdown = arch_timer_shutdown_phys; |
cf8c5009 | 704 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; |
22006994 | 705 | clk->set_next_event = arch_timer_set_next_event_phys; |
f81f03fa MZ |
706 | break; |
707 | default: | |
708 | BUG(); | |
22006994 | 709 | } |
f6dc1576 | 710 | |
4e7813c2 | 711 | arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); |
8a4da6e3 | 712 | } else { |
7b52ad2e | 713 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
714 | clk->name = "arch_mem_timer"; |
715 | clk->rating = 400; | |
716 | clk->cpumask = cpu_all_mask; | |
717 | if (arch_timer_mem_use_virtual) { | |
46c5bfdd | 718 | clk->set_state_shutdown = arch_timer_shutdown_virt_mem; |
cf8c5009 | 719 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; |
22006994 SB |
720 | clk->set_next_event = |
721 | arch_timer_set_next_event_virt_mem; | |
722 | } else { | |
46c5bfdd | 723 | clk->set_state_shutdown = arch_timer_shutdown_phys_mem; |
cf8c5009 | 724 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; |
22006994 SB |
725 | clk->set_next_event = |
726 | arch_timer_set_next_event_phys_mem; | |
727 | } | |
8a4da6e3 MR |
728 | } |
729 | ||
46c5bfdd | 730 | clk->set_state_shutdown(clk); |
8a4da6e3 | 731 | |
22006994 SB |
732 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
733 | } | |
8a4da6e3 | 734 | |
e1ce5c7a NL |
735 | static void arch_timer_evtstrm_enable(int divider) |
736 | { | |
737 | u32 cntkctl = arch_timer_get_cntkctl(); | |
738 | ||
739 | cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; | |
740 | /* Set the divider and enable virtual event stream */ | |
741 | cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | |
742 | | ARCH_TIMER_VIRT_EVT_EN; | |
743 | arch_timer_set_cntkctl(cntkctl); | |
744 | elf_hwcap |= HWCAP_EVTSTRM; | |
745 | #ifdef CONFIG_COMPAT | |
746 | compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; | |
747 | #endif | |
748 | } | |
749 | ||
037f6377 WD |
750 | static void arch_timer_configure_evtstream(void) |
751 | { | |
752 | int evt_stream_div, pos; | |
753 | ||
754 | /* Find the closest power of two to the divisor */ | |
755 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
756 | pos = fls(evt_stream_div); | |
757 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
758 | pos--; | |
759 | /* enable event stream */ | |
760 | arch_timer_evtstrm_enable(min(pos, 15)); | |
761 | } | |
762 | ||
8b8dde00 NL |
763 | static void arch_counter_set_user_access(void) |
764 | { | |
765 | u32 cntkctl = arch_timer_get_cntkctl(); | |
766 | ||
767 | /* Disable user access to the timers and the physical counter */ | |
768 | /* Also disable virtual event stream */ | |
769 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
770 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
771 | | ARCH_TIMER_VIRT_EVT_EN | |
772 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
773 | ||
83f3444f MZ |
774 | /* |
775 | * Enable user access to the virtual counter if it doesn't | |
776 | * need to be workaround. The vdso may have been already | |
777 | * disabled though. | |
778 | */ | |
779 | if (arch_timer_this_cpu_has_cntvct_wa()) | |
780 | pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id()); | |
781 | else | |
782 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
8b8dde00 NL |
783 | |
784 | arch_timer_set_cntkctl(cntkctl); | |
785 | } | |
786 | ||
f81f03fa MZ |
787 | static bool arch_timer_has_nonsecure_ppi(void) |
788 | { | |
5d38740d FW |
789 | return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI && |
790 | arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); | |
f81f03fa MZ |
791 | } |
792 | ||
f005bd7e MZ |
793 | static u32 check_ppi_trigger(int irq) |
794 | { | |
795 | u32 flags = irq_get_trigger_type(irq); | |
796 | ||
797 | if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { | |
798 | pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); | |
799 | pr_warn("WARNING: Please fix your firmware\n"); | |
800 | flags = IRQF_TRIGGER_LOW; | |
801 | } | |
802 | ||
803 | return flags; | |
804 | } | |
805 | ||
7e86e8bd | 806 | static int arch_timer_starting_cpu(unsigned int cpu) |
22006994 | 807 | { |
7e86e8bd | 808 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
f005bd7e | 809 | u32 flags; |
7e86e8bd | 810 | |
ebcb3a17 | 811 | __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk); |
8a4da6e3 | 812 | |
f005bd7e MZ |
813 | flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); |
814 | enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); | |
f81f03fa | 815 | |
f005bd7e | 816 | if (arch_timer_has_nonsecure_ppi()) { |
5d38740d FW |
817 | flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); |
818 | enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI], | |
819 | flags); | |
f005bd7e | 820 | } |
8a4da6e3 MR |
821 | |
822 | arch_counter_set_user_access(); | |
46fd5c6b | 823 | if (evtstrm_enable) |
037f6377 | 824 | arch_timer_configure_evtstream(); |
8a4da6e3 MR |
825 | |
826 | return 0; | |
827 | } | |
828 | ||
2a1f5645 FW |
829 | /* |
830 | * For historical reasons, when probing with DT we use whichever (non-zero) | |
831 | * rate was probed first, and don't verify that others match. If the first node | |
832 | * probed has a clock-frequency property, this overrides the HW register. | |
833 | */ | |
834 | static void arch_timer_of_configure_rate(u32 rate, struct device_node *np) | |
8a4da6e3 | 835 | { |
22006994 SB |
836 | /* Who has more than one independent system counter? */ |
837 | if (arch_timer_rate) | |
838 | return; | |
8a4da6e3 | 839 | |
2a1f5645 FW |
840 | if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) |
841 | arch_timer_rate = rate; | |
8a4da6e3 | 842 | |
22006994 SB |
843 | /* Check the timer frequency. */ |
844 | if (arch_timer_rate == 0) | |
3f968fa1 | 845 | pr_warn("frequency not available\n"); |
22006994 SB |
846 | } |
847 | ||
848 | static void arch_timer_banner(unsigned type) | |
849 | { | |
3f968fa1 | 850 | pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", |
ebcb3a17 FW |
851 | type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "", |
852 | type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? | |
853 | " and " : "", | |
854 | type & ARCH_TIMER_TYPE_MEM ? "mmio" : "", | |
3f968fa1 FW |
855 | (unsigned long)arch_timer_rate / 1000000, |
856 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
ebcb3a17 | 857 | type & ARCH_TIMER_TYPE_CP15 ? |
5d38740d | 858 | (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" : |
22006994 | 859 | "", |
ebcb3a17 FW |
860 | type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "", |
861 | type & ARCH_TIMER_TYPE_MEM ? | |
22006994 SB |
862 | arch_timer_mem_use_virtual ? "virt" : "phys" : |
863 | ""); | |
8a4da6e3 MR |
864 | } |
865 | ||
866 | u32 arch_timer_get_rate(void) | |
867 | { | |
868 | return arch_timer_rate; | |
869 | } | |
870 | ||
22006994 | 871 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 872 | { |
22006994 SB |
873 | u32 vct_lo, vct_hi, tmp_hi; |
874 | ||
875 | do { | |
876 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
877 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
878 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
879 | } while (vct_hi != tmp_hi); | |
880 | ||
881 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
882 | } |
883 | ||
b4d6ce97 JG |
884 | static struct arch_timer_kvm_info arch_timer_kvm_info; |
885 | ||
886 | struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) | |
887 | { | |
888 | return &arch_timer_kvm_info; | |
889 | } | |
8a4da6e3 | 890 | |
22006994 SB |
891 | static void __init arch_counter_register(unsigned type) |
892 | { | |
893 | u64 start_count; | |
894 | ||
895 | /* Register the CP15 based counter if we have one */ | |
ebcb3a17 | 896 | if (type & ARCH_TIMER_TYPE_CP15) { |
5d38740d FW |
897 | if (IS_ENABLED(CONFIG_ARM64) || |
898 | arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) | |
0b46b8a7 SR |
899 | arch_timer_read_counter = arch_counter_get_cntvct; |
900 | else | |
901 | arch_timer_read_counter = arch_counter_get_cntpct; | |
f6dc1576 | 902 | |
83f3444f | 903 | clocksource_counter.archdata.vdso_direct = vdso_default; |
423bd69e | 904 | } else { |
22006994 | 905 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
423bd69e NL |
906 | } |
907 | ||
d8ec7595 BN |
908 | if (!arch_counter_suspend_stop) |
909 | clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
22006994 SB |
910 | start_count = arch_timer_read_counter(); |
911 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
912 | cyclecounter.mult = clocksource_counter.mult; | |
913 | cyclecounter.shift = clocksource_counter.shift; | |
b4d6ce97 JG |
914 | timecounter_init(&arch_timer_kvm_info.timecounter, |
915 | &cyclecounter, start_count); | |
4a7d3e8a TR |
916 | |
917 | /* 56 bits minimum, so we assume worst case rollover */ | |
918 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
919 | } |
920 | ||
8c37bb3a | 921 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 | 922 | { |
3f968fa1 | 923 | pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id()); |
8a4da6e3 | 924 | |
f81f03fa MZ |
925 | disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]); |
926 | if (arch_timer_has_nonsecure_ppi()) | |
5d38740d | 927 | disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); |
8a4da6e3 | 928 | |
46c5bfdd | 929 | clk->set_state_shutdown(clk); |
8a4da6e3 MR |
930 | } |
931 | ||
7e86e8bd | 932 | static int arch_timer_dying_cpu(unsigned int cpu) |
8a4da6e3 | 933 | { |
7e86e8bd | 934 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
8a4da6e3 | 935 | |
7e86e8bd RC |
936 | arch_timer_stop(clk); |
937 | return 0; | |
8a4da6e3 MR |
938 | } |
939 | ||
346e7480 SH |
940 | #ifdef CONFIG_CPU_PM |
941 | static unsigned int saved_cntkctl; | |
942 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, | |
943 | unsigned long action, void *hcpu) | |
944 | { | |
945 | if (action == CPU_PM_ENTER) | |
946 | saved_cntkctl = arch_timer_get_cntkctl(); | |
947 | else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) | |
948 | arch_timer_set_cntkctl(saved_cntkctl); | |
949 | return NOTIFY_OK; | |
950 | } | |
951 | ||
952 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
953 | .notifier_call = arch_timer_cpu_pm_notify, | |
954 | }; | |
955 | ||
956 | static int __init arch_timer_cpu_pm_init(void) | |
957 | { | |
958 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
959 | } | |
7e86e8bd RC |
960 | |
961 | static void __init arch_timer_cpu_pm_deinit(void) | |
962 | { | |
963 | WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier)); | |
964 | } | |
965 | ||
346e7480 SH |
966 | #else |
967 | static int __init arch_timer_cpu_pm_init(void) | |
968 | { | |
969 | return 0; | |
970 | } | |
7e86e8bd RC |
971 | |
972 | static void __init arch_timer_cpu_pm_deinit(void) | |
973 | { | |
974 | } | |
346e7480 SH |
975 | #endif |
976 | ||
8a4da6e3 MR |
977 | static int __init arch_timer_register(void) |
978 | { | |
979 | int err; | |
980 | int ppi; | |
981 | ||
8a4da6e3 MR |
982 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
983 | if (!arch_timer_evt) { | |
984 | err = -ENOMEM; | |
985 | goto out; | |
986 | } | |
987 | ||
f81f03fa MZ |
988 | ppi = arch_timer_ppi[arch_timer_uses_ppi]; |
989 | switch (arch_timer_uses_ppi) { | |
5d38740d | 990 | case ARCH_TIMER_VIRT_PPI: |
8a4da6e3 MR |
991 | err = request_percpu_irq(ppi, arch_timer_handler_virt, |
992 | "arch_timer", arch_timer_evt); | |
f81f03fa | 993 | break; |
5d38740d FW |
994 | case ARCH_TIMER_PHYS_SECURE_PPI: |
995 | case ARCH_TIMER_PHYS_NONSECURE_PPI: | |
8a4da6e3 MR |
996 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
997 | "arch_timer", arch_timer_evt); | |
8e35c293 | 998 | if (!err && arch_timer_has_nonsecure_ppi()) { |
5d38740d | 999 | ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]; |
8a4da6e3 MR |
1000 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
1001 | "arch_timer", arch_timer_evt); | |
1002 | if (err) | |
5d38740d | 1003 | free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI], |
8a4da6e3 MR |
1004 | arch_timer_evt); |
1005 | } | |
f81f03fa | 1006 | break; |
5d38740d | 1007 | case ARCH_TIMER_HYP_PPI: |
f81f03fa MZ |
1008 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
1009 | "arch_timer", arch_timer_evt); | |
1010 | break; | |
1011 | default: | |
1012 | BUG(); | |
8a4da6e3 MR |
1013 | } |
1014 | ||
1015 | if (err) { | |
3f968fa1 | 1016 | pr_err("can't register interrupt %d (%d)\n", ppi, err); |
8a4da6e3 MR |
1017 | goto out_free; |
1018 | } | |
1019 | ||
346e7480 SH |
1020 | err = arch_timer_cpu_pm_init(); |
1021 | if (err) | |
1022 | goto out_unreg_notify; | |
1023 | ||
8a4da6e3 | 1024 | |
7e86e8bd RC |
1025 | /* Register and immediately configure the timer on the boot CPU */ |
1026 | err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, | |
73c1b41e | 1027 | "clockevents/arm/arch_timer:starting", |
7e86e8bd RC |
1028 | arch_timer_starting_cpu, arch_timer_dying_cpu); |
1029 | if (err) | |
1030 | goto out_unreg_cpupm; | |
8a4da6e3 MR |
1031 | return 0; |
1032 | ||
7e86e8bd RC |
1033 | out_unreg_cpupm: |
1034 | arch_timer_cpu_pm_deinit(); | |
1035 | ||
346e7480 | 1036 | out_unreg_notify: |
f81f03fa MZ |
1037 | free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt); |
1038 | if (arch_timer_has_nonsecure_ppi()) | |
5d38740d | 1039 | free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI], |
8a4da6e3 | 1040 | arch_timer_evt); |
8a4da6e3 MR |
1041 | |
1042 | out_free: | |
1043 | free_percpu(arch_timer_evt); | |
1044 | out: | |
1045 | return err; | |
1046 | } | |
1047 | ||
22006994 SB |
1048 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
1049 | { | |
1050 | int ret; | |
1051 | irq_handler_t func; | |
1052 | struct arch_timer *t; | |
1053 | ||
1054 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
1055 | if (!t) | |
1056 | return -ENOMEM; | |
1057 | ||
1058 | t->base = base; | |
1059 | t->evt.irq = irq; | |
ebcb3a17 | 1060 | __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt); |
22006994 SB |
1061 | |
1062 | if (arch_timer_mem_use_virtual) | |
1063 | func = arch_timer_handler_virt_mem; | |
1064 | else | |
1065 | func = arch_timer_handler_phys_mem; | |
1066 | ||
1067 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
1068 | if (ret) { | |
3f968fa1 | 1069 | pr_err("Failed to request mem timer irq\n"); |
22006994 SB |
1070 | kfree(t); |
1071 | } | |
1072 | ||
1073 | return ret; | |
1074 | } | |
1075 | ||
1076 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
1077 | { .compatible = "arm,armv7-timer", }, | |
1078 | { .compatible = "arm,armv8-timer", }, | |
1079 | {}, | |
1080 | }; | |
1081 | ||
1082 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
1083 | { .compatible = "arm,armv7-timer-mem", }, | |
1084 | {}, | |
1085 | }; | |
1086 | ||
5438ee3b | 1087 | static bool __init arch_timer_needs_of_probing(void) |
c387f07e SH |
1088 | { |
1089 | struct device_node *dn; | |
566e6dfa | 1090 | bool needs_probing = false; |
5438ee3b | 1091 | unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM; |
c387f07e | 1092 | |
5438ee3b FW |
1093 | /* We have two timers, and both device-tree nodes are probed. */ |
1094 | if ((arch_timers_present & mask) == mask) | |
1095 | return false; | |
1096 | ||
1097 | /* | |
1098 | * Only one type of timer is probed, | |
1099 | * check if we have another type of timer node in device-tree. | |
1100 | */ | |
1101 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) | |
1102 | dn = of_find_matching_node(NULL, arch_timer_mem_of_match); | |
1103 | else | |
1104 | dn = of_find_matching_node(NULL, arch_timer_of_match); | |
1105 | ||
1106 | if (dn && of_device_is_available(dn)) | |
566e6dfa | 1107 | needs_probing = true; |
5438ee3b | 1108 | |
c387f07e SH |
1109 | of_node_put(dn); |
1110 | ||
566e6dfa | 1111 | return needs_probing; |
c387f07e SH |
1112 | } |
1113 | ||
3c0731db | 1114 | static int __init arch_timer_common_init(void) |
22006994 | 1115 | { |
22006994 SB |
1116 | arch_timer_banner(arch_timers_present); |
1117 | arch_counter_register(arch_timers_present); | |
3c0731db | 1118 | return arch_timer_arch_init(); |
22006994 SB |
1119 | } |
1120 | ||
8e35c293 FW |
1121 | /** |
1122 | * arch_timer_select_ppi() - Select suitable PPI for the current system. | |
1123 | * | |
1124 | * If HYP mode is available, we know that the physical timer | |
1125 | * has been configured to be accessible from PL1. Use it, so | |
1126 | * that a guest can use the virtual timer instead. | |
1127 | * | |
1128 | * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE | |
1129 | * accesses to CNTP_*_EL1 registers are silently redirected to | |
1130 | * their CNTHP_*_EL2 counterparts, and use a different PPI | |
1131 | * number. | |
1132 | * | |
1133 | * If no interrupt provided for virtual timer, we'll have to | |
1134 | * stick to the physical timer. It'd better be accessible... | |
1135 | * For arm64 we never use the secure interrupt. | |
1136 | * | |
1137 | * Return: a suitable PPI type for the current system. | |
1138 | */ | |
1139 | static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void) | |
8a4da6e3 | 1140 | { |
8e35c293 FW |
1141 | if (is_kernel_in_hyp_mode()) |
1142 | return ARCH_TIMER_HYP_PPI; | |
f81f03fa | 1143 | |
8e35c293 FW |
1144 | if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) |
1145 | return ARCH_TIMER_VIRT_PPI; | |
8a4da6e3 | 1146 | |
8e35c293 FW |
1147 | if (IS_ENABLED(CONFIG_ARM64)) |
1148 | return ARCH_TIMER_PHYS_NONSECURE_PPI; | |
1149 | ||
1150 | return ARCH_TIMER_PHYS_SECURE_PPI; | |
1151 | } | |
1152 | ||
3c0731db | 1153 | static int __init arch_timer_of_init(struct device_node *np) |
b09ca1ec | 1154 | { |
e93ed2db | 1155 | int i, ret; |
2a1f5645 | 1156 | u32 rate; |
b09ca1ec | 1157 | |
ebcb3a17 | 1158 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { |
3f968fa1 | 1159 | pr_warn("multiple nodes in dt, skipping\n"); |
3c0731db | 1160 | return 0; |
b09ca1ec HG |
1161 | } |
1162 | ||
ebcb3a17 | 1163 | arch_timers_present |= ARCH_TIMER_TYPE_CP15; |
5d38740d | 1164 | for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) |
b09ca1ec HG |
1165 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); |
1166 | ||
e93ed2db FW |
1167 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI]; |
1168 | ||
2a1f5645 FW |
1169 | rate = arch_timer_get_cntfrq; |
1170 | arch_timer_of_configure_rate(rate, np); | |
b09ca1ec HG |
1171 | |
1172 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); | |
1173 | ||
63d321a7 MZ |
1174 | /* Check for globally applicable workarounds */ |
1175 | arch_timer_check_ool_workaround(ate_match_dt, np); | |
6d0a425d | 1176 | arch_timer_check_ool_workaround(ate_match_global_cap_id, NULL); |
f6dc1576 | 1177 | |
b09ca1ec HG |
1178 | /* |
1179 | * If we cannot rely on firmware initializing the timer registers then | |
1180 | * we should use the physical timers instead. | |
1181 | */ | |
1182 | if (IS_ENABLED(CONFIG_ARM) && | |
1183 | of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) | |
5d38740d | 1184 | arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; |
8e35c293 FW |
1185 | else |
1186 | arch_timer_uses_ppi = arch_timer_select_ppi(); | |
1187 | ||
1188 | if (!arch_timer_ppi[arch_timer_uses_ppi]) { | |
1189 | pr_err("No interrupt available, giving up\n"); | |
1190 | return -EINVAL; | |
1191 | } | |
b09ca1ec | 1192 | |
d8ec7595 BN |
1193 | /* On some systems, the counter stops ticking when in suspend. */ |
1194 | arch_counter_suspend_stop = of_property_read_bool(np, | |
1195 | "arm,no-tick-in-suspend"); | |
1196 | ||
e93ed2db FW |
1197 | ret = arch_timer_register(); |
1198 | if (ret) | |
1199 | return ret; | |
1200 | ||
1201 | if (arch_timer_needs_of_probing()) | |
1202 | return 0; | |
1203 | ||
1204 | return arch_timer_common_init(); | |
b09ca1ec | 1205 | } |
177cf6e5 DL |
1206 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); |
1207 | CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); | |
22006994 | 1208 | |
3c0731db | 1209 | static int __init arch_timer_mem_init(struct device_node *np) |
22006994 SB |
1210 | { |
1211 | struct device_node *frame, *best_frame = NULL; | |
1212 | void __iomem *cntctlbase, *base; | |
3c0731db | 1213 | unsigned int irq, ret = -EINVAL; |
2a1f5645 | 1214 | u32 cnttidr, rate; |
22006994 | 1215 | |
ebcb3a17 | 1216 | arch_timers_present |= ARCH_TIMER_TYPE_MEM; |
22006994 SB |
1217 | cntctlbase = of_iomap(np, 0); |
1218 | if (!cntctlbase) { | |
3f968fa1 | 1219 | pr_err("Can't find CNTCTLBase\n"); |
3c0731db | 1220 | return -ENXIO; |
22006994 SB |
1221 | } |
1222 | ||
1223 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
22006994 SB |
1224 | |
1225 | /* | |
1226 | * Try to find a virtual capable frame. Otherwise fall back to a | |
1227 | * physical capable frame. | |
1228 | */ | |
1229 | for_each_available_child_of_node(np, frame) { | |
1230 | int n; | |
e392d603 | 1231 | u32 cntacr; |
22006994 SB |
1232 | |
1233 | if (of_property_read_u32(frame, "frame-number", &n)) { | |
3f968fa1 | 1234 | pr_err("Missing frame-number\n"); |
22006994 | 1235 | of_node_put(frame); |
e392d603 | 1236 | goto out; |
22006994 SB |
1237 | } |
1238 | ||
e392d603 RM |
1239 | /* Try enabling everything, and see what sticks */ |
1240 | cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | | |
1241 | CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; | |
1242 | writel_relaxed(cntacr, cntctlbase + CNTACR(n)); | |
1243 | cntacr = readl_relaxed(cntctlbase + CNTACR(n)); | |
1244 | ||
1245 | if ((cnttidr & CNTTIDR_VIRT(n)) && | |
1246 | !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { | |
22006994 SB |
1247 | of_node_put(best_frame); |
1248 | best_frame = frame; | |
1249 | arch_timer_mem_use_virtual = true; | |
1250 | break; | |
1251 | } | |
e392d603 RM |
1252 | |
1253 | if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) | |
1254 | continue; | |
1255 | ||
22006994 SB |
1256 | of_node_put(best_frame); |
1257 | best_frame = of_node_get(frame); | |
1258 | } | |
1259 | ||
3c0731db | 1260 | ret= -ENXIO; |
f947ee14 SB |
1261 | base = arch_counter_base = of_io_request_and_map(best_frame, 0, |
1262 | "arch_mem_timer"); | |
1263 | if (IS_ERR(base)) { | |
3f968fa1 | 1264 | pr_err("Can't map frame's registers\n"); |
e392d603 | 1265 | goto out; |
22006994 SB |
1266 | } |
1267 | ||
1268 | if (arch_timer_mem_use_virtual) | |
2c55cf0a | 1269 | irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_VIRT_SPI); |
22006994 | 1270 | else |
2c55cf0a | 1271 | irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_PHYS_SPI); |
e392d603 | 1272 | |
3c0731db | 1273 | ret = -EINVAL; |
22006994 | 1274 | if (!irq) { |
3f968fa1 | 1275 | pr_err("Frame missing %s irq.\n", |
cfb6d656 | 1276 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
e392d603 | 1277 | goto out; |
22006994 SB |
1278 | } |
1279 | ||
2a1f5645 FW |
1280 | rate = readl(base + CNTFRQ); |
1281 | arch_timer_of_configure_rate(rate, np); | |
3c0731db DL |
1282 | ret = arch_timer_mem_register(base, irq); |
1283 | if (ret) | |
1284 | goto out; | |
1285 | ||
e93ed2db FW |
1286 | if (!arch_timer_needs_of_probing()) |
1287 | ret = arch_timer_common_init(); | |
e392d603 RM |
1288 | out: |
1289 | iounmap(cntctlbase); | |
1290 | of_node_put(best_frame); | |
3c0731db | 1291 | return ret; |
22006994 | 1292 | } |
177cf6e5 | 1293 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", |
22006994 | 1294 | arch_timer_mem_init); |
b09ca1ec HG |
1295 | |
1296 | #ifdef CONFIG_ACPI | |
1297 | static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) | |
1298 | { | |
1299 | int trigger, polarity; | |
1300 | ||
1301 | if (!interrupt) | |
1302 | return 0; | |
1303 | ||
1304 | trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE | |
1305 | : ACPI_LEVEL_SENSITIVE; | |
1306 | ||
1307 | polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW | |
1308 | : ACPI_ACTIVE_HIGH; | |
1309 | ||
1310 | return acpi_register_gsi(NULL, interrupt, trigger, polarity); | |
1311 | } | |
1312 | ||
1313 | /* Initialize per-processor generic timer */ | |
1314 | static int __init arch_timer_acpi_init(struct acpi_table_header *table) | |
1315 | { | |
e93ed2db | 1316 | int ret; |
b09ca1ec HG |
1317 | struct acpi_table_gtdt *gtdt; |
1318 | ||
ebcb3a17 | 1319 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { |
3f968fa1 | 1320 | pr_warn("already initialized, skipping\n"); |
b09ca1ec HG |
1321 | return -EINVAL; |
1322 | } | |
1323 | ||
1324 | gtdt = container_of(table, struct acpi_table_gtdt, header); | |
1325 | ||
ebcb3a17 | 1326 | arch_timers_present |= ARCH_TIMER_TYPE_CP15; |
b09ca1ec | 1327 | |
5d38740d | 1328 | arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] = |
b09ca1ec HG |
1329 | map_generic_timer_interrupt(gtdt->secure_el1_interrupt, |
1330 | gtdt->secure_el1_flags); | |
1331 | ||
5d38740d | 1332 | arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] = |
b09ca1ec HG |
1333 | map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt, |
1334 | gtdt->non_secure_el1_flags); | |
1335 | ||
5d38740d | 1336 | arch_timer_ppi[ARCH_TIMER_VIRT_PPI] = |
b09ca1ec HG |
1337 | map_generic_timer_interrupt(gtdt->virtual_timer_interrupt, |
1338 | gtdt->virtual_timer_flags); | |
1339 | ||
5d38740d | 1340 | arch_timer_ppi[ARCH_TIMER_HYP_PPI] = |
b09ca1ec HG |
1341 | map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt, |
1342 | gtdt->non_secure_el2_flags); | |
1343 | ||
e93ed2db FW |
1344 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI]; |
1345 | ||
2a1f5645 FW |
1346 | /* |
1347 | * When probing via ACPI, we have no mechanism to override the sysreg | |
1348 | * CNTFRQ value. This *must* be correct. | |
1349 | */ | |
1350 | arch_timer_rate = arch_timer_get_cntfrq(); | |
1351 | if (!arch_timer_rate) { | |
1352 | pr_err(FW_BUG "frequency not available.\n"); | |
1353 | return -EINVAL; | |
1354 | } | |
b09ca1ec | 1355 | |
8e35c293 FW |
1356 | arch_timer_uses_ppi = arch_timer_select_ppi(); |
1357 | if (!arch_timer_ppi[arch_timer_uses_ppi]) { | |
1358 | pr_err("No interrupt available, giving up\n"); | |
1359 | return -EINVAL; | |
1360 | } | |
1361 | ||
b09ca1ec HG |
1362 | /* Always-on capability */ |
1363 | arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON); | |
1364 | ||
6d0a425d MZ |
1365 | /* Check for globally applicable workarounds */ |
1366 | arch_timer_check_ool_workaround(ate_match_global_cap_id, NULL); | |
ea36ec17 | 1367 | arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table); |
6d0a425d | 1368 | |
e93ed2db FW |
1369 | ret = arch_timer_register(); |
1370 | if (ret) | |
1371 | return ret; | |
1372 | ||
1373 | return arch_timer_common_init(); | |
b09ca1ec | 1374 | } |
ae281cbd | 1375 | CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); |
b09ca1ec | 1376 | #endif |