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8a4da6e3 MR |
1 | /* |
2 | * linux/drivers/clocksource/arm_arch_timer.c | |
3 | * | |
4 | * Copyright (C) 2011 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/smp.h> | |
15 | #include <linux/cpu.h> | |
346e7480 | 16 | #include <linux/cpu_pm.h> |
8a4da6e3 MR |
17 | #include <linux/clockchips.h> |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/of_irq.h> | |
22006994 | 20 | #include <linux/of_address.h> |
8a4da6e3 | 21 | #include <linux/io.h> |
22006994 | 22 | #include <linux/slab.h> |
65cd4f6c | 23 | #include <linux/sched_clock.h> |
8a4da6e3 MR |
24 | |
25 | #include <asm/arch_timer.h> | |
8266891e | 26 | #include <asm/virt.h> |
8a4da6e3 MR |
27 | |
28 | #include <clocksource/arm_arch_timer.h> | |
29 | ||
22006994 SB |
30 | #define CNTTIDR 0x08 |
31 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
32 | ||
33 | #define CNTVCT_LO 0x08 | |
34 | #define CNTVCT_HI 0x0c | |
35 | #define CNTFRQ 0x10 | |
36 | #define CNTP_TVAL 0x28 | |
37 | #define CNTP_CTL 0x2c | |
38 | #define CNTV_TVAL 0x38 | |
39 | #define CNTV_CTL 0x3c | |
40 | ||
41 | #define ARCH_CP15_TIMER BIT(0) | |
42 | #define ARCH_MEM_TIMER BIT(1) | |
43 | static unsigned arch_timers_present __initdata; | |
44 | ||
45 | static void __iomem *arch_counter_base; | |
46 | ||
47 | struct arch_timer { | |
48 | void __iomem *base; | |
49 | struct clock_event_device evt; | |
50 | }; | |
51 | ||
52 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
53 | ||
8a4da6e3 MR |
54 | static u32 arch_timer_rate; |
55 | ||
56 | enum ppi_nr { | |
57 | PHYS_SECURE_PPI, | |
58 | PHYS_NONSECURE_PPI, | |
59 | VIRT_PPI, | |
60 | HYP_PPI, | |
61 | MAX_TIMER_PPI | |
62 | }; | |
63 | ||
64 | static int arch_timer_ppi[MAX_TIMER_PPI]; | |
65 | ||
66 | static struct clock_event_device __percpu *arch_timer_evt; | |
67 | ||
68 | static bool arch_timer_use_virtual = true; | |
82a56194 | 69 | static bool arch_timer_c3stop; |
22006994 | 70 | static bool arch_timer_mem_use_virtual; |
8a4da6e3 MR |
71 | |
72 | /* | |
73 | * Architected system timer support. | |
74 | */ | |
75 | ||
60faddf6 SB |
76 | static __always_inline |
77 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
cfb6d656 | 78 | struct clock_event_device *clk) |
60faddf6 | 79 | { |
22006994 SB |
80 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { |
81 | struct arch_timer *timer = to_arch_timer(clk); | |
82 | switch (reg) { | |
83 | case ARCH_TIMER_REG_CTRL: | |
84 | writel_relaxed(val, timer->base + CNTP_CTL); | |
85 | break; | |
86 | case ARCH_TIMER_REG_TVAL: | |
87 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
88 | break; | |
89 | } | |
90 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
91 | struct arch_timer *timer = to_arch_timer(clk); | |
92 | switch (reg) { | |
93 | case ARCH_TIMER_REG_CTRL: | |
94 | writel_relaxed(val, timer->base + CNTV_CTL); | |
95 | break; | |
96 | case ARCH_TIMER_REG_TVAL: | |
97 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
98 | break; | |
99 | } | |
100 | } else { | |
101 | arch_timer_reg_write_cp15(access, reg, val); | |
102 | } | |
60faddf6 SB |
103 | } |
104 | ||
105 | static __always_inline | |
106 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
cfb6d656 | 107 | struct clock_event_device *clk) |
60faddf6 | 108 | { |
22006994 SB |
109 | u32 val; |
110 | ||
111 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
112 | struct arch_timer *timer = to_arch_timer(clk); | |
113 | switch (reg) { | |
114 | case ARCH_TIMER_REG_CTRL: | |
115 | val = readl_relaxed(timer->base + CNTP_CTL); | |
116 | break; | |
117 | case ARCH_TIMER_REG_TVAL: | |
118 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
119 | break; | |
120 | } | |
121 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
122 | struct arch_timer *timer = to_arch_timer(clk); | |
123 | switch (reg) { | |
124 | case ARCH_TIMER_REG_CTRL: | |
125 | val = readl_relaxed(timer->base + CNTV_CTL); | |
126 | break; | |
127 | case ARCH_TIMER_REG_TVAL: | |
128 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
129 | break; | |
130 | } | |
131 | } else { | |
132 | val = arch_timer_reg_read_cp15(access, reg); | |
133 | } | |
134 | ||
135 | return val; | |
60faddf6 SB |
136 | } |
137 | ||
e09f3cc0 | 138 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
139 | struct clock_event_device *evt) |
140 | { | |
141 | unsigned long ctrl; | |
cfb6d656 | 142 | |
60faddf6 | 143 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
144 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
145 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 146 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
147 | evt->event_handler(evt); |
148 | return IRQ_HANDLED; | |
149 | } | |
150 | ||
151 | return IRQ_NONE; | |
152 | } | |
153 | ||
154 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
155 | { | |
156 | struct clock_event_device *evt = dev_id; | |
157 | ||
158 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
159 | } | |
160 | ||
161 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
162 | { | |
163 | struct clock_event_device *evt = dev_id; | |
164 | ||
165 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
166 | } | |
167 | ||
22006994 SB |
168 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
169 | { | |
170 | struct clock_event_device *evt = dev_id; | |
171 | ||
172 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
173 | } | |
174 | ||
175 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
176 | { | |
177 | struct clock_event_device *evt = dev_id; | |
178 | ||
179 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
180 | } | |
181 | ||
60faddf6 SB |
182 | static __always_inline void timer_set_mode(const int access, int mode, |
183 | struct clock_event_device *clk) | |
8a4da6e3 MR |
184 | { |
185 | unsigned long ctrl; | |
186 | switch (mode) { | |
187 | case CLOCK_EVT_MODE_UNUSED: | |
188 | case CLOCK_EVT_MODE_SHUTDOWN: | |
60faddf6 | 189 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 | 190 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; |
60faddf6 | 191 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); |
8a4da6e3 MR |
192 | break; |
193 | default: | |
194 | break; | |
195 | } | |
196 | } | |
197 | ||
198 | static void arch_timer_set_mode_virt(enum clock_event_mode mode, | |
199 | struct clock_event_device *clk) | |
200 | { | |
60faddf6 | 201 | timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk); |
8a4da6e3 MR |
202 | } |
203 | ||
204 | static void arch_timer_set_mode_phys(enum clock_event_mode mode, | |
205 | struct clock_event_device *clk) | |
206 | { | |
60faddf6 | 207 | timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk); |
8a4da6e3 MR |
208 | } |
209 | ||
22006994 SB |
210 | static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode, |
211 | struct clock_event_device *clk) | |
212 | { | |
213 | timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk); | |
8a4da6e3 MR |
214 | } |
215 | ||
22006994 SB |
216 | static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode, |
217 | struct clock_event_device *clk) | |
218 | { | |
219 | timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk); | |
220 | } | |
221 | ||
60faddf6 | 222 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 223 | struct clock_event_device *clk) |
8a4da6e3 MR |
224 | { |
225 | unsigned long ctrl; | |
60faddf6 | 226 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
227 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
228 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
229 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
230 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
231 | } |
232 | ||
233 | static int arch_timer_set_next_event_virt(unsigned long evt, | |
60faddf6 | 234 | struct clock_event_device *clk) |
8a4da6e3 | 235 | { |
60faddf6 | 236 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
237 | return 0; |
238 | } | |
239 | ||
240 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 241 | struct clock_event_device *clk) |
8a4da6e3 | 242 | { |
60faddf6 | 243 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
244 | return 0; |
245 | } | |
246 | ||
22006994 SB |
247 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
248 | struct clock_event_device *clk) | |
8a4da6e3 | 249 | { |
22006994 SB |
250 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
251 | return 0; | |
252 | } | |
253 | ||
254 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
255 | struct clock_event_device *clk) | |
256 | { | |
257 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
258 | return 0; | |
259 | } | |
260 | ||
cfb6d656 TG |
261 | static void __arch_timer_setup(unsigned type, |
262 | struct clock_event_device *clk) | |
22006994 SB |
263 | { |
264 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
265 | ||
266 | if (type == ARCH_CP15_TIMER) { | |
82a56194 LP |
267 | if (arch_timer_c3stop) |
268 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
269 | clk->name = "arch_sys_timer"; |
270 | clk->rating = 450; | |
271 | clk->cpumask = cpumask_of(smp_processor_id()); | |
272 | if (arch_timer_use_virtual) { | |
273 | clk->irq = arch_timer_ppi[VIRT_PPI]; | |
274 | clk->set_mode = arch_timer_set_mode_virt; | |
275 | clk->set_next_event = arch_timer_set_next_event_virt; | |
276 | } else { | |
277 | clk->irq = arch_timer_ppi[PHYS_SECURE_PPI]; | |
278 | clk->set_mode = arch_timer_set_mode_phys; | |
279 | clk->set_next_event = arch_timer_set_next_event_phys; | |
280 | } | |
8a4da6e3 | 281 | } else { |
7b52ad2e | 282 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
283 | clk->name = "arch_mem_timer"; |
284 | clk->rating = 400; | |
285 | clk->cpumask = cpu_all_mask; | |
286 | if (arch_timer_mem_use_virtual) { | |
287 | clk->set_mode = arch_timer_set_mode_virt_mem; | |
288 | clk->set_next_event = | |
289 | arch_timer_set_next_event_virt_mem; | |
290 | } else { | |
291 | clk->set_mode = arch_timer_set_mode_phys_mem; | |
292 | clk->set_next_event = | |
293 | arch_timer_set_next_event_phys_mem; | |
294 | } | |
8a4da6e3 MR |
295 | } |
296 | ||
1ff99ea6 | 297 | clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk); |
8a4da6e3 | 298 | |
22006994 SB |
299 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
300 | } | |
8a4da6e3 | 301 | |
037f6377 WD |
302 | static void arch_timer_configure_evtstream(void) |
303 | { | |
304 | int evt_stream_div, pos; | |
305 | ||
306 | /* Find the closest power of two to the divisor */ | |
307 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
308 | pos = fls(evt_stream_div); | |
309 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
310 | pos--; | |
311 | /* enable event stream */ | |
312 | arch_timer_evtstrm_enable(min(pos, 15)); | |
313 | } | |
314 | ||
8b8dde00 NL |
315 | static void arch_counter_set_user_access(void) |
316 | { | |
317 | u32 cntkctl = arch_timer_get_cntkctl(); | |
318 | ||
319 | /* Disable user access to the timers and the physical counter */ | |
320 | /* Also disable virtual event stream */ | |
321 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
322 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
323 | | ARCH_TIMER_VIRT_EVT_EN | |
324 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
325 | ||
326 | /* Enable user access to the virtual counter */ | |
327 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
328 | ||
329 | arch_timer_set_cntkctl(cntkctl); | |
330 | } | |
331 | ||
cfb6d656 | 332 | static int arch_timer_setup(struct clock_event_device *clk) |
22006994 SB |
333 | { |
334 | __arch_timer_setup(ARCH_CP15_TIMER, clk); | |
8a4da6e3 MR |
335 | |
336 | if (arch_timer_use_virtual) | |
337 | enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0); | |
338 | else { | |
339 | enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0); | |
340 | if (arch_timer_ppi[PHYS_NONSECURE_PPI]) | |
341 | enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0); | |
342 | } | |
343 | ||
344 | arch_counter_set_user_access(); | |
037f6377 WD |
345 | if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM)) |
346 | arch_timer_configure_evtstream(); | |
8a4da6e3 MR |
347 | |
348 | return 0; | |
349 | } | |
350 | ||
22006994 SB |
351 | static void |
352 | arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) | |
8a4da6e3 | 353 | { |
22006994 SB |
354 | /* Who has more than one independent system counter? */ |
355 | if (arch_timer_rate) | |
356 | return; | |
8a4da6e3 | 357 | |
22006994 SB |
358 | /* Try to determine the frequency from the device tree or CNTFRQ */ |
359 | if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { | |
360 | if (cntbase) | |
361 | arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); | |
362 | else | |
363 | arch_timer_rate = arch_timer_get_cntfrq(); | |
8a4da6e3 MR |
364 | } |
365 | ||
22006994 SB |
366 | /* Check the timer frequency. */ |
367 | if (arch_timer_rate == 0) | |
368 | pr_warn("Architected timer frequency not available\n"); | |
369 | } | |
370 | ||
371 | static void arch_timer_banner(unsigned type) | |
372 | { | |
373 | pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", | |
374 | type & ARCH_CP15_TIMER ? "cp15" : "", | |
375 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "", | |
376 | type & ARCH_MEM_TIMER ? "mmio" : "", | |
8a4da6e3 MR |
377 | (unsigned long)arch_timer_rate / 1000000, |
378 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
22006994 SB |
379 | type & ARCH_CP15_TIMER ? |
380 | arch_timer_use_virtual ? "virt" : "phys" : | |
381 | "", | |
382 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "", | |
383 | type & ARCH_MEM_TIMER ? | |
384 | arch_timer_mem_use_virtual ? "virt" : "phys" : | |
385 | ""); | |
8a4da6e3 MR |
386 | } |
387 | ||
388 | u32 arch_timer_get_rate(void) | |
389 | { | |
390 | return arch_timer_rate; | |
391 | } | |
392 | ||
22006994 | 393 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 394 | { |
22006994 SB |
395 | u32 vct_lo, vct_hi, tmp_hi; |
396 | ||
397 | do { | |
398 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
399 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
400 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
401 | } while (vct_hi != tmp_hi); | |
402 | ||
403 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
404 | } |
405 | ||
22006994 SB |
406 | /* |
407 | * Default to cp15 based access because arm64 uses this function for | |
408 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
409 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
410 | * if we don't have the cp15 accessors we won't have a problem. | |
411 | */ | |
412 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
413 | ||
8a4da6e3 MR |
414 | static cycle_t arch_counter_read(struct clocksource *cs) |
415 | { | |
22006994 | 416 | return arch_timer_read_counter(); |
8a4da6e3 MR |
417 | } |
418 | ||
419 | static cycle_t arch_counter_read_cc(const struct cyclecounter *cc) | |
420 | { | |
22006994 | 421 | return arch_timer_read_counter(); |
8a4da6e3 MR |
422 | } |
423 | ||
424 | static struct clocksource clocksource_counter = { | |
425 | .name = "arch_sys_counter", | |
426 | .rating = 400, | |
427 | .read = arch_counter_read, | |
428 | .mask = CLOCKSOURCE_MASK(56), | |
4fbcdc81 | 429 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, |
8a4da6e3 MR |
430 | }; |
431 | ||
432 | static struct cyclecounter cyclecounter = { | |
433 | .read = arch_counter_read_cc, | |
434 | .mask = CLOCKSOURCE_MASK(56), | |
435 | }; | |
436 | ||
437 | static struct timecounter timecounter; | |
438 | ||
439 | struct timecounter *arch_timer_get_timecounter(void) | |
440 | { | |
441 | return &timecounter; | |
442 | } | |
443 | ||
22006994 SB |
444 | static void __init arch_counter_register(unsigned type) |
445 | { | |
446 | u64 start_count; | |
447 | ||
448 | /* Register the CP15 based counter if we have one */ | |
423bd69e | 449 | if (type & ARCH_CP15_TIMER) { |
22006994 | 450 | arch_timer_read_counter = arch_counter_get_cntvct; |
423bd69e | 451 | } else { |
22006994 SB |
452 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
453 | ||
423bd69e NL |
454 | /* If the clocksource name is "arch_sys_counter" the |
455 | * VDSO will attempt to read the CP15-based counter. | |
456 | * Ensure this does not happen when CP15-based | |
457 | * counter is not available. | |
458 | */ | |
459 | clocksource_counter.name = "arch_mem_counter"; | |
460 | } | |
461 | ||
22006994 SB |
462 | start_count = arch_timer_read_counter(); |
463 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
464 | cyclecounter.mult = clocksource_counter.mult; | |
465 | cyclecounter.shift = clocksource_counter.shift; | |
466 | timecounter_init(&timecounter, &cyclecounter, start_count); | |
4a7d3e8a TR |
467 | |
468 | /* 56 bits minimum, so we assume worst case rollover */ | |
469 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
470 | } |
471 | ||
8c37bb3a | 472 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 MR |
473 | { |
474 | pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", | |
475 | clk->irq, smp_processor_id()); | |
476 | ||
477 | if (arch_timer_use_virtual) | |
478 | disable_percpu_irq(arch_timer_ppi[VIRT_PPI]); | |
479 | else { | |
480 | disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]); | |
481 | if (arch_timer_ppi[PHYS_NONSECURE_PPI]) | |
482 | disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
483 | } | |
484 | ||
485 | clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk); | |
486 | } | |
487 | ||
8c37bb3a | 488 | static int arch_timer_cpu_notify(struct notifier_block *self, |
8a4da6e3 MR |
489 | unsigned long action, void *hcpu) |
490 | { | |
f31c2f1c SB |
491 | /* |
492 | * Grab cpu pointer in each case to avoid spurious | |
493 | * preemptible warnings | |
494 | */ | |
8a4da6e3 MR |
495 | switch (action & ~CPU_TASKS_FROZEN) { |
496 | case CPU_STARTING: | |
f31c2f1c | 497 | arch_timer_setup(this_cpu_ptr(arch_timer_evt)); |
8a4da6e3 MR |
498 | break; |
499 | case CPU_DYING: | |
f31c2f1c | 500 | arch_timer_stop(this_cpu_ptr(arch_timer_evt)); |
8a4da6e3 MR |
501 | break; |
502 | } | |
503 | ||
504 | return NOTIFY_OK; | |
505 | } | |
506 | ||
8c37bb3a | 507 | static struct notifier_block arch_timer_cpu_nb = { |
8a4da6e3 MR |
508 | .notifier_call = arch_timer_cpu_notify, |
509 | }; | |
510 | ||
346e7480 SH |
511 | #ifdef CONFIG_CPU_PM |
512 | static unsigned int saved_cntkctl; | |
513 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, | |
514 | unsigned long action, void *hcpu) | |
515 | { | |
516 | if (action == CPU_PM_ENTER) | |
517 | saved_cntkctl = arch_timer_get_cntkctl(); | |
518 | else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) | |
519 | arch_timer_set_cntkctl(saved_cntkctl); | |
520 | return NOTIFY_OK; | |
521 | } | |
522 | ||
523 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
524 | .notifier_call = arch_timer_cpu_pm_notify, | |
525 | }; | |
526 | ||
527 | static int __init arch_timer_cpu_pm_init(void) | |
528 | { | |
529 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
530 | } | |
531 | #else | |
532 | static int __init arch_timer_cpu_pm_init(void) | |
533 | { | |
534 | return 0; | |
535 | } | |
536 | #endif | |
537 | ||
8a4da6e3 MR |
538 | static int __init arch_timer_register(void) |
539 | { | |
540 | int err; | |
541 | int ppi; | |
542 | ||
8a4da6e3 MR |
543 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
544 | if (!arch_timer_evt) { | |
545 | err = -ENOMEM; | |
546 | goto out; | |
547 | } | |
548 | ||
8a4da6e3 MR |
549 | if (arch_timer_use_virtual) { |
550 | ppi = arch_timer_ppi[VIRT_PPI]; | |
551 | err = request_percpu_irq(ppi, arch_timer_handler_virt, | |
552 | "arch_timer", arch_timer_evt); | |
553 | } else { | |
554 | ppi = arch_timer_ppi[PHYS_SECURE_PPI]; | |
555 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
556 | "arch_timer", arch_timer_evt); | |
557 | if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) { | |
558 | ppi = arch_timer_ppi[PHYS_NONSECURE_PPI]; | |
559 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
560 | "arch_timer", arch_timer_evt); | |
561 | if (err) | |
562 | free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], | |
563 | arch_timer_evt); | |
564 | } | |
565 | } | |
566 | ||
567 | if (err) { | |
568 | pr_err("arch_timer: can't register interrupt %d (%d)\n", | |
569 | ppi, err); | |
570 | goto out_free; | |
571 | } | |
572 | ||
573 | err = register_cpu_notifier(&arch_timer_cpu_nb); | |
574 | if (err) | |
575 | goto out_free_irq; | |
576 | ||
346e7480 SH |
577 | err = arch_timer_cpu_pm_init(); |
578 | if (err) | |
579 | goto out_unreg_notify; | |
580 | ||
8a4da6e3 MR |
581 | /* Immediately configure the timer on the boot CPU */ |
582 | arch_timer_setup(this_cpu_ptr(arch_timer_evt)); | |
583 | ||
584 | return 0; | |
585 | ||
346e7480 SH |
586 | out_unreg_notify: |
587 | unregister_cpu_notifier(&arch_timer_cpu_nb); | |
8a4da6e3 MR |
588 | out_free_irq: |
589 | if (arch_timer_use_virtual) | |
590 | free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt); | |
591 | else { | |
592 | free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], | |
593 | arch_timer_evt); | |
594 | if (arch_timer_ppi[PHYS_NONSECURE_PPI]) | |
595 | free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], | |
596 | arch_timer_evt); | |
597 | } | |
598 | ||
599 | out_free: | |
600 | free_percpu(arch_timer_evt); | |
601 | out: | |
602 | return err; | |
603 | } | |
604 | ||
22006994 SB |
605 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
606 | { | |
607 | int ret; | |
608 | irq_handler_t func; | |
609 | struct arch_timer *t; | |
610 | ||
611 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
612 | if (!t) | |
613 | return -ENOMEM; | |
614 | ||
615 | t->base = base; | |
616 | t->evt.irq = irq; | |
617 | __arch_timer_setup(ARCH_MEM_TIMER, &t->evt); | |
618 | ||
619 | if (arch_timer_mem_use_virtual) | |
620 | func = arch_timer_handler_virt_mem; | |
621 | else | |
622 | func = arch_timer_handler_phys_mem; | |
623 | ||
624 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
625 | if (ret) { | |
626 | pr_err("arch_timer: Failed to request mem timer irq\n"); | |
627 | kfree(t); | |
628 | } | |
629 | ||
630 | return ret; | |
631 | } | |
632 | ||
633 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
634 | { .compatible = "arm,armv7-timer", }, | |
635 | { .compatible = "arm,armv8-timer", }, | |
636 | {}, | |
637 | }; | |
638 | ||
639 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
640 | { .compatible = "arm,armv7-timer-mem", }, | |
641 | {}, | |
642 | }; | |
643 | ||
c387f07e SH |
644 | static bool __init |
645 | arch_timer_probed(int type, const struct of_device_id *matches) | |
646 | { | |
647 | struct device_node *dn; | |
648 | bool probed = false; | |
649 | ||
650 | dn = of_find_matching_node(NULL, matches); | |
651 | if (dn && of_device_is_available(dn) && (arch_timers_present & type)) | |
652 | probed = true; | |
653 | of_node_put(dn); | |
654 | ||
655 | return probed; | |
656 | } | |
657 | ||
22006994 SB |
658 | static void __init arch_timer_common_init(void) |
659 | { | |
660 | unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER; | |
661 | ||
662 | /* Wait until both nodes are probed if we have two timers */ | |
663 | if ((arch_timers_present & mask) != mask) { | |
c387f07e | 664 | if (!arch_timer_probed(ARCH_MEM_TIMER, arch_timer_mem_of_match)) |
22006994 | 665 | return; |
c387f07e | 666 | if (!arch_timer_probed(ARCH_CP15_TIMER, arch_timer_of_match)) |
22006994 SB |
667 | return; |
668 | } | |
669 | ||
670 | arch_timer_banner(arch_timers_present); | |
671 | arch_counter_register(arch_timers_present); | |
672 | arch_timer_arch_init(); | |
673 | } | |
674 | ||
0583fe47 | 675 | static void __init arch_timer_init(struct device_node *np) |
8a4da6e3 | 676 | { |
8a4da6e3 MR |
677 | int i; |
678 | ||
22006994 | 679 | if (arch_timers_present & ARCH_CP15_TIMER) { |
0583fe47 RH |
680 | pr_warn("arch_timer: multiple nodes in dt, skipping\n"); |
681 | return; | |
8a4da6e3 MR |
682 | } |
683 | ||
22006994 | 684 | arch_timers_present |= ARCH_CP15_TIMER; |
8a4da6e3 MR |
685 | for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) |
686 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); | |
22006994 | 687 | arch_timer_detect_rate(NULL, np); |
8a4da6e3 MR |
688 | |
689 | /* | |
8266891e MZ |
690 | * If HYP mode is available, we know that the physical timer |
691 | * has been configured to be accessible from PL1. Use it, so | |
692 | * that a guest can use the virtual timer instead. | |
693 | * | |
8a4da6e3 MR |
694 | * If no interrupt provided for virtual timer, we'll have to |
695 | * stick to the physical timer. It'd better be accessible... | |
696 | */ | |
8266891e | 697 | if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { |
8a4da6e3 MR |
698 | arch_timer_use_virtual = false; |
699 | ||
700 | if (!arch_timer_ppi[PHYS_SECURE_PPI] || | |
701 | !arch_timer_ppi[PHYS_NONSECURE_PPI]) { | |
702 | pr_warn("arch_timer: No interrupt available, giving up\n"); | |
0583fe47 | 703 | return; |
8a4da6e3 MR |
704 | } |
705 | } | |
706 | ||
82a56194 LP |
707 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); |
708 | ||
0583fe47 | 709 | arch_timer_register(); |
22006994 | 710 | arch_timer_common_init(); |
8a4da6e3 | 711 | } |
0583fe47 RH |
712 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init); |
713 | CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init); | |
22006994 SB |
714 | |
715 | static void __init arch_timer_mem_init(struct device_node *np) | |
716 | { | |
717 | struct device_node *frame, *best_frame = NULL; | |
718 | void __iomem *cntctlbase, *base; | |
719 | unsigned int irq; | |
720 | u32 cnttidr; | |
721 | ||
722 | arch_timers_present |= ARCH_MEM_TIMER; | |
723 | cntctlbase = of_iomap(np, 0); | |
724 | if (!cntctlbase) { | |
725 | pr_err("arch_timer: Can't find CNTCTLBase\n"); | |
726 | return; | |
727 | } | |
728 | ||
729 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
730 | iounmap(cntctlbase); | |
731 | ||
732 | /* | |
733 | * Try to find a virtual capable frame. Otherwise fall back to a | |
734 | * physical capable frame. | |
735 | */ | |
736 | for_each_available_child_of_node(np, frame) { | |
737 | int n; | |
738 | ||
739 | if (of_property_read_u32(frame, "frame-number", &n)) { | |
740 | pr_err("arch_timer: Missing frame-number\n"); | |
741 | of_node_put(best_frame); | |
742 | of_node_put(frame); | |
743 | return; | |
744 | } | |
745 | ||
746 | if (cnttidr & CNTTIDR_VIRT(n)) { | |
747 | of_node_put(best_frame); | |
748 | best_frame = frame; | |
749 | arch_timer_mem_use_virtual = true; | |
750 | break; | |
751 | } | |
752 | of_node_put(best_frame); | |
753 | best_frame = of_node_get(frame); | |
754 | } | |
755 | ||
756 | base = arch_counter_base = of_iomap(best_frame, 0); | |
757 | if (!base) { | |
758 | pr_err("arch_timer: Can't map frame's registers\n"); | |
759 | of_node_put(best_frame); | |
760 | return; | |
761 | } | |
762 | ||
763 | if (arch_timer_mem_use_virtual) | |
764 | irq = irq_of_parse_and_map(best_frame, 1); | |
765 | else | |
766 | irq = irq_of_parse_and_map(best_frame, 0); | |
767 | of_node_put(best_frame); | |
768 | if (!irq) { | |
769 | pr_err("arch_timer: Frame missing %s irq", | |
cfb6d656 | 770 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
22006994 SB |
771 | return; |
772 | } | |
773 | ||
774 | arch_timer_detect_rate(base, np); | |
775 | arch_timer_mem_register(base, irq); | |
776 | arch_timer_common_init(); | |
777 | } | |
778 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", | |
779 | arch_timer_mem_init); |