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Commit | Line | Data |
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8a4da6e3 MR |
1 | /* |
2 | * linux/drivers/clocksource/arm_arch_timer.c | |
3 | * | |
4 | * Copyright (C) 2011 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
f005bd7e MZ |
11 | |
12 | #define pr_fmt(fmt) "arm_arch_timer: " fmt | |
13 | ||
8a4da6e3 MR |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/cpu.h> | |
346e7480 | 19 | #include <linux/cpu_pm.h> |
8a4da6e3 | 20 | #include <linux/clockchips.h> |
7c8f1e78 | 21 | #include <linux/clocksource.h> |
8a4da6e3 MR |
22 | #include <linux/interrupt.h> |
23 | #include <linux/of_irq.h> | |
22006994 | 24 | #include <linux/of_address.h> |
8a4da6e3 | 25 | #include <linux/io.h> |
22006994 | 26 | #include <linux/slab.h> |
e6017571 | 27 | #include <linux/sched/clock.h> |
65cd4f6c | 28 | #include <linux/sched_clock.h> |
b09ca1ec | 29 | #include <linux/acpi.h> |
8a4da6e3 MR |
30 | |
31 | #include <asm/arch_timer.h> | |
8266891e | 32 | #include <asm/virt.h> |
8a4da6e3 MR |
33 | |
34 | #include <clocksource/arm_arch_timer.h> | |
35 | ||
22006994 SB |
36 | #define CNTTIDR 0x08 |
37 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
38 | ||
e392d603 RM |
39 | #define CNTACR(n) (0x40 + ((n) * 4)) |
40 | #define CNTACR_RPCT BIT(0) | |
41 | #define CNTACR_RVCT BIT(1) | |
42 | #define CNTACR_RFRQ BIT(2) | |
43 | #define CNTACR_RVOFF BIT(3) | |
44 | #define CNTACR_RWVT BIT(4) | |
45 | #define CNTACR_RWPT BIT(5) | |
46 | ||
22006994 SB |
47 | #define CNTVCT_LO 0x08 |
48 | #define CNTVCT_HI 0x0c | |
49 | #define CNTFRQ 0x10 | |
50 | #define CNTP_TVAL 0x28 | |
51 | #define CNTP_CTL 0x2c | |
52 | #define CNTV_TVAL 0x38 | |
53 | #define CNTV_CTL 0x3c | |
54 | ||
55 | #define ARCH_CP15_TIMER BIT(0) | |
56 | #define ARCH_MEM_TIMER BIT(1) | |
57 | static unsigned arch_timers_present __initdata; | |
58 | ||
59 | static void __iomem *arch_counter_base; | |
60 | ||
61 | struct arch_timer { | |
62 | void __iomem *base; | |
63 | struct clock_event_device evt; | |
64 | }; | |
65 | ||
66 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
67 | ||
8a4da6e3 MR |
68 | static u32 arch_timer_rate; |
69 | ||
70 | enum ppi_nr { | |
71 | PHYS_SECURE_PPI, | |
72 | PHYS_NONSECURE_PPI, | |
73 | VIRT_PPI, | |
74 | HYP_PPI, | |
75 | MAX_TIMER_PPI | |
76 | }; | |
77 | ||
78 | static int arch_timer_ppi[MAX_TIMER_PPI]; | |
79 | ||
80 | static struct clock_event_device __percpu *arch_timer_evt; | |
81 | ||
f81f03fa | 82 | static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI; |
82a56194 | 83 | static bool arch_timer_c3stop; |
22006994 | 84 | static bool arch_timer_mem_use_virtual; |
d8ec7595 | 85 | static bool arch_counter_suspend_stop; |
8a4da6e3 | 86 | |
46fd5c6b WD |
87 | static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); |
88 | ||
89 | static int __init early_evtstrm_cfg(char *buf) | |
90 | { | |
91 | return strtobool(buf, &evtstrm_enable); | |
92 | } | |
93 | early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); | |
94 | ||
8a4da6e3 MR |
95 | /* |
96 | * Architected system timer support. | |
97 | */ | |
98 | ||
f4e00a1a MZ |
99 | static __always_inline |
100 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
101 | struct clock_event_device *clk) | |
102 | { | |
103 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
104 | struct arch_timer *timer = to_arch_timer(clk); | |
105 | switch (reg) { | |
106 | case ARCH_TIMER_REG_CTRL: | |
107 | writel_relaxed(val, timer->base + CNTP_CTL); | |
108 | break; | |
109 | case ARCH_TIMER_REG_TVAL: | |
110 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
111 | break; | |
112 | } | |
113 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
114 | struct arch_timer *timer = to_arch_timer(clk); | |
115 | switch (reg) { | |
116 | case ARCH_TIMER_REG_CTRL: | |
117 | writel_relaxed(val, timer->base + CNTV_CTL); | |
118 | break; | |
119 | case ARCH_TIMER_REG_TVAL: | |
120 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
121 | break; | |
122 | } | |
123 | } else { | |
124 | arch_timer_reg_write_cp15(access, reg, val); | |
125 | } | |
126 | } | |
127 | ||
128 | static __always_inline | |
129 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
130 | struct clock_event_device *clk) | |
131 | { | |
132 | u32 val; | |
133 | ||
134 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
135 | struct arch_timer *timer = to_arch_timer(clk); | |
136 | switch (reg) { | |
137 | case ARCH_TIMER_REG_CTRL: | |
138 | val = readl_relaxed(timer->base + CNTP_CTL); | |
139 | break; | |
140 | case ARCH_TIMER_REG_TVAL: | |
141 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
142 | break; | |
143 | } | |
144 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
145 | struct arch_timer *timer = to_arch_timer(clk); | |
146 | switch (reg) { | |
147 | case ARCH_TIMER_REG_CTRL: | |
148 | val = readl_relaxed(timer->base + CNTV_CTL); | |
149 | break; | |
150 | case ARCH_TIMER_REG_TVAL: | |
151 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
152 | break; | |
153 | } | |
154 | } else { | |
155 | val = arch_timer_reg_read_cp15(access, reg); | |
156 | } | |
157 | ||
158 | return val; | |
159 | } | |
160 | ||
f6dc1576 | 161 | #ifdef CONFIG_FSL_ERRATUM_A008585 |
16d10ef2 DT |
162 | /* |
163 | * The number of retries is an arbitrary value well beyond the highest number | |
164 | * of iterations the loop has been observed to take. | |
165 | */ | |
166 | #define __fsl_a008585_read_reg(reg) ({ \ | |
167 | u64 _old, _new; \ | |
168 | int _retries = 200; \ | |
169 | \ | |
170 | do { \ | |
171 | _old = read_sysreg(reg); \ | |
172 | _new = read_sysreg(reg); \ | |
173 | _retries--; \ | |
174 | } while (unlikely(_old != _new) && _retries); \ | |
175 | \ | |
176 | WARN_ON_ONCE(!_retries); \ | |
177 | _new; \ | |
178 | }) | |
179 | ||
180 | static u32 notrace fsl_a008585_read_cntp_tval_el0(void) | |
f6dc1576 SW |
181 | { |
182 | return __fsl_a008585_read_reg(cntp_tval_el0); | |
183 | } | |
184 | ||
16d10ef2 | 185 | static u32 notrace fsl_a008585_read_cntv_tval_el0(void) |
f6dc1576 SW |
186 | { |
187 | return __fsl_a008585_read_reg(cntv_tval_el0); | |
188 | } | |
189 | ||
16d10ef2 | 190 | static u64 notrace fsl_a008585_read_cntvct_el0(void) |
f6dc1576 SW |
191 | { |
192 | return __fsl_a008585_read_reg(cntvct_el0); | |
193 | } | |
16d10ef2 DT |
194 | #endif |
195 | ||
bb42ca47 DT |
196 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
197 | /* | |
198 | * Verify whether the value of the second read is larger than the first by | |
199 | * less than 32 is the only way to confirm the value is correct, so clear the | |
200 | * lower 5 bits to check whether the difference is greater than 32 or not. | |
201 | * Theoretically the erratum should not occur more than twice in succession | |
202 | * when reading the system counter, but it is possible that some interrupts | |
203 | * may lead to more than twice read errors, triggering the warning, so setting | |
204 | * the number of retries far beyond the number of iterations the loop has been | |
205 | * observed to take. | |
206 | */ | |
207 | #define __hisi_161010101_read_reg(reg) ({ \ | |
208 | u64 _old, _new; \ | |
209 | int _retries = 50; \ | |
210 | \ | |
211 | do { \ | |
212 | _old = read_sysreg(reg); \ | |
213 | _new = read_sysreg(reg); \ | |
214 | _retries--; \ | |
215 | } while (unlikely((_new - _old) >> 5) && _retries); \ | |
216 | \ | |
217 | WARN_ON_ONCE(!_retries); \ | |
218 | _new; \ | |
219 | }) | |
220 | ||
221 | static u32 notrace hisi_161010101_read_cntp_tval_el0(void) | |
222 | { | |
223 | return __hisi_161010101_read_reg(cntp_tval_el0); | |
224 | } | |
225 | ||
226 | static u32 notrace hisi_161010101_read_cntv_tval_el0(void) | |
227 | { | |
228 | return __hisi_161010101_read_reg(cntv_tval_el0); | |
229 | } | |
230 | ||
231 | static u64 notrace hisi_161010101_read_cntvct_el0(void) | |
232 | { | |
233 | return __hisi_161010101_read_reg(cntvct_el0); | |
234 | } | |
235 | #endif | |
236 | ||
16d10ef2 DT |
237 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
238 | const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL; | |
239 | EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); | |
240 | ||
241 | DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); | |
242 | EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled); | |
243 | ||
8328089f MZ |
244 | static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, |
245 | struct clock_event_device *clk) | |
246 | { | |
247 | unsigned long ctrl; | |
248 | u64 cval = evt + arch_counter_get_cntvct(); | |
249 | ||
250 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
251 | ctrl |= ARCH_TIMER_CTRL_ENABLE; | |
252 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
253 | ||
254 | if (access == ARCH_TIMER_PHYS_ACCESS) | |
255 | write_sysreg(cval, cntp_cval_el0); | |
256 | else | |
257 | write_sysreg(cval, cntv_cval_el0); | |
258 | ||
259 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
260 | } | |
261 | ||
262 | static int erratum_set_next_event_tval_virt(unsigned long evt, | |
263 | struct clock_event_device *clk) | |
264 | { | |
265 | erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk); | |
266 | return 0; | |
267 | } | |
268 | ||
269 | static int erratum_set_next_event_tval_phys(unsigned long evt, | |
270 | struct clock_event_device *clk) | |
271 | { | |
272 | erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk); | |
273 | return 0; | |
274 | } | |
275 | ||
16d10ef2 DT |
276 | static const struct arch_timer_erratum_workaround ool_workarounds[] = { |
277 | #ifdef CONFIG_FSL_ERRATUM_A008585 | |
278 | { | |
651bb2e9 | 279 | .match_type = ate_match_dt, |
16d10ef2 | 280 | .id = "fsl,erratum-a008585", |
651bb2e9 | 281 | .desc = "Freescale erratum a005858", |
16d10ef2 DT |
282 | .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, |
283 | .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, | |
284 | .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, | |
01d3e3ff MZ |
285 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
286 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
16d10ef2 DT |
287 | }, |
288 | #endif | |
bb42ca47 DT |
289 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
290 | { | |
651bb2e9 | 291 | .match_type = ate_match_dt, |
bb42ca47 | 292 | .id = "hisilicon,erratum-161010101", |
651bb2e9 | 293 | .desc = "HiSilicon erratum 161010101", |
bb42ca47 DT |
294 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, |
295 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
296 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
01d3e3ff MZ |
297 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
298 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
bb42ca47 DT |
299 | }, |
300 | #endif | |
16d10ef2 | 301 | }; |
651bb2e9 MZ |
302 | |
303 | typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, | |
304 | const void *); | |
305 | ||
306 | static | |
307 | bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa, | |
308 | const void *arg) | |
309 | { | |
310 | const struct device_node *np = arg; | |
311 | ||
312 | return of_property_read_bool(np, wa->id); | |
313 | } | |
314 | ||
0064030c MZ |
315 | static |
316 | bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
317 | const void *arg) | |
318 | { | |
319 | return this_cpu_has_cap((uintptr_t)wa->id); | |
320 | } | |
321 | ||
651bb2e9 MZ |
322 | static const struct arch_timer_erratum_workaround * |
323 | arch_timer_iterate_errata(enum arch_timer_erratum_match_type type, | |
324 | ate_match_fn_t match_fn, | |
325 | void *arg) | |
326 | { | |
327 | int i; | |
328 | ||
329 | for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { | |
330 | if (ool_workarounds[i].match_type != type) | |
331 | continue; | |
332 | ||
333 | if (match_fn(&ool_workarounds[i], arg)) | |
334 | return &ool_workarounds[i]; | |
335 | } | |
336 | ||
337 | return NULL; | |
338 | } | |
339 | ||
340 | static | |
341 | void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa) | |
342 | { | |
343 | timer_unstable_counter_workaround = wa; | |
344 | static_branch_enable(&arch_timer_read_ool_enabled); | |
345 | } | |
346 | ||
347 | static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type, | |
348 | void *arg) | |
349 | { | |
350 | const struct arch_timer_erratum_workaround *wa; | |
351 | ate_match_fn_t match_fn = NULL; | |
0064030c | 352 | bool local = false; |
651bb2e9 MZ |
353 | |
354 | switch (type) { | |
355 | case ate_match_dt: | |
356 | match_fn = arch_timer_check_dt_erratum; | |
357 | break; | |
0064030c MZ |
358 | case ate_match_local_cap_id: |
359 | match_fn = arch_timer_check_local_cap_erratum; | |
360 | local = true; | |
361 | break; | |
651bb2e9 MZ |
362 | default: |
363 | WARN_ON(1); | |
364 | return; | |
365 | } | |
366 | ||
367 | wa = arch_timer_iterate_errata(type, match_fn, arg); | |
368 | if (!wa) | |
369 | return; | |
370 | ||
0064030c MZ |
371 | if (needs_unstable_timer_counter_workaround()) { |
372 | if (wa != timer_unstable_counter_workaround) | |
373 | pr_warn("Can't enable workaround for %s (clashes with %s\n)", | |
374 | wa->desc, | |
375 | timer_unstable_counter_workaround->desc); | |
376 | return; | |
377 | } | |
378 | ||
651bb2e9 | 379 | arch_timer_enable_workaround(wa); |
0064030c MZ |
380 | pr_info("Enabling %s workaround for %s\n", |
381 | local ? "local" : "global", wa->desc); | |
651bb2e9 MZ |
382 | } |
383 | ||
01d3e3ff MZ |
384 | #define erratum_handler(fn, r, ...) \ |
385 | ({ \ | |
386 | bool __val; \ | |
387 | if (needs_unstable_timer_counter_workaround() && \ | |
388 | timer_unstable_counter_workaround->fn) { \ | |
389 | r = timer_unstable_counter_workaround->fn(__VA_ARGS__); \ | |
390 | __val = true; \ | |
391 | } else { \ | |
392 | __val = false; \ | |
393 | } \ | |
394 | __val; \ | |
395 | }) | |
396 | ||
651bb2e9 MZ |
397 | #else |
398 | #define arch_timer_check_ool_workaround(t,a) do { } while(0) | |
8328089f MZ |
399 | #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;}) |
400 | #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;}) | |
01d3e3ff | 401 | #define erratum_handler(fn, r, ...) ({false;}) |
16d10ef2 | 402 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ |
f6dc1576 | 403 | |
e09f3cc0 | 404 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
405 | struct clock_event_device *evt) |
406 | { | |
407 | unsigned long ctrl; | |
cfb6d656 | 408 | |
60faddf6 | 409 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
410 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
411 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 412 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
413 | evt->event_handler(evt); |
414 | return IRQ_HANDLED; | |
415 | } | |
416 | ||
417 | return IRQ_NONE; | |
418 | } | |
419 | ||
420 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
421 | { | |
422 | struct clock_event_device *evt = dev_id; | |
423 | ||
424 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
425 | } | |
426 | ||
427 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
428 | { | |
429 | struct clock_event_device *evt = dev_id; | |
430 | ||
431 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
432 | } | |
433 | ||
22006994 SB |
434 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
435 | { | |
436 | struct clock_event_device *evt = dev_id; | |
437 | ||
438 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
439 | } | |
440 | ||
441 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
442 | { | |
443 | struct clock_event_device *evt = dev_id; | |
444 | ||
445 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
446 | } | |
447 | ||
46c5bfdd VK |
448 | static __always_inline int timer_shutdown(const int access, |
449 | struct clock_event_device *clk) | |
8a4da6e3 MR |
450 | { |
451 | unsigned long ctrl; | |
46c5bfdd VK |
452 | |
453 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
454 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; | |
455 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
456 | ||
457 | return 0; | |
8a4da6e3 MR |
458 | } |
459 | ||
46c5bfdd | 460 | static int arch_timer_shutdown_virt(struct clock_event_device *clk) |
8a4da6e3 | 461 | { |
46c5bfdd | 462 | return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk); |
8a4da6e3 MR |
463 | } |
464 | ||
46c5bfdd | 465 | static int arch_timer_shutdown_phys(struct clock_event_device *clk) |
8a4da6e3 | 466 | { |
46c5bfdd | 467 | return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); |
8a4da6e3 MR |
468 | } |
469 | ||
46c5bfdd | 470 | static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) |
22006994 | 471 | { |
46c5bfdd | 472 | return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); |
8a4da6e3 MR |
473 | } |
474 | ||
46c5bfdd | 475 | static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) |
22006994 | 476 | { |
46c5bfdd | 477 | return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); |
22006994 SB |
478 | } |
479 | ||
60faddf6 | 480 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 481 | struct clock_event_device *clk) |
8a4da6e3 MR |
482 | { |
483 | unsigned long ctrl; | |
60faddf6 | 484 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
485 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
486 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
487 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
488 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
489 | } |
490 | ||
491 | static int arch_timer_set_next_event_virt(unsigned long evt, | |
60faddf6 | 492 | struct clock_event_device *clk) |
8a4da6e3 | 493 | { |
01d3e3ff MZ |
494 | int ret; |
495 | ||
496 | if (erratum_handler(set_next_event_virt, ret, evt, clk)) | |
497 | return ret; | |
8328089f | 498 | |
60faddf6 | 499 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
500 | return 0; |
501 | } | |
502 | ||
503 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 504 | struct clock_event_device *clk) |
8a4da6e3 | 505 | { |
01d3e3ff MZ |
506 | int ret; |
507 | ||
508 | if (erratum_handler(set_next_event_phys, ret, evt, clk)) | |
509 | return ret; | |
8328089f | 510 | |
60faddf6 | 511 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
512 | return 0; |
513 | } | |
514 | ||
22006994 SB |
515 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
516 | struct clock_event_device *clk) | |
8a4da6e3 | 517 | { |
22006994 SB |
518 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
519 | return 0; | |
520 | } | |
521 | ||
522 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
523 | struct clock_event_device *clk) | |
524 | { | |
525 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
526 | return 0; | |
527 | } | |
528 | ||
cfb6d656 TG |
529 | static void __arch_timer_setup(unsigned type, |
530 | struct clock_event_device *clk) | |
22006994 SB |
531 | { |
532 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
533 | ||
534 | if (type == ARCH_CP15_TIMER) { | |
82a56194 LP |
535 | if (arch_timer_c3stop) |
536 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
537 | clk->name = "arch_sys_timer"; |
538 | clk->rating = 450; | |
539 | clk->cpumask = cpumask_of(smp_processor_id()); | |
f81f03fa MZ |
540 | clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; |
541 | switch (arch_timer_uses_ppi) { | |
542 | case VIRT_PPI: | |
46c5bfdd | 543 | clk->set_state_shutdown = arch_timer_shutdown_virt; |
cf8c5009 | 544 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; |
22006994 | 545 | clk->set_next_event = arch_timer_set_next_event_virt; |
f81f03fa MZ |
546 | break; |
547 | case PHYS_SECURE_PPI: | |
548 | case PHYS_NONSECURE_PPI: | |
549 | case HYP_PPI: | |
46c5bfdd | 550 | clk->set_state_shutdown = arch_timer_shutdown_phys; |
cf8c5009 | 551 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; |
22006994 | 552 | clk->set_next_event = arch_timer_set_next_event_phys; |
f81f03fa MZ |
553 | break; |
554 | default: | |
555 | BUG(); | |
22006994 | 556 | } |
f6dc1576 | 557 | |
0064030c | 558 | arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); |
8a4da6e3 | 559 | } else { |
7b52ad2e | 560 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
561 | clk->name = "arch_mem_timer"; |
562 | clk->rating = 400; | |
563 | clk->cpumask = cpu_all_mask; | |
564 | if (arch_timer_mem_use_virtual) { | |
46c5bfdd | 565 | clk->set_state_shutdown = arch_timer_shutdown_virt_mem; |
cf8c5009 | 566 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; |
22006994 SB |
567 | clk->set_next_event = |
568 | arch_timer_set_next_event_virt_mem; | |
569 | } else { | |
46c5bfdd | 570 | clk->set_state_shutdown = arch_timer_shutdown_phys_mem; |
cf8c5009 | 571 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; |
22006994 SB |
572 | clk->set_next_event = |
573 | arch_timer_set_next_event_phys_mem; | |
574 | } | |
8a4da6e3 MR |
575 | } |
576 | ||
46c5bfdd | 577 | clk->set_state_shutdown(clk); |
8a4da6e3 | 578 | |
22006994 SB |
579 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
580 | } | |
8a4da6e3 | 581 | |
e1ce5c7a NL |
582 | static void arch_timer_evtstrm_enable(int divider) |
583 | { | |
584 | u32 cntkctl = arch_timer_get_cntkctl(); | |
585 | ||
586 | cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; | |
587 | /* Set the divider and enable virtual event stream */ | |
588 | cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | |
589 | | ARCH_TIMER_VIRT_EVT_EN; | |
590 | arch_timer_set_cntkctl(cntkctl); | |
591 | elf_hwcap |= HWCAP_EVTSTRM; | |
592 | #ifdef CONFIG_COMPAT | |
593 | compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; | |
594 | #endif | |
595 | } | |
596 | ||
037f6377 WD |
597 | static void arch_timer_configure_evtstream(void) |
598 | { | |
599 | int evt_stream_div, pos; | |
600 | ||
601 | /* Find the closest power of two to the divisor */ | |
602 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
603 | pos = fls(evt_stream_div); | |
604 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
605 | pos--; | |
606 | /* enable event stream */ | |
607 | arch_timer_evtstrm_enable(min(pos, 15)); | |
608 | } | |
609 | ||
8b8dde00 NL |
610 | static void arch_counter_set_user_access(void) |
611 | { | |
612 | u32 cntkctl = arch_timer_get_cntkctl(); | |
613 | ||
614 | /* Disable user access to the timers and the physical counter */ | |
615 | /* Also disable virtual event stream */ | |
616 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
617 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
618 | | ARCH_TIMER_VIRT_EVT_EN | |
619 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
620 | ||
621 | /* Enable user access to the virtual counter */ | |
622 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
623 | ||
624 | arch_timer_set_cntkctl(cntkctl); | |
625 | } | |
626 | ||
f81f03fa MZ |
627 | static bool arch_timer_has_nonsecure_ppi(void) |
628 | { | |
629 | return (arch_timer_uses_ppi == PHYS_SECURE_PPI && | |
630 | arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
631 | } | |
632 | ||
f005bd7e MZ |
633 | static u32 check_ppi_trigger(int irq) |
634 | { | |
635 | u32 flags = irq_get_trigger_type(irq); | |
636 | ||
637 | if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { | |
638 | pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); | |
639 | pr_warn("WARNING: Please fix your firmware\n"); | |
640 | flags = IRQF_TRIGGER_LOW; | |
641 | } | |
642 | ||
643 | return flags; | |
644 | } | |
645 | ||
7e86e8bd | 646 | static int arch_timer_starting_cpu(unsigned int cpu) |
22006994 | 647 | { |
7e86e8bd | 648 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
f005bd7e | 649 | u32 flags; |
7e86e8bd | 650 | |
22006994 | 651 | __arch_timer_setup(ARCH_CP15_TIMER, clk); |
8a4da6e3 | 652 | |
f005bd7e MZ |
653 | flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); |
654 | enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); | |
f81f03fa | 655 | |
f005bd7e MZ |
656 | if (arch_timer_has_nonsecure_ppi()) { |
657 | flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
658 | enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags); | |
659 | } | |
8a4da6e3 MR |
660 | |
661 | arch_counter_set_user_access(); | |
46fd5c6b | 662 | if (evtstrm_enable) |
037f6377 | 663 | arch_timer_configure_evtstream(); |
8a4da6e3 MR |
664 | |
665 | return 0; | |
666 | } | |
667 | ||
22006994 SB |
668 | static void |
669 | arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) | |
8a4da6e3 | 670 | { |
22006994 SB |
671 | /* Who has more than one independent system counter? */ |
672 | if (arch_timer_rate) | |
673 | return; | |
8a4da6e3 | 674 | |
b09ca1ec HG |
675 | /* |
676 | * Try to determine the frequency from the device tree or CNTFRQ, | |
677 | * if ACPI is enabled, get the frequency from CNTFRQ ONLY. | |
678 | */ | |
679 | if (!acpi_disabled || | |
680 | of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { | |
22006994 SB |
681 | if (cntbase) |
682 | arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); | |
683 | else | |
684 | arch_timer_rate = arch_timer_get_cntfrq(); | |
8a4da6e3 MR |
685 | } |
686 | ||
22006994 SB |
687 | /* Check the timer frequency. */ |
688 | if (arch_timer_rate == 0) | |
689 | pr_warn("Architected timer frequency not available\n"); | |
690 | } | |
691 | ||
692 | static void arch_timer_banner(unsigned type) | |
693 | { | |
694 | pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", | |
695 | type & ARCH_CP15_TIMER ? "cp15" : "", | |
696 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "", | |
697 | type & ARCH_MEM_TIMER ? "mmio" : "", | |
8a4da6e3 MR |
698 | (unsigned long)arch_timer_rate / 1000000, |
699 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
22006994 | 700 | type & ARCH_CP15_TIMER ? |
f81f03fa | 701 | (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" : |
22006994 SB |
702 | "", |
703 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "", | |
704 | type & ARCH_MEM_TIMER ? | |
705 | arch_timer_mem_use_virtual ? "virt" : "phys" : | |
706 | ""); | |
8a4da6e3 MR |
707 | } |
708 | ||
709 | u32 arch_timer_get_rate(void) | |
710 | { | |
711 | return arch_timer_rate; | |
712 | } | |
713 | ||
22006994 | 714 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 715 | { |
22006994 SB |
716 | u32 vct_lo, vct_hi, tmp_hi; |
717 | ||
718 | do { | |
719 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
720 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
721 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
722 | } while (vct_hi != tmp_hi); | |
723 | ||
724 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
725 | } |
726 | ||
22006994 SB |
727 | /* |
728 | * Default to cp15 based access because arm64 uses this function for | |
729 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
730 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
731 | * if we don't have the cp15 accessors we won't have a problem. | |
732 | */ | |
733 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
734 | ||
a5a1d1c2 | 735 | static u64 arch_counter_read(struct clocksource *cs) |
8a4da6e3 | 736 | { |
22006994 | 737 | return arch_timer_read_counter(); |
8a4da6e3 MR |
738 | } |
739 | ||
a5a1d1c2 | 740 | static u64 arch_counter_read_cc(const struct cyclecounter *cc) |
8a4da6e3 | 741 | { |
22006994 | 742 | return arch_timer_read_counter(); |
8a4da6e3 MR |
743 | } |
744 | ||
745 | static struct clocksource clocksource_counter = { | |
746 | .name = "arch_sys_counter", | |
747 | .rating = 400, | |
748 | .read = arch_counter_read, | |
749 | .mask = CLOCKSOURCE_MASK(56), | |
d8ec7595 | 750 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8a4da6e3 MR |
751 | }; |
752 | ||
3d837bc0 | 753 | static struct cyclecounter cyclecounter __ro_after_init = { |
8a4da6e3 MR |
754 | .read = arch_counter_read_cc, |
755 | .mask = CLOCKSOURCE_MASK(56), | |
756 | }; | |
757 | ||
b4d6ce97 JG |
758 | static struct arch_timer_kvm_info arch_timer_kvm_info; |
759 | ||
760 | struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) | |
761 | { | |
762 | return &arch_timer_kvm_info; | |
763 | } | |
8a4da6e3 | 764 | |
22006994 SB |
765 | static void __init arch_counter_register(unsigned type) |
766 | { | |
767 | u64 start_count; | |
768 | ||
769 | /* Register the CP15 based counter if we have one */ | |
423bd69e | 770 | if (type & ARCH_CP15_TIMER) { |
f81f03fa | 771 | if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI) |
0b46b8a7 SR |
772 | arch_timer_read_counter = arch_counter_get_cntvct; |
773 | else | |
774 | arch_timer_read_counter = arch_counter_get_cntpct; | |
f6dc1576 | 775 | |
1d8f51d4 SW |
776 | clocksource_counter.archdata.vdso_direct = true; |
777 | ||
16d10ef2 | 778 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
f6dc1576 SW |
779 | /* |
780 | * Don't use the vdso fastpath if errata require using | |
781 | * the out-of-line counter accessor. | |
782 | */ | |
783 | if (static_branch_unlikely(&arch_timer_read_ool_enabled)) | |
1d8f51d4 | 784 | clocksource_counter.archdata.vdso_direct = false; |
f6dc1576 | 785 | #endif |
423bd69e | 786 | } else { |
22006994 | 787 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
423bd69e NL |
788 | } |
789 | ||
d8ec7595 BN |
790 | if (!arch_counter_suspend_stop) |
791 | clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
22006994 SB |
792 | start_count = arch_timer_read_counter(); |
793 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
794 | cyclecounter.mult = clocksource_counter.mult; | |
795 | cyclecounter.shift = clocksource_counter.shift; | |
b4d6ce97 JG |
796 | timecounter_init(&arch_timer_kvm_info.timecounter, |
797 | &cyclecounter, start_count); | |
4a7d3e8a TR |
798 | |
799 | /* 56 bits minimum, so we assume worst case rollover */ | |
800 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
801 | } |
802 | ||
8c37bb3a | 803 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 MR |
804 | { |
805 | pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", | |
806 | clk->irq, smp_processor_id()); | |
807 | ||
f81f03fa MZ |
808 | disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]); |
809 | if (arch_timer_has_nonsecure_ppi()) | |
810 | disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
8a4da6e3 | 811 | |
46c5bfdd | 812 | clk->set_state_shutdown(clk); |
8a4da6e3 MR |
813 | } |
814 | ||
7e86e8bd | 815 | static int arch_timer_dying_cpu(unsigned int cpu) |
8a4da6e3 | 816 | { |
7e86e8bd | 817 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
8a4da6e3 | 818 | |
7e86e8bd RC |
819 | arch_timer_stop(clk); |
820 | return 0; | |
8a4da6e3 MR |
821 | } |
822 | ||
346e7480 SH |
823 | #ifdef CONFIG_CPU_PM |
824 | static unsigned int saved_cntkctl; | |
825 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, | |
826 | unsigned long action, void *hcpu) | |
827 | { | |
828 | if (action == CPU_PM_ENTER) | |
829 | saved_cntkctl = arch_timer_get_cntkctl(); | |
830 | else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) | |
831 | arch_timer_set_cntkctl(saved_cntkctl); | |
832 | return NOTIFY_OK; | |
833 | } | |
834 | ||
835 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
836 | .notifier_call = arch_timer_cpu_pm_notify, | |
837 | }; | |
838 | ||
839 | static int __init arch_timer_cpu_pm_init(void) | |
840 | { | |
841 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
842 | } | |
7e86e8bd RC |
843 | |
844 | static void __init arch_timer_cpu_pm_deinit(void) | |
845 | { | |
846 | WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier)); | |
847 | } | |
848 | ||
346e7480 SH |
849 | #else |
850 | static int __init arch_timer_cpu_pm_init(void) | |
851 | { | |
852 | return 0; | |
853 | } | |
7e86e8bd RC |
854 | |
855 | static void __init arch_timer_cpu_pm_deinit(void) | |
856 | { | |
857 | } | |
346e7480 SH |
858 | #endif |
859 | ||
8a4da6e3 MR |
860 | static int __init arch_timer_register(void) |
861 | { | |
862 | int err; | |
863 | int ppi; | |
864 | ||
8a4da6e3 MR |
865 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
866 | if (!arch_timer_evt) { | |
867 | err = -ENOMEM; | |
868 | goto out; | |
869 | } | |
870 | ||
f81f03fa MZ |
871 | ppi = arch_timer_ppi[arch_timer_uses_ppi]; |
872 | switch (arch_timer_uses_ppi) { | |
873 | case VIRT_PPI: | |
8a4da6e3 MR |
874 | err = request_percpu_irq(ppi, arch_timer_handler_virt, |
875 | "arch_timer", arch_timer_evt); | |
f81f03fa MZ |
876 | break; |
877 | case PHYS_SECURE_PPI: | |
878 | case PHYS_NONSECURE_PPI: | |
8a4da6e3 MR |
879 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
880 | "arch_timer", arch_timer_evt); | |
881 | if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) { | |
882 | ppi = arch_timer_ppi[PHYS_NONSECURE_PPI]; | |
883 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
884 | "arch_timer", arch_timer_evt); | |
885 | if (err) | |
886 | free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], | |
887 | arch_timer_evt); | |
888 | } | |
f81f03fa MZ |
889 | break; |
890 | case HYP_PPI: | |
891 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
892 | "arch_timer", arch_timer_evt); | |
893 | break; | |
894 | default: | |
895 | BUG(); | |
8a4da6e3 MR |
896 | } |
897 | ||
898 | if (err) { | |
899 | pr_err("arch_timer: can't register interrupt %d (%d)\n", | |
900 | ppi, err); | |
901 | goto out_free; | |
902 | } | |
903 | ||
346e7480 SH |
904 | err = arch_timer_cpu_pm_init(); |
905 | if (err) | |
906 | goto out_unreg_notify; | |
907 | ||
8a4da6e3 | 908 | |
7e86e8bd RC |
909 | /* Register and immediately configure the timer on the boot CPU */ |
910 | err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, | |
73c1b41e | 911 | "clockevents/arm/arch_timer:starting", |
7e86e8bd RC |
912 | arch_timer_starting_cpu, arch_timer_dying_cpu); |
913 | if (err) | |
914 | goto out_unreg_cpupm; | |
8a4da6e3 MR |
915 | return 0; |
916 | ||
7e86e8bd RC |
917 | out_unreg_cpupm: |
918 | arch_timer_cpu_pm_deinit(); | |
919 | ||
346e7480 | 920 | out_unreg_notify: |
f81f03fa MZ |
921 | free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt); |
922 | if (arch_timer_has_nonsecure_ppi()) | |
923 | free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], | |
8a4da6e3 | 924 | arch_timer_evt); |
8a4da6e3 MR |
925 | |
926 | out_free: | |
927 | free_percpu(arch_timer_evt); | |
928 | out: | |
929 | return err; | |
930 | } | |
931 | ||
22006994 SB |
932 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
933 | { | |
934 | int ret; | |
935 | irq_handler_t func; | |
936 | struct arch_timer *t; | |
937 | ||
938 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
939 | if (!t) | |
940 | return -ENOMEM; | |
941 | ||
942 | t->base = base; | |
943 | t->evt.irq = irq; | |
944 | __arch_timer_setup(ARCH_MEM_TIMER, &t->evt); | |
945 | ||
946 | if (arch_timer_mem_use_virtual) | |
947 | func = arch_timer_handler_virt_mem; | |
948 | else | |
949 | func = arch_timer_handler_phys_mem; | |
950 | ||
951 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
952 | if (ret) { | |
953 | pr_err("arch_timer: Failed to request mem timer irq\n"); | |
954 | kfree(t); | |
955 | } | |
956 | ||
957 | return ret; | |
958 | } | |
959 | ||
960 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
961 | { .compatible = "arm,armv7-timer", }, | |
962 | { .compatible = "arm,armv8-timer", }, | |
963 | {}, | |
964 | }; | |
965 | ||
966 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
967 | { .compatible = "arm,armv7-timer-mem", }, | |
968 | {}, | |
969 | }; | |
970 | ||
c387f07e | 971 | static bool __init |
566e6dfa | 972 | arch_timer_needs_probing(int type, const struct of_device_id *matches) |
c387f07e SH |
973 | { |
974 | struct device_node *dn; | |
566e6dfa | 975 | bool needs_probing = false; |
c387f07e SH |
976 | |
977 | dn = of_find_matching_node(NULL, matches); | |
59aa896d | 978 | if (dn && of_device_is_available(dn) && !(arch_timers_present & type)) |
566e6dfa | 979 | needs_probing = true; |
c387f07e SH |
980 | of_node_put(dn); |
981 | ||
566e6dfa | 982 | return needs_probing; |
c387f07e SH |
983 | } |
984 | ||
3c0731db | 985 | static int __init arch_timer_common_init(void) |
22006994 SB |
986 | { |
987 | unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER; | |
988 | ||
989 | /* Wait until both nodes are probed if we have two timers */ | |
990 | if ((arch_timers_present & mask) != mask) { | |
566e6dfa | 991 | if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match)) |
3c0731db | 992 | return 0; |
566e6dfa | 993 | if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match)) |
3c0731db | 994 | return 0; |
22006994 SB |
995 | } |
996 | ||
997 | arch_timer_banner(arch_timers_present); | |
998 | arch_counter_register(arch_timers_present); | |
3c0731db | 999 | return arch_timer_arch_init(); |
22006994 SB |
1000 | } |
1001 | ||
3c0731db | 1002 | static int __init arch_timer_init(void) |
8a4da6e3 | 1003 | { |
3c0731db | 1004 | int ret; |
8a4da6e3 | 1005 | /* |
8266891e MZ |
1006 | * If HYP mode is available, we know that the physical timer |
1007 | * has been configured to be accessible from PL1. Use it, so | |
1008 | * that a guest can use the virtual timer instead. | |
1009 | * | |
8a4da6e3 MR |
1010 | * If no interrupt provided for virtual timer, we'll have to |
1011 | * stick to the physical timer. It'd better be accessible... | |
f81f03fa MZ |
1012 | * |
1013 | * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE | |
1014 | * accesses to CNTP_*_EL1 registers are silently redirected to | |
1015 | * their CNTHP_*_EL2 counterparts, and use a different PPI | |
1016 | * number. | |
8a4da6e3 | 1017 | */ |
8266891e | 1018 | if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { |
f81f03fa MZ |
1019 | bool has_ppi; |
1020 | ||
1021 | if (is_kernel_in_hyp_mode()) { | |
1022 | arch_timer_uses_ppi = HYP_PPI; | |
1023 | has_ppi = !!arch_timer_ppi[HYP_PPI]; | |
1024 | } else { | |
1025 | arch_timer_uses_ppi = PHYS_SECURE_PPI; | |
1026 | has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] || | |
1027 | !!arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
1028 | } | |
8a4da6e3 | 1029 | |
f81f03fa | 1030 | if (!has_ppi) { |
8a4da6e3 | 1031 | pr_warn("arch_timer: No interrupt available, giving up\n"); |
3c0731db | 1032 | return -EINVAL; |
8a4da6e3 MR |
1033 | } |
1034 | } | |
1035 | ||
3c0731db DL |
1036 | ret = arch_timer_register(); |
1037 | if (ret) | |
1038 | return ret; | |
1039 | ||
1040 | ret = arch_timer_common_init(); | |
1041 | if (ret) | |
1042 | return ret; | |
d9b5e415 JG |
1043 | |
1044 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI]; | |
3c0731db DL |
1045 | |
1046 | return 0; | |
8a4da6e3 | 1047 | } |
b09ca1ec | 1048 | |
3c0731db | 1049 | static int __init arch_timer_of_init(struct device_node *np) |
b09ca1ec HG |
1050 | { |
1051 | int i; | |
1052 | ||
1053 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
1054 | pr_warn("arch_timer: multiple nodes in dt, skipping\n"); | |
3c0731db | 1055 | return 0; |
b09ca1ec HG |
1056 | } |
1057 | ||
1058 | arch_timers_present |= ARCH_CP15_TIMER; | |
1059 | for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) | |
1060 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); | |
1061 | ||
1062 | arch_timer_detect_rate(NULL, np); | |
1063 | ||
1064 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); | |
1065 | ||
651bb2e9 MZ |
1066 | /* Check for globally applicable workarounds */ |
1067 | arch_timer_check_ool_workaround(ate_match_dt, np); | |
f6dc1576 | 1068 | |
b09ca1ec HG |
1069 | /* |
1070 | * If we cannot rely on firmware initializing the timer registers then | |
1071 | * we should use the physical timers instead. | |
1072 | */ | |
1073 | if (IS_ENABLED(CONFIG_ARM) && | |
1074 | of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) | |
f81f03fa | 1075 | arch_timer_uses_ppi = PHYS_SECURE_PPI; |
b09ca1ec | 1076 | |
d8ec7595 BN |
1077 | /* On some systems, the counter stops ticking when in suspend. */ |
1078 | arch_counter_suspend_stop = of_property_read_bool(np, | |
1079 | "arm,no-tick-in-suspend"); | |
1080 | ||
3c0731db | 1081 | return arch_timer_init(); |
b09ca1ec | 1082 | } |
177cf6e5 DL |
1083 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); |
1084 | CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); | |
22006994 | 1085 | |
3c0731db | 1086 | static int __init arch_timer_mem_init(struct device_node *np) |
22006994 SB |
1087 | { |
1088 | struct device_node *frame, *best_frame = NULL; | |
1089 | void __iomem *cntctlbase, *base; | |
3c0731db | 1090 | unsigned int irq, ret = -EINVAL; |
22006994 SB |
1091 | u32 cnttidr; |
1092 | ||
1093 | arch_timers_present |= ARCH_MEM_TIMER; | |
1094 | cntctlbase = of_iomap(np, 0); | |
1095 | if (!cntctlbase) { | |
1096 | pr_err("arch_timer: Can't find CNTCTLBase\n"); | |
3c0731db | 1097 | return -ENXIO; |
22006994 SB |
1098 | } |
1099 | ||
1100 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
22006994 SB |
1101 | |
1102 | /* | |
1103 | * Try to find a virtual capable frame. Otherwise fall back to a | |
1104 | * physical capable frame. | |
1105 | */ | |
1106 | for_each_available_child_of_node(np, frame) { | |
1107 | int n; | |
e392d603 | 1108 | u32 cntacr; |
22006994 SB |
1109 | |
1110 | if (of_property_read_u32(frame, "frame-number", &n)) { | |
1111 | pr_err("arch_timer: Missing frame-number\n"); | |
22006994 | 1112 | of_node_put(frame); |
e392d603 | 1113 | goto out; |
22006994 SB |
1114 | } |
1115 | ||
e392d603 RM |
1116 | /* Try enabling everything, and see what sticks */ |
1117 | cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | | |
1118 | CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; | |
1119 | writel_relaxed(cntacr, cntctlbase + CNTACR(n)); | |
1120 | cntacr = readl_relaxed(cntctlbase + CNTACR(n)); | |
1121 | ||
1122 | if ((cnttidr & CNTTIDR_VIRT(n)) && | |
1123 | !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { | |
22006994 SB |
1124 | of_node_put(best_frame); |
1125 | best_frame = frame; | |
1126 | arch_timer_mem_use_virtual = true; | |
1127 | break; | |
1128 | } | |
e392d603 RM |
1129 | |
1130 | if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) | |
1131 | continue; | |
1132 | ||
22006994 SB |
1133 | of_node_put(best_frame); |
1134 | best_frame = of_node_get(frame); | |
1135 | } | |
1136 | ||
3c0731db | 1137 | ret= -ENXIO; |
f947ee14 SB |
1138 | base = arch_counter_base = of_io_request_and_map(best_frame, 0, |
1139 | "arch_mem_timer"); | |
1140 | if (IS_ERR(base)) { | |
22006994 | 1141 | pr_err("arch_timer: Can't map frame's registers\n"); |
e392d603 | 1142 | goto out; |
22006994 SB |
1143 | } |
1144 | ||
1145 | if (arch_timer_mem_use_virtual) | |
1146 | irq = irq_of_parse_and_map(best_frame, 1); | |
1147 | else | |
1148 | irq = irq_of_parse_and_map(best_frame, 0); | |
e392d603 | 1149 | |
3c0731db | 1150 | ret = -EINVAL; |
22006994 SB |
1151 | if (!irq) { |
1152 | pr_err("arch_timer: Frame missing %s irq", | |
cfb6d656 | 1153 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
e392d603 | 1154 | goto out; |
22006994 SB |
1155 | } |
1156 | ||
1157 | arch_timer_detect_rate(base, np); | |
3c0731db DL |
1158 | ret = arch_timer_mem_register(base, irq); |
1159 | if (ret) | |
1160 | goto out; | |
1161 | ||
1162 | return arch_timer_common_init(); | |
e392d603 RM |
1163 | out: |
1164 | iounmap(cntctlbase); | |
1165 | of_node_put(best_frame); | |
3c0731db | 1166 | return ret; |
22006994 | 1167 | } |
177cf6e5 | 1168 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", |
22006994 | 1169 | arch_timer_mem_init); |
b09ca1ec HG |
1170 | |
1171 | #ifdef CONFIG_ACPI | |
1172 | static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) | |
1173 | { | |
1174 | int trigger, polarity; | |
1175 | ||
1176 | if (!interrupt) | |
1177 | return 0; | |
1178 | ||
1179 | trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE | |
1180 | : ACPI_LEVEL_SENSITIVE; | |
1181 | ||
1182 | polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW | |
1183 | : ACPI_ACTIVE_HIGH; | |
1184 | ||
1185 | return acpi_register_gsi(NULL, interrupt, trigger, polarity); | |
1186 | } | |
1187 | ||
1188 | /* Initialize per-processor generic timer */ | |
1189 | static int __init arch_timer_acpi_init(struct acpi_table_header *table) | |
1190 | { | |
1191 | struct acpi_table_gtdt *gtdt; | |
1192 | ||
1193 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
1194 | pr_warn("arch_timer: already initialized, skipping\n"); | |
1195 | return -EINVAL; | |
1196 | } | |
1197 | ||
1198 | gtdt = container_of(table, struct acpi_table_gtdt, header); | |
1199 | ||
1200 | arch_timers_present |= ARCH_CP15_TIMER; | |
1201 | ||
1202 | arch_timer_ppi[PHYS_SECURE_PPI] = | |
1203 | map_generic_timer_interrupt(gtdt->secure_el1_interrupt, | |
1204 | gtdt->secure_el1_flags); | |
1205 | ||
1206 | arch_timer_ppi[PHYS_NONSECURE_PPI] = | |
1207 | map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt, | |
1208 | gtdt->non_secure_el1_flags); | |
1209 | ||
1210 | arch_timer_ppi[VIRT_PPI] = | |
1211 | map_generic_timer_interrupt(gtdt->virtual_timer_interrupt, | |
1212 | gtdt->virtual_timer_flags); | |
1213 | ||
1214 | arch_timer_ppi[HYP_PPI] = | |
1215 | map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt, | |
1216 | gtdt->non_secure_el2_flags); | |
1217 | ||
1218 | /* Get the frequency from CNTFRQ */ | |
1219 | arch_timer_detect_rate(NULL, NULL); | |
1220 | ||
1221 | /* Always-on capability */ | |
1222 | arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON); | |
1223 | ||
1224 | arch_timer_init(); | |
1225 | return 0; | |
1226 | } | |
ae281cbd | 1227 | CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); |
b09ca1ec | 1228 | #endif |