]>
Commit | Line | Data |
---|---|---|
8a4da6e3 MR |
1 | /* |
2 | * linux/drivers/clocksource/arm_arch_timer.c | |
3 | * | |
4 | * Copyright (C) 2011 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
f005bd7e MZ |
11 | |
12 | #define pr_fmt(fmt) "arm_arch_timer: " fmt | |
13 | ||
8a4da6e3 MR |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/cpu.h> | |
346e7480 | 19 | #include <linux/cpu_pm.h> |
8a4da6e3 | 20 | #include <linux/clockchips.h> |
7c8f1e78 | 21 | #include <linux/clocksource.h> |
8a4da6e3 MR |
22 | #include <linux/interrupt.h> |
23 | #include <linux/of_irq.h> | |
22006994 | 24 | #include <linux/of_address.h> |
8a4da6e3 | 25 | #include <linux/io.h> |
22006994 | 26 | #include <linux/slab.h> |
65cd4f6c | 27 | #include <linux/sched_clock.h> |
b09ca1ec | 28 | #include <linux/acpi.h> |
8a4da6e3 MR |
29 | |
30 | #include <asm/arch_timer.h> | |
8266891e | 31 | #include <asm/virt.h> |
8a4da6e3 MR |
32 | |
33 | #include <clocksource/arm_arch_timer.h> | |
34 | ||
22006994 SB |
35 | #define CNTTIDR 0x08 |
36 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
37 | ||
e392d603 RM |
38 | #define CNTACR(n) (0x40 + ((n) * 4)) |
39 | #define CNTACR_RPCT BIT(0) | |
40 | #define CNTACR_RVCT BIT(1) | |
41 | #define CNTACR_RFRQ BIT(2) | |
42 | #define CNTACR_RVOFF BIT(3) | |
43 | #define CNTACR_RWVT BIT(4) | |
44 | #define CNTACR_RWPT BIT(5) | |
45 | ||
22006994 SB |
46 | #define CNTVCT_LO 0x08 |
47 | #define CNTVCT_HI 0x0c | |
48 | #define CNTFRQ 0x10 | |
49 | #define CNTP_TVAL 0x28 | |
50 | #define CNTP_CTL 0x2c | |
51 | #define CNTV_TVAL 0x38 | |
52 | #define CNTV_CTL 0x3c | |
53 | ||
54 | #define ARCH_CP15_TIMER BIT(0) | |
55 | #define ARCH_MEM_TIMER BIT(1) | |
56 | static unsigned arch_timers_present __initdata; | |
57 | ||
58 | static void __iomem *arch_counter_base; | |
59 | ||
60 | struct arch_timer { | |
61 | void __iomem *base; | |
62 | struct clock_event_device evt; | |
63 | }; | |
64 | ||
65 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
66 | ||
8a4da6e3 MR |
67 | static u32 arch_timer_rate; |
68 | ||
69 | enum ppi_nr { | |
70 | PHYS_SECURE_PPI, | |
71 | PHYS_NONSECURE_PPI, | |
72 | VIRT_PPI, | |
73 | HYP_PPI, | |
74 | MAX_TIMER_PPI | |
75 | }; | |
76 | ||
77 | static int arch_timer_ppi[MAX_TIMER_PPI]; | |
78 | ||
79 | static struct clock_event_device __percpu *arch_timer_evt; | |
80 | ||
f81f03fa | 81 | static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI; |
82a56194 | 82 | static bool arch_timer_c3stop; |
22006994 | 83 | static bool arch_timer_mem_use_virtual; |
d8ec7595 | 84 | static bool arch_counter_suspend_stop; |
8a4da6e3 | 85 | |
46fd5c6b WD |
86 | static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); |
87 | ||
88 | static int __init early_evtstrm_cfg(char *buf) | |
89 | { | |
90 | return strtobool(buf, &evtstrm_enable); | |
91 | } | |
92 | early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); | |
93 | ||
8a4da6e3 MR |
94 | /* |
95 | * Architected system timer support. | |
96 | */ | |
97 | ||
5271a34c MZ |
98 | static __always_inline |
99 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
100 | struct clock_event_device *clk) | |
101 | { | |
102 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
103 | struct arch_timer *timer = to_arch_timer(clk); | |
104 | switch (reg) { | |
105 | case ARCH_TIMER_REG_CTRL: | |
106 | writel_relaxed(val, timer->base + CNTP_CTL); | |
107 | break; | |
108 | case ARCH_TIMER_REG_TVAL: | |
109 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
110 | break; | |
111 | } | |
112 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
113 | struct arch_timer *timer = to_arch_timer(clk); | |
114 | switch (reg) { | |
115 | case ARCH_TIMER_REG_CTRL: | |
116 | writel_relaxed(val, timer->base + CNTV_CTL); | |
117 | break; | |
118 | case ARCH_TIMER_REG_TVAL: | |
119 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
120 | break; | |
121 | } | |
122 | } else { | |
123 | arch_timer_reg_write_cp15(access, reg, val); | |
124 | } | |
125 | } | |
126 | ||
127 | static __always_inline | |
128 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
129 | struct clock_event_device *clk) | |
130 | { | |
131 | u32 val; | |
132 | ||
133 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
134 | struct arch_timer *timer = to_arch_timer(clk); | |
135 | switch (reg) { | |
136 | case ARCH_TIMER_REG_CTRL: | |
137 | val = readl_relaxed(timer->base + CNTP_CTL); | |
138 | break; | |
139 | case ARCH_TIMER_REG_TVAL: | |
140 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
141 | break; | |
142 | } | |
143 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
144 | struct arch_timer *timer = to_arch_timer(clk); | |
145 | switch (reg) { | |
146 | case ARCH_TIMER_REG_CTRL: | |
147 | val = readl_relaxed(timer->base + CNTV_CTL); | |
148 | break; | |
149 | case ARCH_TIMER_REG_TVAL: | |
150 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
151 | break; | |
152 | } | |
153 | } else { | |
154 | val = arch_timer_reg_read_cp15(access, reg); | |
155 | } | |
156 | ||
157 | return val; | |
158 | } | |
159 | ||
f6dc1576 | 160 | #ifdef CONFIG_FSL_ERRATUM_A008585 |
70d016c2 DT |
161 | /* |
162 | * The number of retries is an arbitrary value well beyond the highest number | |
163 | * of iterations the loop has been observed to take. | |
164 | */ | |
165 | #define __fsl_a008585_read_reg(reg) ({ \ | |
166 | u64 _old, _new; \ | |
167 | int _retries = 200; \ | |
168 | \ | |
169 | do { \ | |
170 | _old = read_sysreg(reg); \ | |
171 | _new = read_sysreg(reg); \ | |
172 | _retries--; \ | |
173 | } while (unlikely(_old != _new) && _retries); \ | |
174 | \ | |
175 | WARN_ON_ONCE(!_retries); \ | |
176 | _new; \ | |
177 | }) | |
178 | ||
179 | static u32 notrace fsl_a008585_read_cntp_tval_el0(void) | |
f6dc1576 SW |
180 | { |
181 | return __fsl_a008585_read_reg(cntp_tval_el0); | |
182 | } | |
183 | ||
70d016c2 | 184 | static u32 notrace fsl_a008585_read_cntv_tval_el0(void) |
f6dc1576 SW |
185 | { |
186 | return __fsl_a008585_read_reg(cntv_tval_el0); | |
187 | } | |
188 | ||
70d016c2 | 189 | static u64 notrace fsl_a008585_read_cntvct_el0(void) |
f6dc1576 SW |
190 | { |
191 | return __fsl_a008585_read_reg(cntvct_el0); | |
192 | } | |
70d016c2 DT |
193 | #endif |
194 | ||
cc104462 DT |
195 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
196 | /* | |
197 | * Verify whether the value of the second read is larger than the first by | |
198 | * less than 32 is the only way to confirm the value is correct, so clear the | |
199 | * lower 5 bits to check whether the difference is greater than 32 or not. | |
200 | * Theoretically the erratum should not occur more than twice in succession | |
201 | * when reading the system counter, but it is possible that some interrupts | |
202 | * may lead to more than twice read errors, triggering the warning, so setting | |
203 | * the number of retries far beyond the number of iterations the loop has been | |
204 | * observed to take. | |
205 | */ | |
206 | #define __hisi_161010101_read_reg(reg) ({ \ | |
207 | u64 _old, _new; \ | |
208 | int _retries = 50; \ | |
209 | \ | |
210 | do { \ | |
211 | _old = read_sysreg(reg); \ | |
212 | _new = read_sysreg(reg); \ | |
213 | _retries--; \ | |
214 | } while (unlikely((_new - _old) >> 5) && _retries); \ | |
215 | \ | |
216 | WARN_ON_ONCE(!_retries); \ | |
217 | _new; \ | |
218 | }) | |
219 | ||
220 | static u32 notrace hisi_161010101_read_cntp_tval_el0(void) | |
221 | { | |
222 | return __hisi_161010101_read_reg(cntp_tval_el0); | |
223 | } | |
224 | ||
225 | static u32 notrace hisi_161010101_read_cntv_tval_el0(void) | |
226 | { | |
227 | return __hisi_161010101_read_reg(cntv_tval_el0); | |
228 | } | |
229 | ||
230 | static u64 notrace hisi_161010101_read_cntvct_el0(void) | |
231 | { | |
232 | return __hisi_161010101_read_reg(cntvct_el0); | |
233 | } | |
234 | #endif | |
235 | ||
70d016c2 DT |
236 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
237 | const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL; | |
238 | EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); | |
239 | ||
240 | DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); | |
241 | EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled); | |
242 | ||
4b76f7fb MZ |
243 | static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, |
244 | struct clock_event_device *clk) | |
245 | { | |
246 | unsigned long ctrl; | |
247 | u64 cval = evt + arch_counter_get_cntvct(); | |
248 | ||
249 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
250 | ctrl |= ARCH_TIMER_CTRL_ENABLE; | |
251 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
252 | ||
253 | if (access == ARCH_TIMER_PHYS_ACCESS) | |
254 | write_sysreg(cval, cntp_cval_el0); | |
255 | else | |
256 | write_sysreg(cval, cntv_cval_el0); | |
257 | ||
258 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
259 | } | |
260 | ||
261 | static int erratum_set_next_event_tval_virt(unsigned long evt, | |
262 | struct clock_event_device *clk) | |
263 | { | |
264 | erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk); | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static int erratum_set_next_event_tval_phys(unsigned long evt, | |
269 | struct clock_event_device *clk) | |
270 | { | |
271 | erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk); | |
272 | return 0; | |
273 | } | |
274 | ||
70d016c2 DT |
275 | static const struct arch_timer_erratum_workaround ool_workarounds[] = { |
276 | #ifdef CONFIG_FSL_ERRATUM_A008585 | |
277 | { | |
63d321a7 | 278 | .match_type = ate_match_dt, |
70d016c2 | 279 | .id = "fsl,erratum-a008585", |
63d321a7 | 280 | .desc = "Freescale erratum a005858", |
70d016c2 DT |
281 | .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, |
282 | .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, | |
283 | .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, | |
5d9decde MZ |
284 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
285 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
70d016c2 DT |
286 | }, |
287 | #endif | |
cc104462 DT |
288 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
289 | { | |
63d321a7 | 290 | .match_type = ate_match_dt, |
cc104462 | 291 | .id = "hisilicon,erratum-161010101", |
63d321a7 | 292 | .desc = "HiSilicon erratum 161010101", |
cc104462 DT |
293 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, |
294 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
295 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
5d9decde MZ |
296 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
297 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
cc104462 DT |
298 | }, |
299 | #endif | |
70d016c2 | 300 | }; |
63d321a7 MZ |
301 | |
302 | typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, | |
303 | const void *); | |
304 | ||
305 | static | |
306 | bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa, | |
307 | const void *arg) | |
308 | { | |
309 | const struct device_node *np = arg; | |
310 | ||
311 | return of_property_read_bool(np, wa->id); | |
312 | } | |
313 | ||
6d0a425d MZ |
314 | static |
315 | bool arch_timer_check_global_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
316 | const void *arg) | |
317 | { | |
318 | return cpus_have_cap((uintptr_t)wa->id); | |
319 | } | |
320 | ||
4e7813c2 MZ |
321 | static |
322 | bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
323 | const void *arg) | |
324 | { | |
325 | return this_cpu_has_cap((uintptr_t)wa->id); | |
326 | } | |
327 | ||
63d321a7 MZ |
328 | static const struct arch_timer_erratum_workaround * |
329 | arch_timer_iterate_errata(enum arch_timer_erratum_match_type type, | |
330 | ate_match_fn_t match_fn, | |
331 | void *arg) | |
332 | { | |
333 | int i; | |
334 | ||
335 | for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { | |
336 | if (ool_workarounds[i].match_type != type) | |
337 | continue; | |
338 | ||
339 | if (match_fn(&ool_workarounds[i], arg)) | |
340 | return &ool_workarounds[i]; | |
341 | } | |
342 | ||
343 | return NULL; | |
344 | } | |
345 | ||
346 | static | |
347 | void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa) | |
348 | { | |
349 | timer_unstable_counter_workaround = wa; | |
350 | static_branch_enable(&arch_timer_read_ool_enabled); | |
351 | } | |
352 | ||
353 | static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type, | |
354 | void *arg) | |
355 | { | |
356 | const struct arch_timer_erratum_workaround *wa; | |
357 | ate_match_fn_t match_fn = NULL; | |
4e7813c2 | 358 | bool local = false; |
63d321a7 MZ |
359 | |
360 | switch (type) { | |
361 | case ate_match_dt: | |
362 | match_fn = arch_timer_check_dt_erratum; | |
363 | break; | |
6d0a425d MZ |
364 | case ate_match_global_cap_id: |
365 | match_fn = arch_timer_check_global_cap_erratum; | |
366 | break; | |
4e7813c2 MZ |
367 | case ate_match_local_cap_id: |
368 | match_fn = arch_timer_check_local_cap_erratum; | |
369 | local = true; | |
370 | break; | |
63d321a7 MZ |
371 | } |
372 | ||
373 | wa = arch_timer_iterate_errata(type, match_fn, arg); | |
374 | if (!wa) | |
375 | return; | |
376 | ||
4e7813c2 MZ |
377 | if (static_branch_unlikely(&arch_timer_read_ool_enabled)) { |
378 | if (wa != timer_unstable_counter_workaround) | |
379 | pr_warn("Can't enable workaround for %s (clashes with %s\n)", | |
380 | wa->desc, | |
381 | timer_unstable_counter_workaround->desc); | |
382 | return; | |
383 | } | |
384 | ||
63d321a7 | 385 | arch_timer_enable_workaround(wa); |
4e7813c2 MZ |
386 | pr_info("Enabling %s workaround for %s\n", |
387 | local ? "local" : "global", wa->desc); | |
63d321a7 MZ |
388 | } |
389 | ||
5d9decde MZ |
390 | #define erratum_handler(fn, r, ...) \ |
391 | ({ \ | |
392 | bool __val; \ | |
393 | if (needs_unstable_timer_counter_workaround() && \ | |
394 | timer_unstable_counter_workaround->fn) { \ | |
395 | r = timer_unstable_counter_workaround->fn(__VA_ARGS__); \ | |
396 | __val = true; \ | |
397 | } else { \ | |
398 | __val = false; \ | |
399 | } \ | |
400 | __val; \ | |
401 | }) | |
402 | ||
63d321a7 MZ |
403 | #else |
404 | #define arch_timer_check_ool_workaround(t,a) do { } while(0) | |
4b76f7fb MZ |
405 | #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;}) |
406 | #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;}) | |
5d9decde | 407 | #define erratum_handler(fn, r, ...) ({false;}) |
70d016c2 | 408 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ |
f6dc1576 | 409 | |
e09f3cc0 | 410 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
411 | struct clock_event_device *evt) |
412 | { | |
413 | unsigned long ctrl; | |
cfb6d656 | 414 | |
60faddf6 | 415 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
416 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
417 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 418 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
419 | evt->event_handler(evt); |
420 | return IRQ_HANDLED; | |
421 | } | |
422 | ||
423 | return IRQ_NONE; | |
424 | } | |
425 | ||
426 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
427 | { | |
428 | struct clock_event_device *evt = dev_id; | |
429 | ||
430 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
431 | } | |
432 | ||
433 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
434 | { | |
435 | struct clock_event_device *evt = dev_id; | |
436 | ||
437 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
438 | } | |
439 | ||
22006994 SB |
440 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
441 | { | |
442 | struct clock_event_device *evt = dev_id; | |
443 | ||
444 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
445 | } | |
446 | ||
447 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
448 | { | |
449 | struct clock_event_device *evt = dev_id; | |
450 | ||
451 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
452 | } | |
453 | ||
46c5bfdd VK |
454 | static __always_inline int timer_shutdown(const int access, |
455 | struct clock_event_device *clk) | |
8a4da6e3 MR |
456 | { |
457 | unsigned long ctrl; | |
46c5bfdd VK |
458 | |
459 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
460 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; | |
461 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
462 | ||
463 | return 0; | |
8a4da6e3 MR |
464 | } |
465 | ||
46c5bfdd | 466 | static int arch_timer_shutdown_virt(struct clock_event_device *clk) |
8a4da6e3 | 467 | { |
46c5bfdd | 468 | return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk); |
8a4da6e3 MR |
469 | } |
470 | ||
46c5bfdd | 471 | static int arch_timer_shutdown_phys(struct clock_event_device *clk) |
8a4da6e3 | 472 | { |
46c5bfdd | 473 | return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); |
8a4da6e3 MR |
474 | } |
475 | ||
46c5bfdd | 476 | static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) |
22006994 | 477 | { |
46c5bfdd | 478 | return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); |
8a4da6e3 MR |
479 | } |
480 | ||
46c5bfdd | 481 | static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) |
22006994 | 482 | { |
46c5bfdd | 483 | return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); |
22006994 SB |
484 | } |
485 | ||
60faddf6 | 486 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 487 | struct clock_event_device *clk) |
8a4da6e3 MR |
488 | { |
489 | unsigned long ctrl; | |
60faddf6 | 490 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
491 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
492 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
493 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
494 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
495 | } |
496 | ||
497 | static int arch_timer_set_next_event_virt(unsigned long evt, | |
60faddf6 | 498 | struct clock_event_device *clk) |
8a4da6e3 | 499 | { |
5d9decde MZ |
500 | int ret; |
501 | ||
502 | if (erratum_handler(set_next_event_virt, ret, evt, clk)) | |
503 | return ret; | |
4b76f7fb | 504 | |
60faddf6 | 505 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
506 | return 0; |
507 | } | |
508 | ||
509 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 510 | struct clock_event_device *clk) |
8a4da6e3 | 511 | { |
5d9decde MZ |
512 | int ret; |
513 | ||
514 | if (erratum_handler(set_next_event_phys, ret, evt, clk)) | |
515 | return ret; | |
4b76f7fb | 516 | |
60faddf6 | 517 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
518 | return 0; |
519 | } | |
520 | ||
22006994 SB |
521 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
522 | struct clock_event_device *clk) | |
8a4da6e3 | 523 | { |
22006994 SB |
524 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
525 | return 0; | |
526 | } | |
527 | ||
528 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
529 | struct clock_event_device *clk) | |
530 | { | |
531 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
532 | return 0; | |
533 | } | |
534 | ||
cfb6d656 TG |
535 | static void __arch_timer_setup(unsigned type, |
536 | struct clock_event_device *clk) | |
22006994 SB |
537 | { |
538 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
539 | ||
540 | if (type == ARCH_CP15_TIMER) { | |
82a56194 LP |
541 | if (arch_timer_c3stop) |
542 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
543 | clk->name = "arch_sys_timer"; |
544 | clk->rating = 450; | |
545 | clk->cpumask = cpumask_of(smp_processor_id()); | |
f81f03fa MZ |
546 | clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; |
547 | switch (arch_timer_uses_ppi) { | |
548 | case VIRT_PPI: | |
46c5bfdd | 549 | clk->set_state_shutdown = arch_timer_shutdown_virt; |
cf8c5009 | 550 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; |
22006994 | 551 | clk->set_next_event = arch_timer_set_next_event_virt; |
f81f03fa MZ |
552 | break; |
553 | case PHYS_SECURE_PPI: | |
554 | case PHYS_NONSECURE_PPI: | |
555 | case HYP_PPI: | |
46c5bfdd | 556 | clk->set_state_shutdown = arch_timer_shutdown_phys; |
cf8c5009 | 557 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; |
22006994 | 558 | clk->set_next_event = arch_timer_set_next_event_phys; |
f81f03fa MZ |
559 | break; |
560 | default: | |
561 | BUG(); | |
22006994 | 562 | } |
f6dc1576 | 563 | |
4e7813c2 | 564 | arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); |
8a4da6e3 | 565 | } else { |
7b52ad2e | 566 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
567 | clk->name = "arch_mem_timer"; |
568 | clk->rating = 400; | |
569 | clk->cpumask = cpu_all_mask; | |
570 | if (arch_timer_mem_use_virtual) { | |
46c5bfdd | 571 | clk->set_state_shutdown = arch_timer_shutdown_virt_mem; |
cf8c5009 | 572 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; |
22006994 SB |
573 | clk->set_next_event = |
574 | arch_timer_set_next_event_virt_mem; | |
575 | } else { | |
46c5bfdd | 576 | clk->set_state_shutdown = arch_timer_shutdown_phys_mem; |
cf8c5009 | 577 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; |
22006994 SB |
578 | clk->set_next_event = |
579 | arch_timer_set_next_event_phys_mem; | |
580 | } | |
8a4da6e3 MR |
581 | } |
582 | ||
46c5bfdd | 583 | clk->set_state_shutdown(clk); |
8a4da6e3 | 584 | |
22006994 SB |
585 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
586 | } | |
8a4da6e3 | 587 | |
e1ce5c7a NL |
588 | static void arch_timer_evtstrm_enable(int divider) |
589 | { | |
590 | u32 cntkctl = arch_timer_get_cntkctl(); | |
591 | ||
592 | cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; | |
593 | /* Set the divider and enable virtual event stream */ | |
594 | cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | |
595 | | ARCH_TIMER_VIRT_EVT_EN; | |
596 | arch_timer_set_cntkctl(cntkctl); | |
597 | elf_hwcap |= HWCAP_EVTSTRM; | |
598 | #ifdef CONFIG_COMPAT | |
599 | compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; | |
600 | #endif | |
601 | } | |
602 | ||
037f6377 WD |
603 | static void arch_timer_configure_evtstream(void) |
604 | { | |
605 | int evt_stream_div, pos; | |
606 | ||
607 | /* Find the closest power of two to the divisor */ | |
608 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
609 | pos = fls(evt_stream_div); | |
610 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
611 | pos--; | |
612 | /* enable event stream */ | |
613 | arch_timer_evtstrm_enable(min(pos, 15)); | |
614 | } | |
615 | ||
8b8dde00 NL |
616 | static void arch_counter_set_user_access(void) |
617 | { | |
618 | u32 cntkctl = arch_timer_get_cntkctl(); | |
619 | ||
620 | /* Disable user access to the timers and the physical counter */ | |
621 | /* Also disable virtual event stream */ | |
622 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
623 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
624 | | ARCH_TIMER_VIRT_EVT_EN | |
625 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
626 | ||
627 | /* Enable user access to the virtual counter */ | |
628 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
629 | ||
630 | arch_timer_set_cntkctl(cntkctl); | |
631 | } | |
632 | ||
f81f03fa MZ |
633 | static bool arch_timer_has_nonsecure_ppi(void) |
634 | { | |
635 | return (arch_timer_uses_ppi == PHYS_SECURE_PPI && | |
636 | arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
637 | } | |
638 | ||
f005bd7e MZ |
639 | static u32 check_ppi_trigger(int irq) |
640 | { | |
641 | u32 flags = irq_get_trigger_type(irq); | |
642 | ||
643 | if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { | |
644 | pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); | |
645 | pr_warn("WARNING: Please fix your firmware\n"); | |
646 | flags = IRQF_TRIGGER_LOW; | |
647 | } | |
648 | ||
649 | return flags; | |
650 | } | |
651 | ||
7e86e8bd | 652 | static int arch_timer_starting_cpu(unsigned int cpu) |
22006994 | 653 | { |
7e86e8bd | 654 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
f005bd7e | 655 | u32 flags; |
7e86e8bd | 656 | |
22006994 | 657 | __arch_timer_setup(ARCH_CP15_TIMER, clk); |
8a4da6e3 | 658 | |
f005bd7e MZ |
659 | flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); |
660 | enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); | |
f81f03fa | 661 | |
f005bd7e MZ |
662 | if (arch_timer_has_nonsecure_ppi()) { |
663 | flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
664 | enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags); | |
665 | } | |
8a4da6e3 MR |
666 | |
667 | arch_counter_set_user_access(); | |
46fd5c6b | 668 | if (evtstrm_enable) |
037f6377 | 669 | arch_timer_configure_evtstream(); |
8a4da6e3 MR |
670 | |
671 | return 0; | |
672 | } | |
673 | ||
22006994 SB |
674 | static void |
675 | arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) | |
8a4da6e3 | 676 | { |
22006994 SB |
677 | /* Who has more than one independent system counter? */ |
678 | if (arch_timer_rate) | |
679 | return; | |
8a4da6e3 | 680 | |
b09ca1ec HG |
681 | /* |
682 | * Try to determine the frequency from the device tree or CNTFRQ, | |
683 | * if ACPI is enabled, get the frequency from CNTFRQ ONLY. | |
684 | */ | |
685 | if (!acpi_disabled || | |
686 | of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { | |
22006994 SB |
687 | if (cntbase) |
688 | arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); | |
689 | else | |
690 | arch_timer_rate = arch_timer_get_cntfrq(); | |
8a4da6e3 MR |
691 | } |
692 | ||
22006994 SB |
693 | /* Check the timer frequency. */ |
694 | if (arch_timer_rate == 0) | |
695 | pr_warn("Architected timer frequency not available\n"); | |
696 | } | |
697 | ||
698 | static void arch_timer_banner(unsigned type) | |
699 | { | |
700 | pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", | |
701 | type & ARCH_CP15_TIMER ? "cp15" : "", | |
702 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "", | |
703 | type & ARCH_MEM_TIMER ? "mmio" : "", | |
8a4da6e3 MR |
704 | (unsigned long)arch_timer_rate / 1000000, |
705 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
22006994 | 706 | type & ARCH_CP15_TIMER ? |
f81f03fa | 707 | (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" : |
22006994 SB |
708 | "", |
709 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "", | |
710 | type & ARCH_MEM_TIMER ? | |
711 | arch_timer_mem_use_virtual ? "virt" : "phys" : | |
712 | ""); | |
8a4da6e3 MR |
713 | } |
714 | ||
715 | u32 arch_timer_get_rate(void) | |
716 | { | |
717 | return arch_timer_rate; | |
718 | } | |
719 | ||
22006994 | 720 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 721 | { |
22006994 SB |
722 | u32 vct_lo, vct_hi, tmp_hi; |
723 | ||
724 | do { | |
725 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
726 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
727 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
728 | } while (vct_hi != tmp_hi); | |
729 | ||
730 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
731 | } |
732 | ||
22006994 SB |
733 | /* |
734 | * Default to cp15 based access because arm64 uses this function for | |
735 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
736 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
737 | * if we don't have the cp15 accessors we won't have a problem. | |
738 | */ | |
739 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
740 | ||
a5a1d1c2 | 741 | static u64 arch_counter_read(struct clocksource *cs) |
8a4da6e3 | 742 | { |
22006994 | 743 | return arch_timer_read_counter(); |
8a4da6e3 MR |
744 | } |
745 | ||
a5a1d1c2 | 746 | static u64 arch_counter_read_cc(const struct cyclecounter *cc) |
8a4da6e3 | 747 | { |
22006994 | 748 | return arch_timer_read_counter(); |
8a4da6e3 MR |
749 | } |
750 | ||
751 | static struct clocksource clocksource_counter = { | |
752 | .name = "arch_sys_counter", | |
753 | .rating = 400, | |
754 | .read = arch_counter_read, | |
755 | .mask = CLOCKSOURCE_MASK(56), | |
d8ec7595 | 756 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8a4da6e3 MR |
757 | }; |
758 | ||
759 | static struct cyclecounter cyclecounter = { | |
760 | .read = arch_counter_read_cc, | |
761 | .mask = CLOCKSOURCE_MASK(56), | |
762 | }; | |
763 | ||
b4d6ce97 JG |
764 | static struct arch_timer_kvm_info arch_timer_kvm_info; |
765 | ||
766 | struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) | |
767 | { | |
768 | return &arch_timer_kvm_info; | |
769 | } | |
8a4da6e3 | 770 | |
22006994 SB |
771 | static void __init arch_counter_register(unsigned type) |
772 | { | |
773 | u64 start_count; | |
774 | ||
775 | /* Register the CP15 based counter if we have one */ | |
423bd69e | 776 | if (type & ARCH_CP15_TIMER) { |
f81f03fa | 777 | if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI) |
0b46b8a7 SR |
778 | arch_timer_read_counter = arch_counter_get_cntvct; |
779 | else | |
780 | arch_timer_read_counter = arch_counter_get_cntpct; | |
f6dc1576 | 781 | |
1d8f51d4 SW |
782 | clocksource_counter.archdata.vdso_direct = true; |
783 | ||
70d016c2 | 784 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
f6dc1576 SW |
785 | /* |
786 | * Don't use the vdso fastpath if errata require using | |
787 | * the out-of-line counter accessor. | |
788 | */ | |
789 | if (static_branch_unlikely(&arch_timer_read_ool_enabled)) | |
1d8f51d4 | 790 | clocksource_counter.archdata.vdso_direct = false; |
f6dc1576 | 791 | #endif |
423bd69e | 792 | } else { |
22006994 | 793 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
423bd69e NL |
794 | } |
795 | ||
d8ec7595 BN |
796 | if (!arch_counter_suspend_stop) |
797 | clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
22006994 SB |
798 | start_count = arch_timer_read_counter(); |
799 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
800 | cyclecounter.mult = clocksource_counter.mult; | |
801 | cyclecounter.shift = clocksource_counter.shift; | |
b4d6ce97 JG |
802 | timecounter_init(&arch_timer_kvm_info.timecounter, |
803 | &cyclecounter, start_count); | |
4a7d3e8a TR |
804 | |
805 | /* 56 bits minimum, so we assume worst case rollover */ | |
806 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
807 | } |
808 | ||
8c37bb3a | 809 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 MR |
810 | { |
811 | pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", | |
812 | clk->irq, smp_processor_id()); | |
813 | ||
f81f03fa MZ |
814 | disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]); |
815 | if (arch_timer_has_nonsecure_ppi()) | |
816 | disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
8a4da6e3 | 817 | |
46c5bfdd | 818 | clk->set_state_shutdown(clk); |
8a4da6e3 MR |
819 | } |
820 | ||
7e86e8bd | 821 | static int arch_timer_dying_cpu(unsigned int cpu) |
8a4da6e3 | 822 | { |
7e86e8bd | 823 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
8a4da6e3 | 824 | |
7e86e8bd RC |
825 | arch_timer_stop(clk); |
826 | return 0; | |
8a4da6e3 MR |
827 | } |
828 | ||
346e7480 SH |
829 | #ifdef CONFIG_CPU_PM |
830 | static unsigned int saved_cntkctl; | |
831 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, | |
832 | unsigned long action, void *hcpu) | |
833 | { | |
834 | if (action == CPU_PM_ENTER) | |
835 | saved_cntkctl = arch_timer_get_cntkctl(); | |
836 | else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) | |
837 | arch_timer_set_cntkctl(saved_cntkctl); | |
838 | return NOTIFY_OK; | |
839 | } | |
840 | ||
841 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
842 | .notifier_call = arch_timer_cpu_pm_notify, | |
843 | }; | |
844 | ||
845 | static int __init arch_timer_cpu_pm_init(void) | |
846 | { | |
847 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
848 | } | |
7e86e8bd RC |
849 | |
850 | static void __init arch_timer_cpu_pm_deinit(void) | |
851 | { | |
852 | WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier)); | |
853 | } | |
854 | ||
346e7480 SH |
855 | #else |
856 | static int __init arch_timer_cpu_pm_init(void) | |
857 | { | |
858 | return 0; | |
859 | } | |
7e86e8bd RC |
860 | |
861 | static void __init arch_timer_cpu_pm_deinit(void) | |
862 | { | |
863 | } | |
346e7480 SH |
864 | #endif |
865 | ||
8a4da6e3 MR |
866 | static int __init arch_timer_register(void) |
867 | { | |
868 | int err; | |
869 | int ppi; | |
870 | ||
8a4da6e3 MR |
871 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
872 | if (!arch_timer_evt) { | |
873 | err = -ENOMEM; | |
874 | goto out; | |
875 | } | |
876 | ||
f81f03fa MZ |
877 | ppi = arch_timer_ppi[arch_timer_uses_ppi]; |
878 | switch (arch_timer_uses_ppi) { | |
879 | case VIRT_PPI: | |
8a4da6e3 MR |
880 | err = request_percpu_irq(ppi, arch_timer_handler_virt, |
881 | "arch_timer", arch_timer_evt); | |
f81f03fa MZ |
882 | break; |
883 | case PHYS_SECURE_PPI: | |
884 | case PHYS_NONSECURE_PPI: | |
8a4da6e3 MR |
885 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
886 | "arch_timer", arch_timer_evt); | |
887 | if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) { | |
888 | ppi = arch_timer_ppi[PHYS_NONSECURE_PPI]; | |
889 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
890 | "arch_timer", arch_timer_evt); | |
891 | if (err) | |
892 | free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], | |
893 | arch_timer_evt); | |
894 | } | |
f81f03fa MZ |
895 | break; |
896 | case HYP_PPI: | |
897 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
898 | "arch_timer", arch_timer_evt); | |
899 | break; | |
900 | default: | |
901 | BUG(); | |
8a4da6e3 MR |
902 | } |
903 | ||
904 | if (err) { | |
905 | pr_err("arch_timer: can't register interrupt %d (%d)\n", | |
906 | ppi, err); | |
907 | goto out_free; | |
908 | } | |
909 | ||
346e7480 SH |
910 | err = arch_timer_cpu_pm_init(); |
911 | if (err) | |
912 | goto out_unreg_notify; | |
913 | ||
8a4da6e3 | 914 | |
7e86e8bd RC |
915 | /* Register and immediately configure the timer on the boot CPU */ |
916 | err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, | |
73c1b41e | 917 | "clockevents/arm/arch_timer:starting", |
7e86e8bd RC |
918 | arch_timer_starting_cpu, arch_timer_dying_cpu); |
919 | if (err) | |
920 | goto out_unreg_cpupm; | |
8a4da6e3 MR |
921 | return 0; |
922 | ||
7e86e8bd RC |
923 | out_unreg_cpupm: |
924 | arch_timer_cpu_pm_deinit(); | |
925 | ||
346e7480 | 926 | out_unreg_notify: |
f81f03fa MZ |
927 | free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt); |
928 | if (arch_timer_has_nonsecure_ppi()) | |
929 | free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], | |
8a4da6e3 | 930 | arch_timer_evt); |
8a4da6e3 MR |
931 | |
932 | out_free: | |
933 | free_percpu(arch_timer_evt); | |
934 | out: | |
935 | return err; | |
936 | } | |
937 | ||
22006994 SB |
938 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
939 | { | |
940 | int ret; | |
941 | irq_handler_t func; | |
942 | struct arch_timer *t; | |
943 | ||
944 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
945 | if (!t) | |
946 | return -ENOMEM; | |
947 | ||
948 | t->base = base; | |
949 | t->evt.irq = irq; | |
950 | __arch_timer_setup(ARCH_MEM_TIMER, &t->evt); | |
951 | ||
952 | if (arch_timer_mem_use_virtual) | |
953 | func = arch_timer_handler_virt_mem; | |
954 | else | |
955 | func = arch_timer_handler_phys_mem; | |
956 | ||
957 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
958 | if (ret) { | |
959 | pr_err("arch_timer: Failed to request mem timer irq\n"); | |
960 | kfree(t); | |
961 | } | |
962 | ||
963 | return ret; | |
964 | } | |
965 | ||
966 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
967 | { .compatible = "arm,armv7-timer", }, | |
968 | { .compatible = "arm,armv8-timer", }, | |
969 | {}, | |
970 | }; | |
971 | ||
972 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
973 | { .compatible = "arm,armv7-timer-mem", }, | |
974 | {}, | |
975 | }; | |
976 | ||
c387f07e | 977 | static bool __init |
566e6dfa | 978 | arch_timer_needs_probing(int type, const struct of_device_id *matches) |
c387f07e SH |
979 | { |
980 | struct device_node *dn; | |
566e6dfa | 981 | bool needs_probing = false; |
c387f07e SH |
982 | |
983 | dn = of_find_matching_node(NULL, matches); | |
59aa896d | 984 | if (dn && of_device_is_available(dn) && !(arch_timers_present & type)) |
566e6dfa | 985 | needs_probing = true; |
c387f07e SH |
986 | of_node_put(dn); |
987 | ||
566e6dfa | 988 | return needs_probing; |
c387f07e SH |
989 | } |
990 | ||
3c0731db | 991 | static int __init arch_timer_common_init(void) |
22006994 SB |
992 | { |
993 | unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER; | |
994 | ||
995 | /* Wait until both nodes are probed if we have two timers */ | |
996 | if ((arch_timers_present & mask) != mask) { | |
566e6dfa | 997 | if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match)) |
3c0731db | 998 | return 0; |
566e6dfa | 999 | if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match)) |
3c0731db | 1000 | return 0; |
22006994 SB |
1001 | } |
1002 | ||
1003 | arch_timer_banner(arch_timers_present); | |
1004 | arch_counter_register(arch_timers_present); | |
3c0731db | 1005 | return arch_timer_arch_init(); |
22006994 SB |
1006 | } |
1007 | ||
3c0731db | 1008 | static int __init arch_timer_init(void) |
8a4da6e3 | 1009 | { |
3c0731db | 1010 | int ret; |
8a4da6e3 | 1011 | /* |
8266891e MZ |
1012 | * If HYP mode is available, we know that the physical timer |
1013 | * has been configured to be accessible from PL1. Use it, so | |
1014 | * that a guest can use the virtual timer instead. | |
1015 | * | |
8a4da6e3 MR |
1016 | * If no interrupt provided for virtual timer, we'll have to |
1017 | * stick to the physical timer. It'd better be accessible... | |
f81f03fa MZ |
1018 | * |
1019 | * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE | |
1020 | * accesses to CNTP_*_EL1 registers are silently redirected to | |
1021 | * their CNTHP_*_EL2 counterparts, and use a different PPI | |
1022 | * number. | |
8a4da6e3 | 1023 | */ |
8266891e | 1024 | if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { |
f81f03fa MZ |
1025 | bool has_ppi; |
1026 | ||
1027 | if (is_kernel_in_hyp_mode()) { | |
1028 | arch_timer_uses_ppi = HYP_PPI; | |
1029 | has_ppi = !!arch_timer_ppi[HYP_PPI]; | |
1030 | } else { | |
1031 | arch_timer_uses_ppi = PHYS_SECURE_PPI; | |
1032 | has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] || | |
1033 | !!arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
1034 | } | |
8a4da6e3 | 1035 | |
f81f03fa | 1036 | if (!has_ppi) { |
8a4da6e3 | 1037 | pr_warn("arch_timer: No interrupt available, giving up\n"); |
3c0731db | 1038 | return -EINVAL; |
8a4da6e3 MR |
1039 | } |
1040 | } | |
1041 | ||
3c0731db DL |
1042 | ret = arch_timer_register(); |
1043 | if (ret) | |
1044 | return ret; | |
1045 | ||
1046 | ret = arch_timer_common_init(); | |
1047 | if (ret) | |
1048 | return ret; | |
d9b5e415 JG |
1049 | |
1050 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI]; | |
3c0731db DL |
1051 | |
1052 | return 0; | |
8a4da6e3 | 1053 | } |
b09ca1ec | 1054 | |
3c0731db | 1055 | static int __init arch_timer_of_init(struct device_node *np) |
b09ca1ec HG |
1056 | { |
1057 | int i; | |
1058 | ||
1059 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
1060 | pr_warn("arch_timer: multiple nodes in dt, skipping\n"); | |
3c0731db | 1061 | return 0; |
b09ca1ec HG |
1062 | } |
1063 | ||
1064 | arch_timers_present |= ARCH_CP15_TIMER; | |
1065 | for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) | |
1066 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); | |
1067 | ||
1068 | arch_timer_detect_rate(NULL, np); | |
1069 | ||
1070 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); | |
1071 | ||
63d321a7 MZ |
1072 | /* Check for globally applicable workarounds */ |
1073 | arch_timer_check_ool_workaround(ate_match_dt, np); | |
6d0a425d | 1074 | arch_timer_check_ool_workaround(ate_match_global_cap_id, NULL); |
f6dc1576 | 1075 | |
b09ca1ec HG |
1076 | /* |
1077 | * If we cannot rely on firmware initializing the timer registers then | |
1078 | * we should use the physical timers instead. | |
1079 | */ | |
1080 | if (IS_ENABLED(CONFIG_ARM) && | |
1081 | of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) | |
f81f03fa | 1082 | arch_timer_uses_ppi = PHYS_SECURE_PPI; |
b09ca1ec | 1083 | |
d8ec7595 BN |
1084 | /* On some systems, the counter stops ticking when in suspend. */ |
1085 | arch_counter_suspend_stop = of_property_read_bool(np, | |
1086 | "arm,no-tick-in-suspend"); | |
1087 | ||
3c0731db | 1088 | return arch_timer_init(); |
b09ca1ec | 1089 | } |
177cf6e5 DL |
1090 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); |
1091 | CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); | |
22006994 | 1092 | |
3c0731db | 1093 | static int __init arch_timer_mem_init(struct device_node *np) |
22006994 SB |
1094 | { |
1095 | struct device_node *frame, *best_frame = NULL; | |
1096 | void __iomem *cntctlbase, *base; | |
3c0731db | 1097 | unsigned int irq, ret = -EINVAL; |
22006994 SB |
1098 | u32 cnttidr; |
1099 | ||
1100 | arch_timers_present |= ARCH_MEM_TIMER; | |
1101 | cntctlbase = of_iomap(np, 0); | |
1102 | if (!cntctlbase) { | |
1103 | pr_err("arch_timer: Can't find CNTCTLBase\n"); | |
3c0731db | 1104 | return -ENXIO; |
22006994 SB |
1105 | } |
1106 | ||
1107 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
22006994 SB |
1108 | |
1109 | /* | |
1110 | * Try to find a virtual capable frame. Otherwise fall back to a | |
1111 | * physical capable frame. | |
1112 | */ | |
1113 | for_each_available_child_of_node(np, frame) { | |
1114 | int n; | |
e392d603 | 1115 | u32 cntacr; |
22006994 SB |
1116 | |
1117 | if (of_property_read_u32(frame, "frame-number", &n)) { | |
1118 | pr_err("arch_timer: Missing frame-number\n"); | |
22006994 | 1119 | of_node_put(frame); |
e392d603 | 1120 | goto out; |
22006994 SB |
1121 | } |
1122 | ||
e392d603 RM |
1123 | /* Try enabling everything, and see what sticks */ |
1124 | cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | | |
1125 | CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; | |
1126 | writel_relaxed(cntacr, cntctlbase + CNTACR(n)); | |
1127 | cntacr = readl_relaxed(cntctlbase + CNTACR(n)); | |
1128 | ||
1129 | if ((cnttidr & CNTTIDR_VIRT(n)) && | |
1130 | !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { | |
22006994 SB |
1131 | of_node_put(best_frame); |
1132 | best_frame = frame; | |
1133 | arch_timer_mem_use_virtual = true; | |
1134 | break; | |
1135 | } | |
e392d603 RM |
1136 | |
1137 | if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) | |
1138 | continue; | |
1139 | ||
22006994 SB |
1140 | of_node_put(best_frame); |
1141 | best_frame = of_node_get(frame); | |
1142 | } | |
1143 | ||
3c0731db | 1144 | ret= -ENXIO; |
f947ee14 SB |
1145 | base = arch_counter_base = of_io_request_and_map(best_frame, 0, |
1146 | "arch_mem_timer"); | |
1147 | if (IS_ERR(base)) { | |
22006994 | 1148 | pr_err("arch_timer: Can't map frame's registers\n"); |
e392d603 | 1149 | goto out; |
22006994 SB |
1150 | } |
1151 | ||
1152 | if (arch_timer_mem_use_virtual) | |
1153 | irq = irq_of_parse_and_map(best_frame, 1); | |
1154 | else | |
1155 | irq = irq_of_parse_and_map(best_frame, 0); | |
e392d603 | 1156 | |
3c0731db | 1157 | ret = -EINVAL; |
22006994 SB |
1158 | if (!irq) { |
1159 | pr_err("arch_timer: Frame missing %s irq", | |
cfb6d656 | 1160 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
e392d603 | 1161 | goto out; |
22006994 SB |
1162 | } |
1163 | ||
1164 | arch_timer_detect_rate(base, np); | |
3c0731db DL |
1165 | ret = arch_timer_mem_register(base, irq); |
1166 | if (ret) | |
1167 | goto out; | |
1168 | ||
1169 | return arch_timer_common_init(); | |
e392d603 RM |
1170 | out: |
1171 | iounmap(cntctlbase); | |
1172 | of_node_put(best_frame); | |
3c0731db | 1173 | return ret; |
22006994 | 1174 | } |
177cf6e5 | 1175 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", |
22006994 | 1176 | arch_timer_mem_init); |
b09ca1ec HG |
1177 | |
1178 | #ifdef CONFIG_ACPI | |
1179 | static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) | |
1180 | { | |
1181 | int trigger, polarity; | |
1182 | ||
1183 | if (!interrupt) | |
1184 | return 0; | |
1185 | ||
1186 | trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE | |
1187 | : ACPI_LEVEL_SENSITIVE; | |
1188 | ||
1189 | polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW | |
1190 | : ACPI_ACTIVE_HIGH; | |
1191 | ||
1192 | return acpi_register_gsi(NULL, interrupt, trigger, polarity); | |
1193 | } | |
1194 | ||
1195 | /* Initialize per-processor generic timer */ | |
1196 | static int __init arch_timer_acpi_init(struct acpi_table_header *table) | |
1197 | { | |
1198 | struct acpi_table_gtdt *gtdt; | |
1199 | ||
1200 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
1201 | pr_warn("arch_timer: already initialized, skipping\n"); | |
1202 | return -EINVAL; | |
1203 | } | |
1204 | ||
1205 | gtdt = container_of(table, struct acpi_table_gtdt, header); | |
1206 | ||
1207 | arch_timers_present |= ARCH_CP15_TIMER; | |
1208 | ||
1209 | arch_timer_ppi[PHYS_SECURE_PPI] = | |
1210 | map_generic_timer_interrupt(gtdt->secure_el1_interrupt, | |
1211 | gtdt->secure_el1_flags); | |
1212 | ||
1213 | arch_timer_ppi[PHYS_NONSECURE_PPI] = | |
1214 | map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt, | |
1215 | gtdt->non_secure_el1_flags); | |
1216 | ||
1217 | arch_timer_ppi[VIRT_PPI] = | |
1218 | map_generic_timer_interrupt(gtdt->virtual_timer_interrupt, | |
1219 | gtdt->virtual_timer_flags); | |
1220 | ||
1221 | arch_timer_ppi[HYP_PPI] = | |
1222 | map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt, | |
1223 | gtdt->non_secure_el2_flags); | |
1224 | ||
1225 | /* Get the frequency from CNTFRQ */ | |
1226 | arch_timer_detect_rate(NULL, NULL); | |
1227 | ||
1228 | /* Always-on capability */ | |
1229 | arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON); | |
1230 | ||
6d0a425d MZ |
1231 | /* Check for globally applicable workarounds */ |
1232 | arch_timer_check_ool_workaround(ate_match_global_cap_id, NULL); | |
1233 | ||
b09ca1ec HG |
1234 | arch_timer_init(); |
1235 | return 0; | |
1236 | } | |
ae281cbd | 1237 | CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); |
b09ca1ec | 1238 | #endif |