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Commit | Line | Data |
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8a4da6e3 MR |
1 | /* |
2 | * linux/drivers/clocksource/arm_arch_timer.c | |
3 | * | |
4 | * Copyright (C) 2011 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
f005bd7e MZ |
11 | |
12 | #define pr_fmt(fmt) "arm_arch_timer: " fmt | |
13 | ||
8a4da6e3 MR |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/cpu.h> | |
346e7480 | 19 | #include <linux/cpu_pm.h> |
8a4da6e3 | 20 | #include <linux/clockchips.h> |
7c8f1e78 | 21 | #include <linux/clocksource.h> |
8a4da6e3 MR |
22 | #include <linux/interrupt.h> |
23 | #include <linux/of_irq.h> | |
22006994 | 24 | #include <linux/of_address.h> |
8a4da6e3 | 25 | #include <linux/io.h> |
22006994 | 26 | #include <linux/slab.h> |
e6017571 | 27 | #include <linux/sched/clock.h> |
65cd4f6c | 28 | #include <linux/sched_clock.h> |
b09ca1ec | 29 | #include <linux/acpi.h> |
8a4da6e3 MR |
30 | |
31 | #include <asm/arch_timer.h> | |
8266891e | 32 | #include <asm/virt.h> |
8a4da6e3 MR |
33 | |
34 | #include <clocksource/arm_arch_timer.h> | |
35 | ||
22006994 SB |
36 | #define CNTTIDR 0x08 |
37 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
38 | ||
e392d603 RM |
39 | #define CNTACR(n) (0x40 + ((n) * 4)) |
40 | #define CNTACR_RPCT BIT(0) | |
41 | #define CNTACR_RVCT BIT(1) | |
42 | #define CNTACR_RFRQ BIT(2) | |
43 | #define CNTACR_RVOFF BIT(3) | |
44 | #define CNTACR_RWVT BIT(4) | |
45 | #define CNTACR_RWPT BIT(5) | |
46 | ||
22006994 SB |
47 | #define CNTVCT_LO 0x08 |
48 | #define CNTVCT_HI 0x0c | |
49 | #define CNTFRQ 0x10 | |
50 | #define CNTP_TVAL 0x28 | |
51 | #define CNTP_CTL 0x2c | |
52 | #define CNTV_TVAL 0x38 | |
53 | #define CNTV_CTL 0x3c | |
54 | ||
55 | #define ARCH_CP15_TIMER BIT(0) | |
56 | #define ARCH_MEM_TIMER BIT(1) | |
57 | static unsigned arch_timers_present __initdata; | |
58 | ||
59 | static void __iomem *arch_counter_base; | |
60 | ||
61 | struct arch_timer { | |
62 | void __iomem *base; | |
63 | struct clock_event_device evt; | |
64 | }; | |
65 | ||
66 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
67 | ||
8a4da6e3 MR |
68 | static u32 arch_timer_rate; |
69 | ||
70 | enum ppi_nr { | |
71 | PHYS_SECURE_PPI, | |
72 | PHYS_NONSECURE_PPI, | |
73 | VIRT_PPI, | |
74 | HYP_PPI, | |
75 | MAX_TIMER_PPI | |
76 | }; | |
77 | ||
78 | static int arch_timer_ppi[MAX_TIMER_PPI]; | |
79 | ||
80 | static struct clock_event_device __percpu *arch_timer_evt; | |
81 | ||
f81f03fa | 82 | static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI; |
82a56194 | 83 | static bool arch_timer_c3stop; |
22006994 | 84 | static bool arch_timer_mem_use_virtual; |
d8ec7595 | 85 | static bool arch_counter_suspend_stop; |
8a4da6e3 | 86 | |
46fd5c6b WD |
87 | static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); |
88 | ||
89 | static int __init early_evtstrm_cfg(char *buf) | |
90 | { | |
91 | return strtobool(buf, &evtstrm_enable); | |
92 | } | |
93 | early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); | |
94 | ||
8a4da6e3 MR |
95 | /* |
96 | * Architected system timer support. | |
97 | */ | |
98 | ||
f4e00a1a MZ |
99 | static __always_inline |
100 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
101 | struct clock_event_device *clk) | |
102 | { | |
103 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
104 | struct arch_timer *timer = to_arch_timer(clk); | |
105 | switch (reg) { | |
106 | case ARCH_TIMER_REG_CTRL: | |
107 | writel_relaxed(val, timer->base + CNTP_CTL); | |
108 | break; | |
109 | case ARCH_TIMER_REG_TVAL: | |
110 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
111 | break; | |
112 | } | |
113 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
114 | struct arch_timer *timer = to_arch_timer(clk); | |
115 | switch (reg) { | |
116 | case ARCH_TIMER_REG_CTRL: | |
117 | writel_relaxed(val, timer->base + CNTV_CTL); | |
118 | break; | |
119 | case ARCH_TIMER_REG_TVAL: | |
120 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
121 | break; | |
122 | } | |
123 | } else { | |
124 | arch_timer_reg_write_cp15(access, reg, val); | |
125 | } | |
126 | } | |
127 | ||
128 | static __always_inline | |
129 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
130 | struct clock_event_device *clk) | |
131 | { | |
132 | u32 val; | |
133 | ||
134 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
135 | struct arch_timer *timer = to_arch_timer(clk); | |
136 | switch (reg) { | |
137 | case ARCH_TIMER_REG_CTRL: | |
138 | val = readl_relaxed(timer->base + CNTP_CTL); | |
139 | break; | |
140 | case ARCH_TIMER_REG_TVAL: | |
141 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
142 | break; | |
143 | } | |
144 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
145 | struct arch_timer *timer = to_arch_timer(clk); | |
146 | switch (reg) { | |
147 | case ARCH_TIMER_REG_CTRL: | |
148 | val = readl_relaxed(timer->base + CNTV_CTL); | |
149 | break; | |
150 | case ARCH_TIMER_REG_TVAL: | |
151 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
152 | break; | |
153 | } | |
154 | } else { | |
155 | val = arch_timer_reg_read_cp15(access, reg); | |
156 | } | |
157 | ||
158 | return val; | |
159 | } | |
160 | ||
992dd16f MZ |
161 | /* |
162 | * Default to cp15 based access because arm64 uses this function for | |
163 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
164 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
165 | * if we don't have the cp15 accessors we won't have a problem. | |
166 | */ | |
167 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
168 | ||
169 | static u64 arch_counter_read(struct clocksource *cs) | |
170 | { | |
171 | return arch_timer_read_counter(); | |
172 | } | |
173 | ||
174 | static u64 arch_counter_read_cc(const struct cyclecounter *cc) | |
175 | { | |
176 | return arch_timer_read_counter(); | |
177 | } | |
178 | ||
179 | static struct clocksource clocksource_counter = { | |
180 | .name = "arch_sys_counter", | |
181 | .rating = 400, | |
182 | .read = arch_counter_read, | |
183 | .mask = CLOCKSOURCE_MASK(56), | |
184 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
185 | }; | |
186 | ||
187 | static struct cyclecounter cyclecounter __ro_after_init = { | |
188 | .read = arch_counter_read_cc, | |
189 | .mask = CLOCKSOURCE_MASK(56), | |
190 | }; | |
191 | ||
f6dc1576 | 192 | #ifdef CONFIG_FSL_ERRATUM_A008585 |
16d10ef2 DT |
193 | /* |
194 | * The number of retries is an arbitrary value well beyond the highest number | |
195 | * of iterations the loop has been observed to take. | |
196 | */ | |
197 | #define __fsl_a008585_read_reg(reg) ({ \ | |
198 | u64 _old, _new; \ | |
199 | int _retries = 200; \ | |
200 | \ | |
201 | do { \ | |
202 | _old = read_sysreg(reg); \ | |
203 | _new = read_sysreg(reg); \ | |
204 | _retries--; \ | |
205 | } while (unlikely(_old != _new) && _retries); \ | |
206 | \ | |
207 | WARN_ON_ONCE(!_retries); \ | |
208 | _new; \ | |
209 | }) | |
210 | ||
211 | static u32 notrace fsl_a008585_read_cntp_tval_el0(void) | |
f6dc1576 SW |
212 | { |
213 | return __fsl_a008585_read_reg(cntp_tval_el0); | |
214 | } | |
215 | ||
16d10ef2 | 216 | static u32 notrace fsl_a008585_read_cntv_tval_el0(void) |
f6dc1576 SW |
217 | { |
218 | return __fsl_a008585_read_reg(cntv_tval_el0); | |
219 | } | |
220 | ||
16d10ef2 | 221 | static u64 notrace fsl_a008585_read_cntvct_el0(void) |
f6dc1576 SW |
222 | { |
223 | return __fsl_a008585_read_reg(cntvct_el0); | |
224 | } | |
16d10ef2 DT |
225 | #endif |
226 | ||
bb42ca47 DT |
227 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
228 | /* | |
229 | * Verify whether the value of the second read is larger than the first by | |
230 | * less than 32 is the only way to confirm the value is correct, so clear the | |
231 | * lower 5 bits to check whether the difference is greater than 32 or not. | |
232 | * Theoretically the erratum should not occur more than twice in succession | |
233 | * when reading the system counter, but it is possible that some interrupts | |
234 | * may lead to more than twice read errors, triggering the warning, so setting | |
235 | * the number of retries far beyond the number of iterations the loop has been | |
236 | * observed to take. | |
237 | */ | |
238 | #define __hisi_161010101_read_reg(reg) ({ \ | |
239 | u64 _old, _new; \ | |
240 | int _retries = 50; \ | |
241 | \ | |
242 | do { \ | |
243 | _old = read_sysreg(reg); \ | |
244 | _new = read_sysreg(reg); \ | |
245 | _retries--; \ | |
246 | } while (unlikely((_new - _old) >> 5) && _retries); \ | |
247 | \ | |
248 | WARN_ON_ONCE(!_retries); \ | |
249 | _new; \ | |
250 | }) | |
251 | ||
252 | static u32 notrace hisi_161010101_read_cntp_tval_el0(void) | |
253 | { | |
254 | return __hisi_161010101_read_reg(cntp_tval_el0); | |
255 | } | |
256 | ||
257 | static u32 notrace hisi_161010101_read_cntv_tval_el0(void) | |
258 | { | |
259 | return __hisi_161010101_read_reg(cntv_tval_el0); | |
260 | } | |
261 | ||
262 | static u64 notrace hisi_161010101_read_cntvct_el0(void) | |
263 | { | |
264 | return __hisi_161010101_read_reg(cntvct_el0); | |
265 | } | |
266 | #endif | |
267 | ||
16d10ef2 | 268 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
6acc71cc MZ |
269 | DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, |
270 | timer_unstable_counter_workaround); | |
16d10ef2 DT |
271 | EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); |
272 | ||
273 | DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); | |
274 | EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled); | |
275 | ||
8328089f MZ |
276 | static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, |
277 | struct clock_event_device *clk) | |
278 | { | |
279 | unsigned long ctrl; | |
280 | u64 cval = evt + arch_counter_get_cntvct(); | |
281 | ||
282 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
283 | ctrl |= ARCH_TIMER_CTRL_ENABLE; | |
284 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
285 | ||
286 | if (access == ARCH_TIMER_PHYS_ACCESS) | |
287 | write_sysreg(cval, cntp_cval_el0); | |
288 | else | |
289 | write_sysreg(cval, cntv_cval_el0); | |
290 | ||
291 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
292 | } | |
293 | ||
294 | static int erratum_set_next_event_tval_virt(unsigned long evt, | |
295 | struct clock_event_device *clk) | |
296 | { | |
297 | erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk); | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static int erratum_set_next_event_tval_phys(unsigned long evt, | |
302 | struct clock_event_device *clk) | |
303 | { | |
304 | erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk); | |
305 | return 0; | |
306 | } | |
307 | ||
16d10ef2 DT |
308 | static const struct arch_timer_erratum_workaround ool_workarounds[] = { |
309 | #ifdef CONFIG_FSL_ERRATUM_A008585 | |
310 | { | |
651bb2e9 | 311 | .match_type = ate_match_dt, |
16d10ef2 | 312 | .id = "fsl,erratum-a008585", |
651bb2e9 | 313 | .desc = "Freescale erratum a005858", |
16d10ef2 DT |
314 | .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, |
315 | .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, | |
316 | .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, | |
01d3e3ff MZ |
317 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
318 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
16d10ef2 DT |
319 | }, |
320 | #endif | |
bb42ca47 DT |
321 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
322 | { | |
651bb2e9 | 323 | .match_type = ate_match_dt, |
bb42ca47 | 324 | .id = "hisilicon,erratum-161010101", |
651bb2e9 | 325 | .desc = "HiSilicon erratum 161010101", |
bb42ca47 DT |
326 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, |
327 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
328 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
01d3e3ff MZ |
329 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
330 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
bb42ca47 DT |
331 | }, |
332 | #endif | |
16d10ef2 | 333 | }; |
651bb2e9 MZ |
334 | |
335 | typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, | |
336 | const void *); | |
337 | ||
338 | static | |
339 | bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa, | |
340 | const void *arg) | |
341 | { | |
342 | const struct device_node *np = arg; | |
343 | ||
344 | return of_property_read_bool(np, wa->id); | |
345 | } | |
346 | ||
0064030c MZ |
347 | static |
348 | bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
349 | const void *arg) | |
350 | { | |
351 | return this_cpu_has_cap((uintptr_t)wa->id); | |
352 | } | |
353 | ||
651bb2e9 MZ |
354 | static const struct arch_timer_erratum_workaround * |
355 | arch_timer_iterate_errata(enum arch_timer_erratum_match_type type, | |
356 | ate_match_fn_t match_fn, | |
357 | void *arg) | |
358 | { | |
359 | int i; | |
360 | ||
361 | for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { | |
362 | if (ool_workarounds[i].match_type != type) | |
363 | continue; | |
364 | ||
365 | if (match_fn(&ool_workarounds[i], arg)) | |
366 | return &ool_workarounds[i]; | |
367 | } | |
368 | ||
369 | return NULL; | |
370 | } | |
371 | ||
372 | static | |
6acc71cc MZ |
373 | void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa, |
374 | bool local) | |
651bb2e9 | 375 | { |
6acc71cc MZ |
376 | int i; |
377 | ||
378 | if (local) { | |
379 | __this_cpu_write(timer_unstable_counter_workaround, wa); | |
380 | } else { | |
381 | for_each_possible_cpu(i) | |
382 | per_cpu(timer_unstable_counter_workaround, i) = wa; | |
383 | } | |
384 | ||
651bb2e9 MZ |
385 | static_branch_enable(&arch_timer_read_ool_enabled); |
386 | } | |
387 | ||
388 | static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type, | |
389 | void *arg) | |
390 | { | |
391 | const struct arch_timer_erratum_workaround *wa; | |
392 | ate_match_fn_t match_fn = NULL; | |
0064030c | 393 | bool local = false; |
651bb2e9 MZ |
394 | |
395 | switch (type) { | |
396 | case ate_match_dt: | |
397 | match_fn = arch_timer_check_dt_erratum; | |
398 | break; | |
0064030c MZ |
399 | case ate_match_local_cap_id: |
400 | match_fn = arch_timer_check_local_cap_erratum; | |
401 | local = true; | |
402 | break; | |
651bb2e9 MZ |
403 | default: |
404 | WARN_ON(1); | |
405 | return; | |
406 | } | |
407 | ||
408 | wa = arch_timer_iterate_errata(type, match_fn, arg); | |
409 | if (!wa) | |
410 | return; | |
411 | ||
0064030c | 412 | if (needs_unstable_timer_counter_workaround()) { |
6acc71cc MZ |
413 | const struct arch_timer_erratum_workaround *__wa; |
414 | __wa = __this_cpu_read(timer_unstable_counter_workaround); | |
415 | if (__wa && wa != __wa) | |
0064030c | 416 | pr_warn("Can't enable workaround for %s (clashes with %s\n)", |
6acc71cc MZ |
417 | wa->desc, __wa->desc); |
418 | ||
419 | if (__wa) | |
420 | return; | |
0064030c MZ |
421 | } |
422 | ||
6acc71cc | 423 | arch_timer_enable_workaround(wa, local); |
0064030c MZ |
424 | pr_info("Enabling %s workaround for %s\n", |
425 | local ? "local" : "global", wa->desc); | |
651bb2e9 MZ |
426 | } |
427 | ||
01d3e3ff MZ |
428 | #define erratum_handler(fn, r, ...) \ |
429 | ({ \ | |
430 | bool __val; \ | |
6acc71cc MZ |
431 | if (needs_unstable_timer_counter_workaround()) { \ |
432 | const struct arch_timer_erratum_workaround *__wa; \ | |
433 | __wa = __this_cpu_read(timer_unstable_counter_workaround); \ | |
434 | if (__wa && __wa->fn) { \ | |
435 | r = __wa->fn(__VA_ARGS__); \ | |
436 | __val = true; \ | |
437 | } else { \ | |
438 | __val = false; \ | |
439 | } \ | |
01d3e3ff MZ |
440 | } else { \ |
441 | __val = false; \ | |
442 | } \ | |
443 | __val; \ | |
444 | }) | |
445 | ||
651bb2e9 MZ |
446 | #else |
447 | #define arch_timer_check_ool_workaround(t,a) do { } while(0) | |
8328089f MZ |
448 | #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;}) |
449 | #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;}) | |
01d3e3ff | 450 | #define erratum_handler(fn, r, ...) ({false;}) |
16d10ef2 | 451 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ |
f6dc1576 | 452 | |
e09f3cc0 | 453 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
454 | struct clock_event_device *evt) |
455 | { | |
456 | unsigned long ctrl; | |
cfb6d656 | 457 | |
60faddf6 | 458 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
459 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
460 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 461 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
462 | evt->event_handler(evt); |
463 | return IRQ_HANDLED; | |
464 | } | |
465 | ||
466 | return IRQ_NONE; | |
467 | } | |
468 | ||
469 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
470 | { | |
471 | struct clock_event_device *evt = dev_id; | |
472 | ||
473 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
474 | } | |
475 | ||
476 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
477 | { | |
478 | struct clock_event_device *evt = dev_id; | |
479 | ||
480 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
481 | } | |
482 | ||
22006994 SB |
483 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
484 | { | |
485 | struct clock_event_device *evt = dev_id; | |
486 | ||
487 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
488 | } | |
489 | ||
490 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
491 | { | |
492 | struct clock_event_device *evt = dev_id; | |
493 | ||
494 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
495 | } | |
496 | ||
46c5bfdd VK |
497 | static __always_inline int timer_shutdown(const int access, |
498 | struct clock_event_device *clk) | |
8a4da6e3 MR |
499 | { |
500 | unsigned long ctrl; | |
46c5bfdd VK |
501 | |
502 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
503 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; | |
504 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
505 | ||
506 | return 0; | |
8a4da6e3 MR |
507 | } |
508 | ||
46c5bfdd | 509 | static int arch_timer_shutdown_virt(struct clock_event_device *clk) |
8a4da6e3 | 510 | { |
46c5bfdd | 511 | return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk); |
8a4da6e3 MR |
512 | } |
513 | ||
46c5bfdd | 514 | static int arch_timer_shutdown_phys(struct clock_event_device *clk) |
8a4da6e3 | 515 | { |
46c5bfdd | 516 | return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); |
8a4da6e3 MR |
517 | } |
518 | ||
46c5bfdd | 519 | static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) |
22006994 | 520 | { |
46c5bfdd | 521 | return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); |
8a4da6e3 MR |
522 | } |
523 | ||
46c5bfdd | 524 | static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) |
22006994 | 525 | { |
46c5bfdd | 526 | return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); |
22006994 SB |
527 | } |
528 | ||
60faddf6 | 529 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 530 | struct clock_event_device *clk) |
8a4da6e3 MR |
531 | { |
532 | unsigned long ctrl; | |
60faddf6 | 533 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
534 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
535 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
536 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
537 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
538 | } |
539 | ||
540 | static int arch_timer_set_next_event_virt(unsigned long evt, | |
60faddf6 | 541 | struct clock_event_device *clk) |
8a4da6e3 | 542 | { |
01d3e3ff MZ |
543 | int ret; |
544 | ||
545 | if (erratum_handler(set_next_event_virt, ret, evt, clk)) | |
546 | return ret; | |
8328089f | 547 | |
60faddf6 | 548 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
549 | return 0; |
550 | } | |
551 | ||
552 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 553 | struct clock_event_device *clk) |
8a4da6e3 | 554 | { |
01d3e3ff MZ |
555 | int ret; |
556 | ||
557 | if (erratum_handler(set_next_event_phys, ret, evt, clk)) | |
558 | return ret; | |
8328089f | 559 | |
60faddf6 | 560 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
561 | return 0; |
562 | } | |
563 | ||
22006994 SB |
564 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
565 | struct clock_event_device *clk) | |
8a4da6e3 | 566 | { |
22006994 SB |
567 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
568 | return 0; | |
569 | } | |
570 | ||
571 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
572 | struct clock_event_device *clk) | |
573 | { | |
574 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
575 | return 0; | |
576 | } | |
577 | ||
cfb6d656 TG |
578 | static void __arch_timer_setup(unsigned type, |
579 | struct clock_event_device *clk) | |
22006994 SB |
580 | { |
581 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
582 | ||
583 | if (type == ARCH_CP15_TIMER) { | |
82a56194 LP |
584 | if (arch_timer_c3stop) |
585 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
586 | clk->name = "arch_sys_timer"; |
587 | clk->rating = 450; | |
588 | clk->cpumask = cpumask_of(smp_processor_id()); | |
f81f03fa MZ |
589 | clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; |
590 | switch (arch_timer_uses_ppi) { | |
591 | case VIRT_PPI: | |
46c5bfdd | 592 | clk->set_state_shutdown = arch_timer_shutdown_virt; |
cf8c5009 | 593 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; |
22006994 | 594 | clk->set_next_event = arch_timer_set_next_event_virt; |
f81f03fa MZ |
595 | break; |
596 | case PHYS_SECURE_PPI: | |
597 | case PHYS_NONSECURE_PPI: | |
598 | case HYP_PPI: | |
46c5bfdd | 599 | clk->set_state_shutdown = arch_timer_shutdown_phys; |
cf8c5009 | 600 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; |
22006994 | 601 | clk->set_next_event = arch_timer_set_next_event_phys; |
f81f03fa MZ |
602 | break; |
603 | default: | |
604 | BUG(); | |
22006994 | 605 | } |
f6dc1576 | 606 | |
0064030c | 607 | arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); |
8a4da6e3 | 608 | } else { |
7b52ad2e | 609 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
610 | clk->name = "arch_mem_timer"; |
611 | clk->rating = 400; | |
612 | clk->cpumask = cpu_all_mask; | |
613 | if (arch_timer_mem_use_virtual) { | |
46c5bfdd | 614 | clk->set_state_shutdown = arch_timer_shutdown_virt_mem; |
cf8c5009 | 615 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; |
22006994 SB |
616 | clk->set_next_event = |
617 | arch_timer_set_next_event_virt_mem; | |
618 | } else { | |
46c5bfdd | 619 | clk->set_state_shutdown = arch_timer_shutdown_phys_mem; |
cf8c5009 | 620 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; |
22006994 SB |
621 | clk->set_next_event = |
622 | arch_timer_set_next_event_phys_mem; | |
623 | } | |
8a4da6e3 MR |
624 | } |
625 | ||
46c5bfdd | 626 | clk->set_state_shutdown(clk); |
8a4da6e3 | 627 | |
22006994 SB |
628 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
629 | } | |
8a4da6e3 | 630 | |
e1ce5c7a NL |
631 | static void arch_timer_evtstrm_enable(int divider) |
632 | { | |
633 | u32 cntkctl = arch_timer_get_cntkctl(); | |
634 | ||
635 | cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; | |
636 | /* Set the divider and enable virtual event stream */ | |
637 | cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | |
638 | | ARCH_TIMER_VIRT_EVT_EN; | |
639 | arch_timer_set_cntkctl(cntkctl); | |
640 | elf_hwcap |= HWCAP_EVTSTRM; | |
641 | #ifdef CONFIG_COMPAT | |
642 | compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; | |
643 | #endif | |
644 | } | |
645 | ||
037f6377 WD |
646 | static void arch_timer_configure_evtstream(void) |
647 | { | |
648 | int evt_stream_div, pos; | |
649 | ||
650 | /* Find the closest power of two to the divisor */ | |
651 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
652 | pos = fls(evt_stream_div); | |
653 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
654 | pos--; | |
655 | /* enable event stream */ | |
656 | arch_timer_evtstrm_enable(min(pos, 15)); | |
657 | } | |
658 | ||
8b8dde00 NL |
659 | static void arch_counter_set_user_access(void) |
660 | { | |
661 | u32 cntkctl = arch_timer_get_cntkctl(); | |
662 | ||
663 | /* Disable user access to the timers and the physical counter */ | |
664 | /* Also disable virtual event stream */ | |
665 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
666 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
667 | | ARCH_TIMER_VIRT_EVT_EN | |
668 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
669 | ||
670 | /* Enable user access to the virtual counter */ | |
671 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
672 | ||
673 | arch_timer_set_cntkctl(cntkctl); | |
674 | } | |
675 | ||
f81f03fa MZ |
676 | static bool arch_timer_has_nonsecure_ppi(void) |
677 | { | |
678 | return (arch_timer_uses_ppi == PHYS_SECURE_PPI && | |
679 | arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
680 | } | |
681 | ||
f005bd7e MZ |
682 | static u32 check_ppi_trigger(int irq) |
683 | { | |
684 | u32 flags = irq_get_trigger_type(irq); | |
685 | ||
686 | if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { | |
687 | pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); | |
688 | pr_warn("WARNING: Please fix your firmware\n"); | |
689 | flags = IRQF_TRIGGER_LOW; | |
690 | } | |
691 | ||
692 | return flags; | |
693 | } | |
694 | ||
7e86e8bd | 695 | static int arch_timer_starting_cpu(unsigned int cpu) |
22006994 | 696 | { |
7e86e8bd | 697 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
f005bd7e | 698 | u32 flags; |
7e86e8bd | 699 | |
22006994 | 700 | __arch_timer_setup(ARCH_CP15_TIMER, clk); |
8a4da6e3 | 701 | |
f005bd7e MZ |
702 | flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); |
703 | enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); | |
f81f03fa | 704 | |
f005bd7e MZ |
705 | if (arch_timer_has_nonsecure_ppi()) { |
706 | flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
707 | enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags); | |
708 | } | |
8a4da6e3 MR |
709 | |
710 | arch_counter_set_user_access(); | |
46fd5c6b | 711 | if (evtstrm_enable) |
037f6377 | 712 | arch_timer_configure_evtstream(); |
8a4da6e3 MR |
713 | |
714 | return 0; | |
715 | } | |
716 | ||
22006994 SB |
717 | static void |
718 | arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) | |
8a4da6e3 | 719 | { |
22006994 SB |
720 | /* Who has more than one independent system counter? */ |
721 | if (arch_timer_rate) | |
722 | return; | |
8a4da6e3 | 723 | |
b09ca1ec HG |
724 | /* |
725 | * Try to determine the frequency from the device tree or CNTFRQ, | |
726 | * if ACPI is enabled, get the frequency from CNTFRQ ONLY. | |
727 | */ | |
728 | if (!acpi_disabled || | |
729 | of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { | |
22006994 SB |
730 | if (cntbase) |
731 | arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); | |
732 | else | |
733 | arch_timer_rate = arch_timer_get_cntfrq(); | |
8a4da6e3 MR |
734 | } |
735 | ||
22006994 SB |
736 | /* Check the timer frequency. */ |
737 | if (arch_timer_rate == 0) | |
738 | pr_warn("Architected timer frequency not available\n"); | |
739 | } | |
740 | ||
741 | static void arch_timer_banner(unsigned type) | |
742 | { | |
743 | pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", | |
744 | type & ARCH_CP15_TIMER ? "cp15" : "", | |
745 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "", | |
746 | type & ARCH_MEM_TIMER ? "mmio" : "", | |
8a4da6e3 MR |
747 | (unsigned long)arch_timer_rate / 1000000, |
748 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
22006994 | 749 | type & ARCH_CP15_TIMER ? |
f81f03fa | 750 | (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" : |
22006994 SB |
751 | "", |
752 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "", | |
753 | type & ARCH_MEM_TIMER ? | |
754 | arch_timer_mem_use_virtual ? "virt" : "phys" : | |
755 | ""); | |
8a4da6e3 MR |
756 | } |
757 | ||
758 | u32 arch_timer_get_rate(void) | |
759 | { | |
760 | return arch_timer_rate; | |
761 | } | |
762 | ||
22006994 | 763 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 764 | { |
22006994 SB |
765 | u32 vct_lo, vct_hi, tmp_hi; |
766 | ||
767 | do { | |
768 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
769 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
770 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
771 | } while (vct_hi != tmp_hi); | |
772 | ||
773 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
774 | } |
775 | ||
b4d6ce97 JG |
776 | static struct arch_timer_kvm_info arch_timer_kvm_info; |
777 | ||
778 | struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) | |
779 | { | |
780 | return &arch_timer_kvm_info; | |
781 | } | |
8a4da6e3 | 782 | |
22006994 SB |
783 | static void __init arch_counter_register(unsigned type) |
784 | { | |
785 | u64 start_count; | |
786 | ||
787 | /* Register the CP15 based counter if we have one */ | |
423bd69e | 788 | if (type & ARCH_CP15_TIMER) { |
f81f03fa | 789 | if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI) |
0b46b8a7 SR |
790 | arch_timer_read_counter = arch_counter_get_cntvct; |
791 | else | |
792 | arch_timer_read_counter = arch_counter_get_cntpct; | |
f6dc1576 | 793 | |
1d8f51d4 SW |
794 | clocksource_counter.archdata.vdso_direct = true; |
795 | ||
16d10ef2 | 796 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
f6dc1576 SW |
797 | /* |
798 | * Don't use the vdso fastpath if errata require using | |
799 | * the out-of-line counter accessor. | |
800 | */ | |
801 | if (static_branch_unlikely(&arch_timer_read_ool_enabled)) | |
1d8f51d4 | 802 | clocksource_counter.archdata.vdso_direct = false; |
f6dc1576 | 803 | #endif |
423bd69e | 804 | } else { |
22006994 | 805 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
423bd69e NL |
806 | } |
807 | ||
d8ec7595 BN |
808 | if (!arch_counter_suspend_stop) |
809 | clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
22006994 SB |
810 | start_count = arch_timer_read_counter(); |
811 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
812 | cyclecounter.mult = clocksource_counter.mult; | |
813 | cyclecounter.shift = clocksource_counter.shift; | |
b4d6ce97 JG |
814 | timecounter_init(&arch_timer_kvm_info.timecounter, |
815 | &cyclecounter, start_count); | |
4a7d3e8a TR |
816 | |
817 | /* 56 bits minimum, so we assume worst case rollover */ | |
818 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
819 | } |
820 | ||
8c37bb3a | 821 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 MR |
822 | { |
823 | pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", | |
824 | clk->irq, smp_processor_id()); | |
825 | ||
f81f03fa MZ |
826 | disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]); |
827 | if (arch_timer_has_nonsecure_ppi()) | |
828 | disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
8a4da6e3 | 829 | |
46c5bfdd | 830 | clk->set_state_shutdown(clk); |
8a4da6e3 MR |
831 | } |
832 | ||
7e86e8bd | 833 | static int arch_timer_dying_cpu(unsigned int cpu) |
8a4da6e3 | 834 | { |
7e86e8bd | 835 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
8a4da6e3 | 836 | |
7e86e8bd RC |
837 | arch_timer_stop(clk); |
838 | return 0; | |
8a4da6e3 MR |
839 | } |
840 | ||
346e7480 SH |
841 | #ifdef CONFIG_CPU_PM |
842 | static unsigned int saved_cntkctl; | |
843 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, | |
844 | unsigned long action, void *hcpu) | |
845 | { | |
846 | if (action == CPU_PM_ENTER) | |
847 | saved_cntkctl = arch_timer_get_cntkctl(); | |
848 | else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) | |
849 | arch_timer_set_cntkctl(saved_cntkctl); | |
850 | return NOTIFY_OK; | |
851 | } | |
852 | ||
853 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
854 | .notifier_call = arch_timer_cpu_pm_notify, | |
855 | }; | |
856 | ||
857 | static int __init arch_timer_cpu_pm_init(void) | |
858 | { | |
859 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
860 | } | |
7e86e8bd RC |
861 | |
862 | static void __init arch_timer_cpu_pm_deinit(void) | |
863 | { | |
864 | WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier)); | |
865 | } | |
866 | ||
346e7480 SH |
867 | #else |
868 | static int __init arch_timer_cpu_pm_init(void) | |
869 | { | |
870 | return 0; | |
871 | } | |
7e86e8bd RC |
872 | |
873 | static void __init arch_timer_cpu_pm_deinit(void) | |
874 | { | |
875 | } | |
346e7480 SH |
876 | #endif |
877 | ||
8a4da6e3 MR |
878 | static int __init arch_timer_register(void) |
879 | { | |
880 | int err; | |
881 | int ppi; | |
882 | ||
8a4da6e3 MR |
883 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
884 | if (!arch_timer_evt) { | |
885 | err = -ENOMEM; | |
886 | goto out; | |
887 | } | |
888 | ||
f81f03fa MZ |
889 | ppi = arch_timer_ppi[arch_timer_uses_ppi]; |
890 | switch (arch_timer_uses_ppi) { | |
891 | case VIRT_PPI: | |
8a4da6e3 MR |
892 | err = request_percpu_irq(ppi, arch_timer_handler_virt, |
893 | "arch_timer", arch_timer_evt); | |
f81f03fa MZ |
894 | break; |
895 | case PHYS_SECURE_PPI: | |
896 | case PHYS_NONSECURE_PPI: | |
8a4da6e3 MR |
897 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
898 | "arch_timer", arch_timer_evt); | |
899 | if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) { | |
900 | ppi = arch_timer_ppi[PHYS_NONSECURE_PPI]; | |
901 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
902 | "arch_timer", arch_timer_evt); | |
903 | if (err) | |
904 | free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], | |
905 | arch_timer_evt); | |
906 | } | |
f81f03fa MZ |
907 | break; |
908 | case HYP_PPI: | |
909 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
910 | "arch_timer", arch_timer_evt); | |
911 | break; | |
912 | default: | |
913 | BUG(); | |
8a4da6e3 MR |
914 | } |
915 | ||
916 | if (err) { | |
917 | pr_err("arch_timer: can't register interrupt %d (%d)\n", | |
918 | ppi, err); | |
919 | goto out_free; | |
920 | } | |
921 | ||
346e7480 SH |
922 | err = arch_timer_cpu_pm_init(); |
923 | if (err) | |
924 | goto out_unreg_notify; | |
925 | ||
8a4da6e3 | 926 | |
7e86e8bd RC |
927 | /* Register and immediately configure the timer on the boot CPU */ |
928 | err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, | |
73c1b41e | 929 | "clockevents/arm/arch_timer:starting", |
7e86e8bd RC |
930 | arch_timer_starting_cpu, arch_timer_dying_cpu); |
931 | if (err) | |
932 | goto out_unreg_cpupm; | |
8a4da6e3 MR |
933 | return 0; |
934 | ||
7e86e8bd RC |
935 | out_unreg_cpupm: |
936 | arch_timer_cpu_pm_deinit(); | |
937 | ||
346e7480 | 938 | out_unreg_notify: |
f81f03fa MZ |
939 | free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt); |
940 | if (arch_timer_has_nonsecure_ppi()) | |
941 | free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], | |
8a4da6e3 | 942 | arch_timer_evt); |
8a4da6e3 MR |
943 | |
944 | out_free: | |
945 | free_percpu(arch_timer_evt); | |
946 | out: | |
947 | return err; | |
948 | } | |
949 | ||
22006994 SB |
950 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
951 | { | |
952 | int ret; | |
953 | irq_handler_t func; | |
954 | struct arch_timer *t; | |
955 | ||
956 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
957 | if (!t) | |
958 | return -ENOMEM; | |
959 | ||
960 | t->base = base; | |
961 | t->evt.irq = irq; | |
962 | __arch_timer_setup(ARCH_MEM_TIMER, &t->evt); | |
963 | ||
964 | if (arch_timer_mem_use_virtual) | |
965 | func = arch_timer_handler_virt_mem; | |
966 | else | |
967 | func = arch_timer_handler_phys_mem; | |
968 | ||
969 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
970 | if (ret) { | |
971 | pr_err("arch_timer: Failed to request mem timer irq\n"); | |
972 | kfree(t); | |
973 | } | |
974 | ||
975 | return ret; | |
976 | } | |
977 | ||
978 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
979 | { .compatible = "arm,armv7-timer", }, | |
980 | { .compatible = "arm,armv8-timer", }, | |
981 | {}, | |
982 | }; | |
983 | ||
984 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
985 | { .compatible = "arm,armv7-timer-mem", }, | |
986 | {}, | |
987 | }; | |
988 | ||
c387f07e | 989 | static bool __init |
566e6dfa | 990 | arch_timer_needs_probing(int type, const struct of_device_id *matches) |
c387f07e SH |
991 | { |
992 | struct device_node *dn; | |
566e6dfa | 993 | bool needs_probing = false; |
c387f07e SH |
994 | |
995 | dn = of_find_matching_node(NULL, matches); | |
59aa896d | 996 | if (dn && of_device_is_available(dn) && !(arch_timers_present & type)) |
566e6dfa | 997 | needs_probing = true; |
c387f07e SH |
998 | of_node_put(dn); |
999 | ||
566e6dfa | 1000 | return needs_probing; |
c387f07e SH |
1001 | } |
1002 | ||
3c0731db | 1003 | static int __init arch_timer_common_init(void) |
22006994 SB |
1004 | { |
1005 | unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER; | |
1006 | ||
1007 | /* Wait until both nodes are probed if we have two timers */ | |
1008 | if ((arch_timers_present & mask) != mask) { | |
566e6dfa | 1009 | if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match)) |
3c0731db | 1010 | return 0; |
566e6dfa | 1011 | if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match)) |
3c0731db | 1012 | return 0; |
22006994 SB |
1013 | } |
1014 | ||
1015 | arch_timer_banner(arch_timers_present); | |
1016 | arch_counter_register(arch_timers_present); | |
3c0731db | 1017 | return arch_timer_arch_init(); |
22006994 SB |
1018 | } |
1019 | ||
3c0731db | 1020 | static int __init arch_timer_init(void) |
8a4da6e3 | 1021 | { |
3c0731db | 1022 | int ret; |
8a4da6e3 | 1023 | /* |
8266891e MZ |
1024 | * If HYP mode is available, we know that the physical timer |
1025 | * has been configured to be accessible from PL1. Use it, so | |
1026 | * that a guest can use the virtual timer instead. | |
1027 | * | |
8a4da6e3 MR |
1028 | * If no interrupt provided for virtual timer, we'll have to |
1029 | * stick to the physical timer. It'd better be accessible... | |
f81f03fa MZ |
1030 | * |
1031 | * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE | |
1032 | * accesses to CNTP_*_EL1 registers are silently redirected to | |
1033 | * their CNTHP_*_EL2 counterparts, and use a different PPI | |
1034 | * number. | |
8a4da6e3 | 1035 | */ |
8266891e | 1036 | if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { |
f81f03fa MZ |
1037 | bool has_ppi; |
1038 | ||
1039 | if (is_kernel_in_hyp_mode()) { | |
1040 | arch_timer_uses_ppi = HYP_PPI; | |
1041 | has_ppi = !!arch_timer_ppi[HYP_PPI]; | |
1042 | } else { | |
1043 | arch_timer_uses_ppi = PHYS_SECURE_PPI; | |
1044 | has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] || | |
1045 | !!arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
1046 | } | |
8a4da6e3 | 1047 | |
f81f03fa | 1048 | if (!has_ppi) { |
8a4da6e3 | 1049 | pr_warn("arch_timer: No interrupt available, giving up\n"); |
3c0731db | 1050 | return -EINVAL; |
8a4da6e3 MR |
1051 | } |
1052 | } | |
1053 | ||
3c0731db DL |
1054 | ret = arch_timer_register(); |
1055 | if (ret) | |
1056 | return ret; | |
1057 | ||
1058 | ret = arch_timer_common_init(); | |
1059 | if (ret) | |
1060 | return ret; | |
d9b5e415 JG |
1061 | |
1062 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI]; | |
3c0731db DL |
1063 | |
1064 | return 0; | |
8a4da6e3 | 1065 | } |
b09ca1ec | 1066 | |
3c0731db | 1067 | static int __init arch_timer_of_init(struct device_node *np) |
b09ca1ec HG |
1068 | { |
1069 | int i; | |
1070 | ||
1071 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
1072 | pr_warn("arch_timer: multiple nodes in dt, skipping\n"); | |
3c0731db | 1073 | return 0; |
b09ca1ec HG |
1074 | } |
1075 | ||
1076 | arch_timers_present |= ARCH_CP15_TIMER; | |
1077 | for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) | |
1078 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); | |
1079 | ||
1080 | arch_timer_detect_rate(NULL, np); | |
1081 | ||
1082 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); | |
1083 | ||
651bb2e9 MZ |
1084 | /* Check for globally applicable workarounds */ |
1085 | arch_timer_check_ool_workaround(ate_match_dt, np); | |
f6dc1576 | 1086 | |
b09ca1ec HG |
1087 | /* |
1088 | * If we cannot rely on firmware initializing the timer registers then | |
1089 | * we should use the physical timers instead. | |
1090 | */ | |
1091 | if (IS_ENABLED(CONFIG_ARM) && | |
1092 | of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) | |
f81f03fa | 1093 | arch_timer_uses_ppi = PHYS_SECURE_PPI; |
b09ca1ec | 1094 | |
d8ec7595 BN |
1095 | /* On some systems, the counter stops ticking when in suspend. */ |
1096 | arch_counter_suspend_stop = of_property_read_bool(np, | |
1097 | "arm,no-tick-in-suspend"); | |
1098 | ||
3c0731db | 1099 | return arch_timer_init(); |
b09ca1ec | 1100 | } |
177cf6e5 DL |
1101 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); |
1102 | CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); | |
22006994 | 1103 | |
3c0731db | 1104 | static int __init arch_timer_mem_init(struct device_node *np) |
22006994 SB |
1105 | { |
1106 | struct device_node *frame, *best_frame = NULL; | |
1107 | void __iomem *cntctlbase, *base; | |
3c0731db | 1108 | unsigned int irq, ret = -EINVAL; |
22006994 SB |
1109 | u32 cnttidr; |
1110 | ||
1111 | arch_timers_present |= ARCH_MEM_TIMER; | |
1112 | cntctlbase = of_iomap(np, 0); | |
1113 | if (!cntctlbase) { | |
1114 | pr_err("arch_timer: Can't find CNTCTLBase\n"); | |
3c0731db | 1115 | return -ENXIO; |
22006994 SB |
1116 | } |
1117 | ||
1118 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
22006994 SB |
1119 | |
1120 | /* | |
1121 | * Try to find a virtual capable frame. Otherwise fall back to a | |
1122 | * physical capable frame. | |
1123 | */ | |
1124 | for_each_available_child_of_node(np, frame) { | |
1125 | int n; | |
e392d603 | 1126 | u32 cntacr; |
22006994 SB |
1127 | |
1128 | if (of_property_read_u32(frame, "frame-number", &n)) { | |
1129 | pr_err("arch_timer: Missing frame-number\n"); | |
22006994 | 1130 | of_node_put(frame); |
e392d603 | 1131 | goto out; |
22006994 SB |
1132 | } |
1133 | ||
e392d603 RM |
1134 | /* Try enabling everything, and see what sticks */ |
1135 | cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | | |
1136 | CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; | |
1137 | writel_relaxed(cntacr, cntctlbase + CNTACR(n)); | |
1138 | cntacr = readl_relaxed(cntctlbase + CNTACR(n)); | |
1139 | ||
1140 | if ((cnttidr & CNTTIDR_VIRT(n)) && | |
1141 | !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { | |
22006994 SB |
1142 | of_node_put(best_frame); |
1143 | best_frame = frame; | |
1144 | arch_timer_mem_use_virtual = true; | |
1145 | break; | |
1146 | } | |
e392d603 RM |
1147 | |
1148 | if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) | |
1149 | continue; | |
1150 | ||
22006994 SB |
1151 | of_node_put(best_frame); |
1152 | best_frame = of_node_get(frame); | |
1153 | } | |
1154 | ||
3c0731db | 1155 | ret= -ENXIO; |
f947ee14 SB |
1156 | base = arch_counter_base = of_io_request_and_map(best_frame, 0, |
1157 | "arch_mem_timer"); | |
1158 | if (IS_ERR(base)) { | |
22006994 | 1159 | pr_err("arch_timer: Can't map frame's registers\n"); |
e392d603 | 1160 | goto out; |
22006994 SB |
1161 | } |
1162 | ||
1163 | if (arch_timer_mem_use_virtual) | |
1164 | irq = irq_of_parse_and_map(best_frame, 1); | |
1165 | else | |
1166 | irq = irq_of_parse_and_map(best_frame, 0); | |
e392d603 | 1167 | |
3c0731db | 1168 | ret = -EINVAL; |
22006994 SB |
1169 | if (!irq) { |
1170 | pr_err("arch_timer: Frame missing %s irq", | |
cfb6d656 | 1171 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
e392d603 | 1172 | goto out; |
22006994 SB |
1173 | } |
1174 | ||
1175 | arch_timer_detect_rate(base, np); | |
3c0731db DL |
1176 | ret = arch_timer_mem_register(base, irq); |
1177 | if (ret) | |
1178 | goto out; | |
1179 | ||
1180 | return arch_timer_common_init(); | |
e392d603 RM |
1181 | out: |
1182 | iounmap(cntctlbase); | |
1183 | of_node_put(best_frame); | |
3c0731db | 1184 | return ret; |
22006994 | 1185 | } |
177cf6e5 | 1186 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", |
22006994 | 1187 | arch_timer_mem_init); |
b09ca1ec HG |
1188 | |
1189 | #ifdef CONFIG_ACPI | |
1190 | static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) | |
1191 | { | |
1192 | int trigger, polarity; | |
1193 | ||
1194 | if (!interrupt) | |
1195 | return 0; | |
1196 | ||
1197 | trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE | |
1198 | : ACPI_LEVEL_SENSITIVE; | |
1199 | ||
1200 | polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW | |
1201 | : ACPI_ACTIVE_HIGH; | |
1202 | ||
1203 | return acpi_register_gsi(NULL, interrupt, trigger, polarity); | |
1204 | } | |
1205 | ||
1206 | /* Initialize per-processor generic timer */ | |
1207 | static int __init arch_timer_acpi_init(struct acpi_table_header *table) | |
1208 | { | |
1209 | struct acpi_table_gtdt *gtdt; | |
1210 | ||
1211 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
1212 | pr_warn("arch_timer: already initialized, skipping\n"); | |
1213 | return -EINVAL; | |
1214 | } | |
1215 | ||
1216 | gtdt = container_of(table, struct acpi_table_gtdt, header); | |
1217 | ||
1218 | arch_timers_present |= ARCH_CP15_TIMER; | |
1219 | ||
1220 | arch_timer_ppi[PHYS_SECURE_PPI] = | |
1221 | map_generic_timer_interrupt(gtdt->secure_el1_interrupt, | |
1222 | gtdt->secure_el1_flags); | |
1223 | ||
1224 | arch_timer_ppi[PHYS_NONSECURE_PPI] = | |
1225 | map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt, | |
1226 | gtdt->non_secure_el1_flags); | |
1227 | ||
1228 | arch_timer_ppi[VIRT_PPI] = | |
1229 | map_generic_timer_interrupt(gtdt->virtual_timer_interrupt, | |
1230 | gtdt->virtual_timer_flags); | |
1231 | ||
1232 | arch_timer_ppi[HYP_PPI] = | |
1233 | map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt, | |
1234 | gtdt->non_secure_el2_flags); | |
1235 | ||
1236 | /* Get the frequency from CNTFRQ */ | |
1237 | arch_timer_detect_rate(NULL, NULL); | |
1238 | ||
1239 | /* Always-on capability */ | |
1240 | arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON); | |
1241 | ||
1242 | arch_timer_init(); | |
1243 | return 0; | |
1244 | } | |
ae281cbd | 1245 | CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); |
b09ca1ec | 1246 | #endif |