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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8a4da6e3 MR |
2 | /* |
3 | * linux/drivers/clocksource/arm_arch_timer.c | |
4 | * | |
5 | * Copyright (C) 2011 ARM Ltd. | |
6 | * All Rights Reserved | |
8a4da6e3 | 7 | */ |
f005bd7e | 8 | |
9155697e | 9 | #define pr_fmt(fmt) "arch_timer: " fmt |
f005bd7e | 10 | |
8a4da6e3 MR |
11 | #include <linux/init.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/smp.h> | |
15 | #include <linux/cpu.h> | |
346e7480 | 16 | #include <linux/cpu_pm.h> |
8a4da6e3 | 17 | #include <linux/clockchips.h> |
7c8f1e78 | 18 | #include <linux/clocksource.h> |
8a4da6e3 MR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/of_irq.h> | |
22006994 | 21 | #include <linux/of_address.h> |
8a4da6e3 | 22 | #include <linux/io.h> |
22006994 | 23 | #include <linux/slab.h> |
e6017571 | 24 | #include <linux/sched/clock.h> |
65cd4f6c | 25 | #include <linux/sched_clock.h> |
b09ca1ec | 26 | #include <linux/acpi.h> |
8a4da6e3 MR |
27 | |
28 | #include <asm/arch_timer.h> | |
8266891e | 29 | #include <asm/virt.h> |
8a4da6e3 MR |
30 | |
31 | #include <clocksource/arm_arch_timer.h> | |
32 | ||
22006994 SB |
33 | #define CNTTIDR 0x08 |
34 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
35 | ||
e392d603 RM |
36 | #define CNTACR(n) (0x40 + ((n) * 4)) |
37 | #define CNTACR_RPCT BIT(0) | |
38 | #define CNTACR_RVCT BIT(1) | |
39 | #define CNTACR_RFRQ BIT(2) | |
40 | #define CNTACR_RVOFF BIT(3) | |
41 | #define CNTACR_RWVT BIT(4) | |
42 | #define CNTACR_RWPT BIT(5) | |
43 | ||
22006994 SB |
44 | #define CNTVCT_LO 0x08 |
45 | #define CNTVCT_HI 0x0c | |
46 | #define CNTFRQ 0x10 | |
47 | #define CNTP_TVAL 0x28 | |
48 | #define CNTP_CTL 0x2c | |
49 | #define CNTV_TVAL 0x38 | |
50 | #define CNTV_CTL 0x3c | |
51 | ||
22006994 SB |
52 | static unsigned arch_timers_present __initdata; |
53 | ||
54 | static void __iomem *arch_counter_base; | |
55 | ||
56 | struct arch_timer { | |
57 | void __iomem *base; | |
58 | struct clock_event_device evt; | |
59 | }; | |
60 | ||
61 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
62 | ||
8a4da6e3 | 63 | static u32 arch_timer_rate; |
ee34f1e6 | 64 | static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI]; |
8a4da6e3 MR |
65 | |
66 | static struct clock_event_device __percpu *arch_timer_evt; | |
67 | ||
ee34f1e6 | 68 | static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI; |
82a56194 | 69 | static bool arch_timer_c3stop; |
22006994 | 70 | static bool arch_timer_mem_use_virtual; |
d8ec7595 | 71 | static bool arch_counter_suspend_stop; |
a67de48b | 72 | #ifdef CONFIG_GENERIC_GETTIMEOFDAY |
5e3c6a31 | 73 | static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER; |
a67de48b VF |
74 | #else |
75 | static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE; | |
76 | #endif /* CONFIG_GENERIC_GETTIMEOFDAY */ | |
8a4da6e3 | 77 | |
ec5c8e42 | 78 | static cpumask_t evtstrm_available = CPU_MASK_NONE; |
46fd5c6b WD |
79 | static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); |
80 | ||
81 | static int __init early_evtstrm_cfg(char *buf) | |
82 | { | |
83 | return strtobool(buf, &evtstrm_enable); | |
84 | } | |
85 | early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); | |
86 | ||
8a4da6e3 MR |
87 | /* |
88 | * Architected system timer support. | |
89 | */ | |
90 | ||
f4e00a1a MZ |
91 | static __always_inline |
92 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
93 | struct clock_event_device *clk) | |
94 | { | |
95 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
96 | struct arch_timer *timer = to_arch_timer(clk); | |
97 | switch (reg) { | |
98 | case ARCH_TIMER_REG_CTRL: | |
99 | writel_relaxed(val, timer->base + CNTP_CTL); | |
100 | break; | |
101 | case ARCH_TIMER_REG_TVAL: | |
102 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
103 | break; | |
104 | } | |
105 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
106 | struct arch_timer *timer = to_arch_timer(clk); | |
107 | switch (reg) { | |
108 | case ARCH_TIMER_REG_CTRL: | |
109 | writel_relaxed(val, timer->base + CNTV_CTL); | |
110 | break; | |
111 | case ARCH_TIMER_REG_TVAL: | |
112 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
113 | break; | |
114 | } | |
115 | } else { | |
116 | arch_timer_reg_write_cp15(access, reg, val); | |
117 | } | |
118 | } | |
119 | ||
120 | static __always_inline | |
121 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
122 | struct clock_event_device *clk) | |
123 | { | |
124 | u32 val; | |
125 | ||
126 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
127 | struct arch_timer *timer = to_arch_timer(clk); | |
128 | switch (reg) { | |
129 | case ARCH_TIMER_REG_CTRL: | |
130 | val = readl_relaxed(timer->base + CNTP_CTL); | |
131 | break; | |
132 | case ARCH_TIMER_REG_TVAL: | |
133 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
134 | break; | |
135 | } | |
136 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
137 | struct arch_timer *timer = to_arch_timer(clk); | |
138 | switch (reg) { | |
139 | case ARCH_TIMER_REG_CTRL: | |
140 | val = readl_relaxed(timer->base + CNTV_CTL); | |
141 | break; | |
142 | case ARCH_TIMER_REG_TVAL: | |
143 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
144 | break; | |
145 | } | |
146 | } else { | |
147 | val = arch_timer_reg_read_cp15(access, reg); | |
148 | } | |
149 | ||
150 | return val; | |
151 | } | |
152 | ||
5d6168fc | 153 | static notrace u64 arch_counter_get_cntpct_stable(void) |
0ea41539 MZ |
154 | { |
155 | return __arch_counter_get_cntpct_stable(); | |
156 | } | |
157 | ||
5d6168fc | 158 | static notrace u64 arch_counter_get_cntpct(void) |
0ea41539 MZ |
159 | { |
160 | return __arch_counter_get_cntpct(); | |
161 | } | |
162 | ||
5d6168fc | 163 | static notrace u64 arch_counter_get_cntvct_stable(void) |
0ea41539 MZ |
164 | { |
165 | return __arch_counter_get_cntvct_stable(); | |
166 | } | |
167 | ||
5d6168fc | 168 | static notrace u64 arch_counter_get_cntvct(void) |
0ea41539 MZ |
169 | { |
170 | return __arch_counter_get_cntvct(); | |
171 | } | |
172 | ||
992dd16f MZ |
173 | /* |
174 | * Default to cp15 based access because arm64 uses this function for | |
175 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
176 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
177 | * if we don't have the cp15 accessors we won't have a problem. | |
178 | */ | |
179 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
e6d68b00 | 180 | EXPORT_SYMBOL_GPL(arch_timer_read_counter); |
992dd16f MZ |
181 | |
182 | static u64 arch_counter_read(struct clocksource *cs) | |
183 | { | |
184 | return arch_timer_read_counter(); | |
185 | } | |
186 | ||
187 | static u64 arch_counter_read_cc(const struct cyclecounter *cc) | |
188 | { | |
189 | return arch_timer_read_counter(); | |
190 | } | |
191 | ||
192 | static struct clocksource clocksource_counter = { | |
193 | .name = "arch_sys_counter", | |
194 | .rating = 400, | |
195 | .read = arch_counter_read, | |
196 | .mask = CLOCKSOURCE_MASK(56), | |
197 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
198 | }; | |
199 | ||
200 | static struct cyclecounter cyclecounter __ro_after_init = { | |
201 | .read = arch_counter_read_cc, | |
202 | .mask = CLOCKSOURCE_MASK(56), | |
203 | }; | |
204 | ||
5a38bcac MZ |
205 | struct ate_acpi_oem_info { |
206 | char oem_id[ACPI_OEM_ID_SIZE + 1]; | |
207 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; | |
208 | u32 oem_revision; | |
209 | }; | |
210 | ||
f6dc1576 | 211 | #ifdef CONFIG_FSL_ERRATUM_A008585 |
16d10ef2 DT |
212 | /* |
213 | * The number of retries is an arbitrary value well beyond the highest number | |
214 | * of iterations the loop has been observed to take. | |
215 | */ | |
216 | #define __fsl_a008585_read_reg(reg) ({ \ | |
217 | u64 _old, _new; \ | |
218 | int _retries = 200; \ | |
219 | \ | |
220 | do { \ | |
221 | _old = read_sysreg(reg); \ | |
222 | _new = read_sysreg(reg); \ | |
223 | _retries--; \ | |
224 | } while (unlikely(_old != _new) && _retries); \ | |
225 | \ | |
226 | WARN_ON_ONCE(!_retries); \ | |
227 | _new; \ | |
228 | }) | |
229 | ||
230 | static u32 notrace fsl_a008585_read_cntp_tval_el0(void) | |
f6dc1576 SW |
231 | { |
232 | return __fsl_a008585_read_reg(cntp_tval_el0); | |
233 | } | |
234 | ||
16d10ef2 | 235 | static u32 notrace fsl_a008585_read_cntv_tval_el0(void) |
f6dc1576 SW |
236 | { |
237 | return __fsl_a008585_read_reg(cntv_tval_el0); | |
238 | } | |
239 | ||
f2e600c1 CD |
240 | static u64 notrace fsl_a008585_read_cntpct_el0(void) |
241 | { | |
242 | return __fsl_a008585_read_reg(cntpct_el0); | |
243 | } | |
244 | ||
16d10ef2 | 245 | static u64 notrace fsl_a008585_read_cntvct_el0(void) |
f6dc1576 SW |
246 | { |
247 | return __fsl_a008585_read_reg(cntvct_el0); | |
248 | } | |
16d10ef2 DT |
249 | #endif |
250 | ||
bb42ca47 DT |
251 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
252 | /* | |
253 | * Verify whether the value of the second read is larger than the first by | |
254 | * less than 32 is the only way to confirm the value is correct, so clear the | |
255 | * lower 5 bits to check whether the difference is greater than 32 or not. | |
256 | * Theoretically the erratum should not occur more than twice in succession | |
257 | * when reading the system counter, but it is possible that some interrupts | |
258 | * may lead to more than twice read errors, triggering the warning, so setting | |
259 | * the number of retries far beyond the number of iterations the loop has been | |
260 | * observed to take. | |
261 | */ | |
262 | #define __hisi_161010101_read_reg(reg) ({ \ | |
263 | u64 _old, _new; \ | |
264 | int _retries = 50; \ | |
265 | \ | |
266 | do { \ | |
267 | _old = read_sysreg(reg); \ | |
268 | _new = read_sysreg(reg); \ | |
269 | _retries--; \ | |
270 | } while (unlikely((_new - _old) >> 5) && _retries); \ | |
271 | \ | |
272 | WARN_ON_ONCE(!_retries); \ | |
273 | _new; \ | |
274 | }) | |
275 | ||
276 | static u32 notrace hisi_161010101_read_cntp_tval_el0(void) | |
277 | { | |
278 | return __hisi_161010101_read_reg(cntp_tval_el0); | |
279 | } | |
280 | ||
281 | static u32 notrace hisi_161010101_read_cntv_tval_el0(void) | |
282 | { | |
283 | return __hisi_161010101_read_reg(cntv_tval_el0); | |
284 | } | |
285 | ||
f2e600c1 CD |
286 | static u64 notrace hisi_161010101_read_cntpct_el0(void) |
287 | { | |
288 | return __hisi_161010101_read_reg(cntpct_el0); | |
289 | } | |
290 | ||
bb42ca47 DT |
291 | static u64 notrace hisi_161010101_read_cntvct_el0(void) |
292 | { | |
293 | return __hisi_161010101_read_reg(cntvct_el0); | |
294 | } | |
d003d029 MZ |
295 | |
296 | static struct ate_acpi_oem_info hisi_161010101_oem_info[] = { | |
297 | /* | |
298 | * Note that trailing spaces are required to properly match | |
299 | * the OEM table information. | |
300 | */ | |
301 | { | |
302 | .oem_id = "HISI ", | |
303 | .oem_table_id = "HIP05 ", | |
304 | .oem_revision = 0, | |
305 | }, | |
306 | { | |
307 | .oem_id = "HISI ", | |
308 | .oem_table_id = "HIP06 ", | |
309 | .oem_revision = 0, | |
310 | }, | |
311 | { | |
312 | .oem_id = "HISI ", | |
313 | .oem_table_id = "HIP07 ", | |
314 | .oem_revision = 0, | |
315 | }, | |
316 | { /* Sentinel indicating the end of the OEM array */ }, | |
317 | }; | |
bb42ca47 DT |
318 | #endif |
319 | ||
fa8d815f | 320 | #ifdef CONFIG_ARM64_ERRATUM_858921 |
f2e600c1 CD |
321 | static u64 notrace arm64_858921_read_cntpct_el0(void) |
322 | { | |
323 | u64 old, new; | |
324 | ||
325 | old = read_sysreg(cntpct_el0); | |
326 | new = read_sysreg(cntpct_el0); | |
327 | return (((old ^ new) >> 32) & 1) ? old : new; | |
328 | } | |
329 | ||
fa8d815f MZ |
330 | static u64 notrace arm64_858921_read_cntvct_el0(void) |
331 | { | |
332 | u64 old, new; | |
333 | ||
334 | old = read_sysreg(cntvct_el0); | |
335 | new = read_sysreg(cntvct_el0); | |
336 | return (((old ^ new) >> 32) & 1) ? old : new; | |
337 | } | |
338 | #endif | |
339 | ||
c950ca8c SH |
340 | #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 |
341 | /* | |
342 | * The low bits of the counter registers are indeterminate while bit 10 or | |
343 | * greater is rolling over. Since the counter value can jump both backward | |
344 | * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values | |
345 | * with all ones or all zeros in the low bits. Bound the loop by the maximum | |
346 | * number of CPU cycles in 3 consecutive 24 MHz counter periods. | |
347 | */ | |
348 | #define __sun50i_a64_read_reg(reg) ({ \ | |
349 | u64 _val; \ | |
350 | int _retries = 150; \ | |
351 | \ | |
352 | do { \ | |
353 | _val = read_sysreg(reg); \ | |
354 | _retries--; \ | |
355 | } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \ | |
356 | \ | |
357 | WARN_ON_ONCE(!_retries); \ | |
358 | _val; \ | |
359 | }) | |
360 | ||
361 | static u64 notrace sun50i_a64_read_cntpct_el0(void) | |
362 | { | |
363 | return __sun50i_a64_read_reg(cntpct_el0); | |
364 | } | |
365 | ||
366 | static u64 notrace sun50i_a64_read_cntvct_el0(void) | |
367 | { | |
368 | return __sun50i_a64_read_reg(cntvct_el0); | |
369 | } | |
370 | ||
371 | static u32 notrace sun50i_a64_read_cntp_tval_el0(void) | |
372 | { | |
373 | return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0(); | |
374 | } | |
375 | ||
376 | static u32 notrace sun50i_a64_read_cntv_tval_el0(void) | |
377 | { | |
378 | return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0(); | |
379 | } | |
380 | #endif | |
381 | ||
16d10ef2 | 382 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
a7fb4577 | 383 | DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); |
16d10ef2 DT |
384 | EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); |
385 | ||
0ea41539 | 386 | static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0); |
16d10ef2 | 387 | |
8328089f MZ |
388 | static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, |
389 | struct clock_event_device *clk) | |
390 | { | |
391 | unsigned long ctrl; | |
e6d68b00 | 392 | u64 cval; |
8328089f MZ |
393 | |
394 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
395 | ctrl |= ARCH_TIMER_CTRL_ENABLE; | |
396 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
397 | ||
e6d68b00 CD |
398 | if (access == ARCH_TIMER_PHYS_ACCESS) { |
399 | cval = evt + arch_counter_get_cntpct(); | |
8328089f | 400 | write_sysreg(cval, cntp_cval_el0); |
e6d68b00 CD |
401 | } else { |
402 | cval = evt + arch_counter_get_cntvct(); | |
8328089f | 403 | write_sysreg(cval, cntv_cval_el0); |
e6d68b00 | 404 | } |
8328089f MZ |
405 | |
406 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
407 | } | |
408 | ||
eb645221 | 409 | static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt, |
8328089f MZ |
410 | struct clock_event_device *clk) |
411 | { | |
412 | erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk); | |
413 | return 0; | |
414 | } | |
415 | ||
eb645221 | 416 | static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt, |
8328089f MZ |
417 | struct clock_event_device *clk) |
418 | { | |
419 | erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk); | |
420 | return 0; | |
421 | } | |
422 | ||
16d10ef2 DT |
423 | static const struct arch_timer_erratum_workaround ool_workarounds[] = { |
424 | #ifdef CONFIG_FSL_ERRATUM_A008585 | |
425 | { | |
651bb2e9 | 426 | .match_type = ate_match_dt, |
16d10ef2 | 427 | .id = "fsl,erratum-a008585", |
651bb2e9 | 428 | .desc = "Freescale erratum a005858", |
16d10ef2 DT |
429 | .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, |
430 | .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, | |
f2e600c1 | 431 | .read_cntpct_el0 = fsl_a008585_read_cntpct_el0, |
16d10ef2 | 432 | .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, |
01d3e3ff MZ |
433 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
434 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
16d10ef2 DT |
435 | }, |
436 | #endif | |
bb42ca47 DT |
437 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
438 | { | |
651bb2e9 | 439 | .match_type = ate_match_dt, |
bb42ca47 | 440 | .id = "hisilicon,erratum-161010101", |
651bb2e9 | 441 | .desc = "HiSilicon erratum 161010101", |
bb42ca47 DT |
442 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, |
443 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
f2e600c1 | 444 | .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, |
bb42ca47 | 445 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, |
01d3e3ff MZ |
446 | .set_next_event_phys = erratum_set_next_event_tval_phys, |
447 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
d003d029 MZ |
448 | }, |
449 | { | |
450 | .match_type = ate_match_acpi_oem_info, | |
451 | .id = hisi_161010101_oem_info, | |
452 | .desc = "HiSilicon erratum 161010101", | |
453 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, | |
454 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
f2e600c1 | 455 | .read_cntpct_el0 = hisi_161010101_read_cntpct_el0, |
d003d029 MZ |
456 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, |
457 | .set_next_event_phys = erratum_set_next_event_tval_phys, | |
458 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
bb42ca47 DT |
459 | }, |
460 | #endif | |
fa8d815f MZ |
461 | #ifdef CONFIG_ARM64_ERRATUM_858921 |
462 | { | |
463 | .match_type = ate_match_local_cap_id, | |
464 | .id = (void *)ARM64_WORKAROUND_858921, | |
465 | .desc = "ARM erratum 858921", | |
f2e600c1 | 466 | .read_cntpct_el0 = arm64_858921_read_cntpct_el0, |
fa8d815f MZ |
467 | .read_cntvct_el0 = arm64_858921_read_cntvct_el0, |
468 | }, | |
469 | #endif | |
c950ca8c SH |
470 | #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 |
471 | { | |
472 | .match_type = ate_match_dt, | |
473 | .id = "allwinner,erratum-unknown1", | |
474 | .desc = "Allwinner erratum UNKNOWN1", | |
475 | .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0, | |
476 | .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0, | |
477 | .read_cntpct_el0 = sun50i_a64_read_cntpct_el0, | |
478 | .read_cntvct_el0 = sun50i_a64_read_cntvct_el0, | |
479 | .set_next_event_phys = erratum_set_next_event_tval_phys, | |
480 | .set_next_event_virt = erratum_set_next_event_tval_virt, | |
481 | }, | |
482 | #endif | |
16d10ef2 | 483 | }; |
651bb2e9 MZ |
484 | |
485 | typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, | |
486 | const void *); | |
487 | ||
488 | static | |
489 | bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa, | |
490 | const void *arg) | |
491 | { | |
492 | const struct device_node *np = arg; | |
493 | ||
494 | return of_property_read_bool(np, wa->id); | |
495 | } | |
496 | ||
0064030c MZ |
497 | static |
498 | bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa, | |
499 | const void *arg) | |
500 | { | |
501 | return this_cpu_has_cap((uintptr_t)wa->id); | |
502 | } | |
503 | ||
5a38bcac MZ |
504 | |
505 | static | |
506 | bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa, | |
507 | const void *arg) | |
508 | { | |
509 | static const struct ate_acpi_oem_info empty_oem_info = {}; | |
510 | const struct ate_acpi_oem_info *info = wa->id; | |
511 | const struct acpi_table_header *table = arg; | |
512 | ||
513 | /* Iterate over the ACPI OEM info array, looking for a match */ | |
514 | while (memcmp(info, &empty_oem_info, sizeof(*info))) { | |
515 | if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) && | |
516 | !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && | |
517 | info->oem_revision == table->oem_revision) | |
518 | return true; | |
519 | ||
520 | info++; | |
521 | } | |
522 | ||
523 | return false; | |
524 | } | |
525 | ||
651bb2e9 MZ |
526 | static const struct arch_timer_erratum_workaround * |
527 | arch_timer_iterate_errata(enum arch_timer_erratum_match_type type, | |
528 | ate_match_fn_t match_fn, | |
529 | void *arg) | |
530 | { | |
531 | int i; | |
532 | ||
533 | for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { | |
534 | if (ool_workarounds[i].match_type != type) | |
535 | continue; | |
536 | ||
537 | if (match_fn(&ool_workarounds[i], arg)) | |
538 | return &ool_workarounds[i]; | |
539 | } | |
540 | ||
541 | return NULL; | |
542 | } | |
543 | ||
544 | static | |
6acc71cc MZ |
545 | void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa, |
546 | bool local) | |
651bb2e9 | 547 | { |
6acc71cc MZ |
548 | int i; |
549 | ||
550 | if (local) { | |
551 | __this_cpu_write(timer_unstable_counter_workaround, wa); | |
552 | } else { | |
553 | for_each_possible_cpu(i) | |
554 | per_cpu(timer_unstable_counter_workaround, i) = wa; | |
555 | } | |
556 | ||
0ea41539 MZ |
557 | if (wa->read_cntvct_el0 || wa->read_cntpct_el0) |
558 | atomic_set(&timer_unstable_counter_workaround_in_use, 1); | |
a86bd139 MZ |
559 | |
560 | /* | |
561 | * Don't use the vdso fastpath if errata require using the | |
562 | * out-of-line counter accessor. We may change our mind pretty | |
563 | * late in the game (with a per-CPU erratum, for example), so | |
564 | * change both the default value and the vdso itself. | |
565 | */ | |
566 | if (wa->read_cntvct_el0) { | |
5e3c6a31 TG |
567 | clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE; |
568 | vdso_default = VDSO_CLOCKMODE_NONE; | |
a86bd139 | 569 | } |
651bb2e9 MZ |
570 | } |
571 | ||
572 | static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type, | |
573 | void *arg) | |
574 | { | |
a862fc22 | 575 | const struct arch_timer_erratum_workaround *wa, *__wa; |
651bb2e9 | 576 | ate_match_fn_t match_fn = NULL; |
0064030c | 577 | bool local = false; |
651bb2e9 MZ |
578 | |
579 | switch (type) { | |
580 | case ate_match_dt: | |
581 | match_fn = arch_timer_check_dt_erratum; | |
582 | break; | |
0064030c MZ |
583 | case ate_match_local_cap_id: |
584 | match_fn = arch_timer_check_local_cap_erratum; | |
585 | local = true; | |
586 | break; | |
5a38bcac MZ |
587 | case ate_match_acpi_oem_info: |
588 | match_fn = arch_timer_check_acpi_oem_erratum; | |
589 | break; | |
651bb2e9 MZ |
590 | default: |
591 | WARN_ON(1); | |
592 | return; | |
593 | } | |
594 | ||
595 | wa = arch_timer_iterate_errata(type, match_fn, arg); | |
596 | if (!wa) | |
597 | return; | |
598 | ||
a862fc22 MZ |
599 | __wa = __this_cpu_read(timer_unstable_counter_workaround); |
600 | if (__wa && wa != __wa) | |
601 | pr_warn("Can't enable workaround for %s (clashes with %s\n)", | |
602 | wa->desc, __wa->desc); | |
6acc71cc | 603 | |
a862fc22 MZ |
604 | if (__wa) |
605 | return; | |
0064030c | 606 | |
6acc71cc | 607 | arch_timer_enable_workaround(wa, local); |
0064030c MZ |
608 | pr_info("Enabling %s workaround for %s\n", |
609 | local ? "local" : "global", wa->desc); | |
651bb2e9 MZ |
610 | } |
611 | ||
a86bd139 MZ |
612 | static bool arch_timer_this_cpu_has_cntvct_wa(void) |
613 | { | |
5ef19a16 | 614 | return has_erratum_handler(read_cntvct_el0); |
a86bd139 | 615 | } |
a86bd139 | 616 | |
0ea41539 MZ |
617 | static bool arch_timer_counter_has_wa(void) |
618 | { | |
619 | return atomic_read(&timer_unstable_counter_workaround_in_use); | |
a86bd139 | 620 | } |
651bb2e9 MZ |
621 | #else |
622 | #define arch_timer_check_ool_workaround(t,a) do { } while(0) | |
a86bd139 | 623 | #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) |
0ea41539 | 624 | #define arch_timer_counter_has_wa() ({false;}) |
16d10ef2 | 625 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ |
f6dc1576 | 626 | |
e09f3cc0 | 627 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
628 | struct clock_event_device *evt) |
629 | { | |
630 | unsigned long ctrl; | |
cfb6d656 | 631 | |
60faddf6 | 632 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
633 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
634 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 635 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
636 | evt->event_handler(evt); |
637 | return IRQ_HANDLED; | |
638 | } | |
639 | ||
640 | return IRQ_NONE; | |
641 | } | |
642 | ||
643 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
644 | { | |
645 | struct clock_event_device *evt = dev_id; | |
646 | ||
647 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
648 | } | |
649 | ||
650 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
651 | { | |
652 | struct clock_event_device *evt = dev_id; | |
653 | ||
654 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
655 | } | |
656 | ||
22006994 SB |
657 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
658 | { | |
659 | struct clock_event_device *evt = dev_id; | |
660 | ||
661 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
662 | } | |
663 | ||
664 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
665 | { | |
666 | struct clock_event_device *evt = dev_id; | |
667 | ||
668 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
669 | } | |
670 | ||
46c5bfdd VK |
671 | static __always_inline int timer_shutdown(const int access, |
672 | struct clock_event_device *clk) | |
8a4da6e3 MR |
673 | { |
674 | unsigned long ctrl; | |
46c5bfdd VK |
675 | |
676 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
677 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; | |
678 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
679 | ||
680 | return 0; | |
8a4da6e3 MR |
681 | } |
682 | ||
46c5bfdd | 683 | static int arch_timer_shutdown_virt(struct clock_event_device *clk) |
8a4da6e3 | 684 | { |
46c5bfdd | 685 | return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk); |
8a4da6e3 MR |
686 | } |
687 | ||
46c5bfdd | 688 | static int arch_timer_shutdown_phys(struct clock_event_device *clk) |
8a4da6e3 | 689 | { |
46c5bfdd | 690 | return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); |
8a4da6e3 MR |
691 | } |
692 | ||
46c5bfdd | 693 | static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) |
22006994 | 694 | { |
46c5bfdd | 695 | return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); |
8a4da6e3 MR |
696 | } |
697 | ||
46c5bfdd | 698 | static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) |
22006994 | 699 | { |
46c5bfdd | 700 | return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); |
22006994 SB |
701 | } |
702 | ||
60faddf6 | 703 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 704 | struct clock_event_device *clk) |
8a4da6e3 MR |
705 | { |
706 | unsigned long ctrl; | |
60faddf6 | 707 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
708 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
709 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
710 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
711 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
712 | } |
713 | ||
714 | static int arch_timer_set_next_event_virt(unsigned long evt, | |
60faddf6 | 715 | struct clock_event_device *clk) |
8a4da6e3 | 716 | { |
60faddf6 | 717 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
718 | return 0; |
719 | } | |
720 | ||
721 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 722 | struct clock_event_device *clk) |
8a4da6e3 | 723 | { |
60faddf6 | 724 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
725 | return 0; |
726 | } | |
727 | ||
22006994 SB |
728 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
729 | struct clock_event_device *clk) | |
8a4da6e3 | 730 | { |
22006994 SB |
731 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
732 | return 0; | |
733 | } | |
734 | ||
735 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
736 | struct clock_event_device *clk) | |
737 | { | |
738 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
739 | return 0; | |
740 | } | |
741 | ||
cfb6d656 TG |
742 | static void __arch_timer_setup(unsigned type, |
743 | struct clock_event_device *clk) | |
22006994 SB |
744 | { |
745 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
746 | ||
8a5c21dc | 747 | if (type == ARCH_TIMER_TYPE_CP15) { |
5ef19a16 MZ |
748 | typeof(clk->set_next_event) sne; |
749 | ||
750 | arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); | |
751 | ||
82a56194 LP |
752 | if (arch_timer_c3stop) |
753 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
754 | clk->name = "arch_sys_timer"; |
755 | clk->rating = 450; | |
756 | clk->cpumask = cpumask_of(smp_processor_id()); | |
f81f03fa MZ |
757 | clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; |
758 | switch (arch_timer_uses_ppi) { | |
ee34f1e6 | 759 | case ARCH_TIMER_VIRT_PPI: |
46c5bfdd | 760 | clk->set_state_shutdown = arch_timer_shutdown_virt; |
cf8c5009 | 761 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; |
5ef19a16 | 762 | sne = erratum_handler(set_next_event_virt); |
f81f03fa | 763 | break; |
ee34f1e6 FW |
764 | case ARCH_TIMER_PHYS_SECURE_PPI: |
765 | case ARCH_TIMER_PHYS_NONSECURE_PPI: | |
766 | case ARCH_TIMER_HYP_PPI: | |
46c5bfdd | 767 | clk->set_state_shutdown = arch_timer_shutdown_phys; |
cf8c5009 | 768 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; |
5ef19a16 | 769 | sne = erratum_handler(set_next_event_phys); |
f81f03fa MZ |
770 | break; |
771 | default: | |
772 | BUG(); | |
22006994 | 773 | } |
f6dc1576 | 774 | |
5ef19a16 | 775 | clk->set_next_event = sne; |
8a4da6e3 | 776 | } else { |
7b52ad2e | 777 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
778 | clk->name = "arch_mem_timer"; |
779 | clk->rating = 400; | |
5e18e412 | 780 | clk->cpumask = cpu_possible_mask; |
22006994 | 781 | if (arch_timer_mem_use_virtual) { |
46c5bfdd | 782 | clk->set_state_shutdown = arch_timer_shutdown_virt_mem; |
cf8c5009 | 783 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; |
22006994 SB |
784 | clk->set_next_event = |
785 | arch_timer_set_next_event_virt_mem; | |
786 | } else { | |
46c5bfdd | 787 | clk->set_state_shutdown = arch_timer_shutdown_phys_mem; |
cf8c5009 | 788 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; |
22006994 SB |
789 | clk->set_next_event = |
790 | arch_timer_set_next_event_phys_mem; | |
791 | } | |
8a4da6e3 MR |
792 | } |
793 | ||
46c5bfdd | 794 | clk->set_state_shutdown(clk); |
8a4da6e3 | 795 | |
22006994 SB |
796 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
797 | } | |
8a4da6e3 | 798 | |
e1ce5c7a NL |
799 | static void arch_timer_evtstrm_enable(int divider) |
800 | { | |
801 | u32 cntkctl = arch_timer_get_cntkctl(); | |
802 | ||
803 | cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; | |
804 | /* Set the divider and enable virtual event stream */ | |
805 | cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | |
806 | | ARCH_TIMER_VIRT_EVT_EN; | |
807 | arch_timer_set_cntkctl(cntkctl); | |
5a354412 | 808 | arch_timer_set_evtstrm_feature(); |
ec5c8e42 | 809 | cpumask_set_cpu(smp_processor_id(), &evtstrm_available); |
e1ce5c7a NL |
810 | } |
811 | ||
037f6377 WD |
812 | static void arch_timer_configure_evtstream(void) |
813 | { | |
814 | int evt_stream_div, pos; | |
815 | ||
816 | /* Find the closest power of two to the divisor */ | |
817 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
818 | pos = fls(evt_stream_div); | |
819 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
820 | pos--; | |
821 | /* enable event stream */ | |
822 | arch_timer_evtstrm_enable(min(pos, 15)); | |
823 | } | |
824 | ||
8b8dde00 NL |
825 | static void arch_counter_set_user_access(void) |
826 | { | |
827 | u32 cntkctl = arch_timer_get_cntkctl(); | |
828 | ||
a86bd139 | 829 | /* Disable user access to the timers and both counters */ |
8b8dde00 NL |
830 | /* Also disable virtual event stream */ |
831 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
832 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
a86bd139 | 833 | | ARCH_TIMER_USR_VCT_ACCESS_EN |
8b8dde00 NL |
834 | | ARCH_TIMER_VIRT_EVT_EN |
835 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
836 | ||
a86bd139 MZ |
837 | /* |
838 | * Enable user access to the virtual counter if it doesn't | |
839 | * need to be workaround. The vdso may have been already | |
840 | * disabled though. | |
841 | */ | |
842 | if (arch_timer_this_cpu_has_cntvct_wa()) | |
843 | pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id()); | |
844 | else | |
845 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
8b8dde00 NL |
846 | |
847 | arch_timer_set_cntkctl(cntkctl); | |
848 | } | |
849 | ||
f81f03fa MZ |
850 | static bool arch_timer_has_nonsecure_ppi(void) |
851 | { | |
ee34f1e6 FW |
852 | return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI && |
853 | arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); | |
f81f03fa MZ |
854 | } |
855 | ||
f005bd7e MZ |
856 | static u32 check_ppi_trigger(int irq) |
857 | { | |
858 | u32 flags = irq_get_trigger_type(irq); | |
859 | ||
860 | if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { | |
861 | pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); | |
862 | pr_warn("WARNING: Please fix your firmware\n"); | |
863 | flags = IRQF_TRIGGER_LOW; | |
864 | } | |
865 | ||
866 | return flags; | |
867 | } | |
868 | ||
7e86e8bd | 869 | static int arch_timer_starting_cpu(unsigned int cpu) |
22006994 | 870 | { |
7e86e8bd | 871 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
f005bd7e | 872 | u32 flags; |
7e86e8bd | 873 | |
8a5c21dc | 874 | __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk); |
8a4da6e3 | 875 | |
f005bd7e MZ |
876 | flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); |
877 | enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); | |
f81f03fa | 878 | |
f005bd7e | 879 | if (arch_timer_has_nonsecure_ppi()) { |
ee34f1e6 FW |
880 | flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); |
881 | enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI], | |
882 | flags); | |
f005bd7e | 883 | } |
8a4da6e3 MR |
884 | |
885 | arch_counter_set_user_access(); | |
46fd5c6b | 886 | if (evtstrm_enable) |
037f6377 | 887 | arch_timer_configure_evtstream(); |
8a4da6e3 MR |
888 | |
889 | return 0; | |
890 | } | |
891 | ||
5d3dfa96 FW |
892 | /* |
893 | * For historical reasons, when probing with DT we use whichever (non-zero) | |
894 | * rate was probed first, and don't verify that others match. If the first node | |
895 | * probed has a clock-frequency property, this overrides the HW register. | |
896 | */ | |
897 | static void arch_timer_of_configure_rate(u32 rate, struct device_node *np) | |
8a4da6e3 | 898 | { |
22006994 SB |
899 | /* Who has more than one independent system counter? */ |
900 | if (arch_timer_rate) | |
901 | return; | |
8a4da6e3 | 902 | |
5d3dfa96 FW |
903 | if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) |
904 | arch_timer_rate = rate; | |
8a4da6e3 | 905 | |
22006994 SB |
906 | /* Check the timer frequency. */ |
907 | if (arch_timer_rate == 0) | |
ded24019 | 908 | pr_warn("frequency not available\n"); |
22006994 SB |
909 | } |
910 | ||
911 | static void arch_timer_banner(unsigned type) | |
912 | { | |
ded24019 | 913 | pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", |
8a5c21dc FW |
914 | type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "", |
915 | type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? | |
916 | " and " : "", | |
917 | type & ARCH_TIMER_TYPE_MEM ? "mmio" : "", | |
ded24019 FW |
918 | (unsigned long)arch_timer_rate / 1000000, |
919 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
8a5c21dc | 920 | type & ARCH_TIMER_TYPE_CP15 ? |
ee34f1e6 | 921 | (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" : |
22006994 | 922 | "", |
8a5c21dc FW |
923 | type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "", |
924 | type & ARCH_TIMER_TYPE_MEM ? | |
22006994 SB |
925 | arch_timer_mem_use_virtual ? "virt" : "phys" : |
926 | ""); | |
8a4da6e3 MR |
927 | } |
928 | ||
929 | u32 arch_timer_get_rate(void) | |
930 | { | |
931 | return arch_timer_rate; | |
932 | } | |
933 | ||
ec5c8e42 JT |
934 | bool arch_timer_evtstrm_available(void) |
935 | { | |
936 | /* | |
937 | * We might get called from a preemptible context. This is fine | |
938 | * because availability of the event stream should be always the same | |
939 | * for a preemptible context and context where we might resume a task. | |
940 | */ | |
941 | return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available); | |
942 | } | |
943 | ||
22006994 | 944 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 945 | { |
22006994 SB |
946 | u32 vct_lo, vct_hi, tmp_hi; |
947 | ||
948 | do { | |
949 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
950 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
951 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
952 | } while (vct_hi != tmp_hi); | |
953 | ||
954 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
955 | } |
956 | ||
b4d6ce97 JG |
957 | static struct arch_timer_kvm_info arch_timer_kvm_info; |
958 | ||
959 | struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) | |
960 | { | |
961 | return &arch_timer_kvm_info; | |
962 | } | |
8a4da6e3 | 963 | |
22006994 SB |
964 | static void __init arch_counter_register(unsigned type) |
965 | { | |
966 | u64 start_count; | |
967 | ||
968 | /* Register the CP15 based counter if we have one */ | |
8a5c21dc | 969 | if (type & ARCH_TIMER_TYPE_CP15) { |
0ea41539 MZ |
970 | u64 (*rd)(void); |
971 | ||
e6d68b00 | 972 | if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || |
0ea41539 MZ |
973 | arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) { |
974 | if (arch_timer_counter_has_wa()) | |
975 | rd = arch_counter_get_cntvct_stable; | |
976 | else | |
977 | rd = arch_counter_get_cntvct; | |
978 | } else { | |
979 | if (arch_timer_counter_has_wa()) | |
980 | rd = arch_counter_get_cntpct_stable; | |
981 | else | |
982 | rd = arch_counter_get_cntpct; | |
983 | } | |
f6dc1576 | 984 | |
0ea41539 | 985 | arch_timer_read_counter = rd; |
5e3c6a31 | 986 | clocksource_counter.vdso_clock_mode = vdso_default; |
423bd69e | 987 | } else { |
22006994 | 988 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
423bd69e NL |
989 | } |
990 | ||
d8ec7595 BN |
991 | if (!arch_counter_suspend_stop) |
992 | clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
22006994 SB |
993 | start_count = arch_timer_read_counter(); |
994 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
995 | cyclecounter.mult = clocksource_counter.mult; | |
996 | cyclecounter.shift = clocksource_counter.shift; | |
b4d6ce97 JG |
997 | timecounter_init(&arch_timer_kvm_info.timecounter, |
998 | &cyclecounter, start_count); | |
4a7d3e8a TR |
999 | |
1000 | /* 56 bits minimum, so we assume worst case rollover */ | |
1001 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
1002 | } |
1003 | ||
8c37bb3a | 1004 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 | 1005 | { |
ded24019 | 1006 | pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id()); |
8a4da6e3 | 1007 | |
f81f03fa MZ |
1008 | disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]); |
1009 | if (arch_timer_has_nonsecure_ppi()) | |
ee34f1e6 | 1010 | disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]); |
8a4da6e3 | 1011 | |
46c5bfdd | 1012 | clk->set_state_shutdown(clk); |
8a4da6e3 MR |
1013 | } |
1014 | ||
7e86e8bd | 1015 | static int arch_timer_dying_cpu(unsigned int cpu) |
8a4da6e3 | 1016 | { |
7e86e8bd | 1017 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
8a4da6e3 | 1018 | |
ec5c8e42 JT |
1019 | cpumask_clear_cpu(smp_processor_id(), &evtstrm_available); |
1020 | ||
7e86e8bd RC |
1021 | arch_timer_stop(clk); |
1022 | return 0; | |
8a4da6e3 MR |
1023 | } |
1024 | ||
346e7480 | 1025 | #ifdef CONFIG_CPU_PM |
bee67c53 | 1026 | static DEFINE_PER_CPU(unsigned long, saved_cntkctl); |
346e7480 SH |
1027 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, |
1028 | unsigned long action, void *hcpu) | |
1029 | { | |
ec5c8e42 | 1030 | if (action == CPU_PM_ENTER) { |
bee67c53 | 1031 | __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl()); |
ec5c8e42 JT |
1032 | |
1033 | cpumask_clear_cpu(smp_processor_id(), &evtstrm_available); | |
1034 | } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) { | |
bee67c53 | 1035 | arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl)); |
ec5c8e42 | 1036 | |
5a354412 | 1037 | if (arch_timer_have_evtstrm_feature()) |
ec5c8e42 JT |
1038 | cpumask_set_cpu(smp_processor_id(), &evtstrm_available); |
1039 | } | |
346e7480 SH |
1040 | return NOTIFY_OK; |
1041 | } | |
1042 | ||
1043 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
1044 | .notifier_call = arch_timer_cpu_pm_notify, | |
1045 | }; | |
1046 | ||
1047 | static int __init arch_timer_cpu_pm_init(void) | |
1048 | { | |
1049 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
1050 | } | |
7e86e8bd RC |
1051 | |
1052 | static void __init arch_timer_cpu_pm_deinit(void) | |
1053 | { | |
1054 | WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier)); | |
1055 | } | |
1056 | ||
346e7480 SH |
1057 | #else |
1058 | static int __init arch_timer_cpu_pm_init(void) | |
1059 | { | |
1060 | return 0; | |
1061 | } | |
7e86e8bd RC |
1062 | |
1063 | static void __init arch_timer_cpu_pm_deinit(void) | |
1064 | { | |
1065 | } | |
346e7480 SH |
1066 | #endif |
1067 | ||
8a4da6e3 MR |
1068 | static int __init arch_timer_register(void) |
1069 | { | |
1070 | int err; | |
1071 | int ppi; | |
1072 | ||
8a4da6e3 MR |
1073 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
1074 | if (!arch_timer_evt) { | |
1075 | err = -ENOMEM; | |
1076 | goto out; | |
1077 | } | |
1078 | ||
f81f03fa MZ |
1079 | ppi = arch_timer_ppi[arch_timer_uses_ppi]; |
1080 | switch (arch_timer_uses_ppi) { | |
ee34f1e6 | 1081 | case ARCH_TIMER_VIRT_PPI: |
8a4da6e3 MR |
1082 | err = request_percpu_irq(ppi, arch_timer_handler_virt, |
1083 | "arch_timer", arch_timer_evt); | |
f81f03fa | 1084 | break; |
ee34f1e6 FW |
1085 | case ARCH_TIMER_PHYS_SECURE_PPI: |
1086 | case ARCH_TIMER_PHYS_NONSECURE_PPI: | |
8a4da6e3 MR |
1087 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
1088 | "arch_timer", arch_timer_evt); | |
4502b6bb | 1089 | if (!err && arch_timer_has_nonsecure_ppi()) { |
ee34f1e6 | 1090 | ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]; |
8a4da6e3 MR |
1091 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
1092 | "arch_timer", arch_timer_evt); | |
1093 | if (err) | |
ee34f1e6 | 1094 | free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI], |
8a4da6e3 MR |
1095 | arch_timer_evt); |
1096 | } | |
f81f03fa | 1097 | break; |
ee34f1e6 | 1098 | case ARCH_TIMER_HYP_PPI: |
f81f03fa MZ |
1099 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
1100 | "arch_timer", arch_timer_evt); | |
1101 | break; | |
1102 | default: | |
1103 | BUG(); | |
8a4da6e3 MR |
1104 | } |
1105 | ||
1106 | if (err) { | |
ded24019 | 1107 | pr_err("can't register interrupt %d (%d)\n", ppi, err); |
8a4da6e3 MR |
1108 | goto out_free; |
1109 | } | |
1110 | ||
346e7480 SH |
1111 | err = arch_timer_cpu_pm_init(); |
1112 | if (err) | |
1113 | goto out_unreg_notify; | |
1114 | ||
7e86e8bd RC |
1115 | /* Register and immediately configure the timer on the boot CPU */ |
1116 | err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, | |
73c1b41e | 1117 | "clockevents/arm/arch_timer:starting", |
7e86e8bd RC |
1118 | arch_timer_starting_cpu, arch_timer_dying_cpu); |
1119 | if (err) | |
1120 | goto out_unreg_cpupm; | |
8a4da6e3 MR |
1121 | return 0; |
1122 | ||
7e86e8bd RC |
1123 | out_unreg_cpupm: |
1124 | arch_timer_cpu_pm_deinit(); | |
1125 | ||
346e7480 | 1126 | out_unreg_notify: |
f81f03fa MZ |
1127 | free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt); |
1128 | if (arch_timer_has_nonsecure_ppi()) | |
ee34f1e6 | 1129 | free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI], |
8a4da6e3 | 1130 | arch_timer_evt); |
8a4da6e3 MR |
1131 | |
1132 | out_free: | |
1133 | free_percpu(arch_timer_evt); | |
1134 | out: | |
1135 | return err; | |
1136 | } | |
1137 | ||
22006994 SB |
1138 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
1139 | { | |
1140 | int ret; | |
1141 | irq_handler_t func; | |
1142 | struct arch_timer *t; | |
1143 | ||
1144 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
1145 | if (!t) | |
1146 | return -ENOMEM; | |
1147 | ||
1148 | t->base = base; | |
1149 | t->evt.irq = irq; | |
8a5c21dc | 1150 | __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt); |
22006994 SB |
1151 | |
1152 | if (arch_timer_mem_use_virtual) | |
1153 | func = arch_timer_handler_virt_mem; | |
1154 | else | |
1155 | func = arch_timer_handler_phys_mem; | |
1156 | ||
1157 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
1158 | if (ret) { | |
ded24019 | 1159 | pr_err("Failed to request mem timer irq\n"); |
22006994 SB |
1160 | kfree(t); |
1161 | } | |
1162 | ||
1163 | return ret; | |
1164 | } | |
1165 | ||
1166 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
1167 | { .compatible = "arm,armv7-timer", }, | |
1168 | { .compatible = "arm,armv8-timer", }, | |
1169 | {}, | |
1170 | }; | |
1171 | ||
1172 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
1173 | { .compatible = "arm,armv7-timer-mem", }, | |
1174 | {}, | |
1175 | }; | |
1176 | ||
13bf6992 | 1177 | static bool __init arch_timer_needs_of_probing(void) |
c387f07e SH |
1178 | { |
1179 | struct device_node *dn; | |
566e6dfa | 1180 | bool needs_probing = false; |
13bf6992 | 1181 | unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM; |
c387f07e | 1182 | |
13bf6992 FW |
1183 | /* We have two timers, and both device-tree nodes are probed. */ |
1184 | if ((arch_timers_present & mask) == mask) | |
1185 | return false; | |
1186 | ||
1187 | /* | |
1188 | * Only one type of timer is probed, | |
1189 | * check if we have another type of timer node in device-tree. | |
1190 | */ | |
1191 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) | |
1192 | dn = of_find_matching_node(NULL, arch_timer_mem_of_match); | |
1193 | else | |
1194 | dn = of_find_matching_node(NULL, arch_timer_of_match); | |
1195 | ||
1196 | if (dn && of_device_is_available(dn)) | |
566e6dfa | 1197 | needs_probing = true; |
13bf6992 | 1198 | |
c387f07e SH |
1199 | of_node_put(dn); |
1200 | ||
566e6dfa | 1201 | return needs_probing; |
c387f07e SH |
1202 | } |
1203 | ||
3c0731db | 1204 | static int __init arch_timer_common_init(void) |
22006994 | 1205 | { |
22006994 SB |
1206 | arch_timer_banner(arch_timers_present); |
1207 | arch_counter_register(arch_timers_present); | |
3c0731db | 1208 | return arch_timer_arch_init(); |
22006994 SB |
1209 | } |
1210 | ||
4502b6bb FW |
1211 | /** |
1212 | * arch_timer_select_ppi() - Select suitable PPI for the current system. | |
1213 | * | |
1214 | * If HYP mode is available, we know that the physical timer | |
1215 | * has been configured to be accessible from PL1. Use it, so | |
1216 | * that a guest can use the virtual timer instead. | |
1217 | * | |
1218 | * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE | |
1219 | * accesses to CNTP_*_EL1 registers are silently redirected to | |
1220 | * their CNTHP_*_EL2 counterparts, and use a different PPI | |
1221 | * number. | |
1222 | * | |
1223 | * If no interrupt provided for virtual timer, we'll have to | |
1224 | * stick to the physical timer. It'd better be accessible... | |
1225 | * For arm64 we never use the secure interrupt. | |
1226 | * | |
1227 | * Return: a suitable PPI type for the current system. | |
1228 | */ | |
1229 | static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void) | |
8a4da6e3 | 1230 | { |
4502b6bb FW |
1231 | if (is_kernel_in_hyp_mode()) |
1232 | return ARCH_TIMER_HYP_PPI; | |
f81f03fa | 1233 | |
4502b6bb FW |
1234 | if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) |
1235 | return ARCH_TIMER_VIRT_PPI; | |
8a4da6e3 | 1236 | |
4502b6bb FW |
1237 | if (IS_ENABLED(CONFIG_ARM64)) |
1238 | return ARCH_TIMER_PHYS_NONSECURE_PPI; | |
1239 | ||
1240 | return ARCH_TIMER_PHYS_SECURE_PPI; | |
1241 | } | |
1242 | ||
ee793049 AP |
1243 | static void __init arch_timer_populate_kvm_info(void) |
1244 | { | |
1245 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI]; | |
1246 | if (is_kernel_in_hyp_mode()) | |
1247 | arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]; | |
1248 | } | |
1249 | ||
3c0731db | 1250 | static int __init arch_timer_of_init(struct device_node *np) |
b09ca1ec | 1251 | { |
ca0e1b52 | 1252 | int i, ret; |
5d3dfa96 | 1253 | u32 rate; |
b09ca1ec | 1254 | |
8a5c21dc | 1255 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { |
ded24019 | 1256 | pr_warn("multiple nodes in dt, skipping\n"); |
3c0731db | 1257 | return 0; |
b09ca1ec HG |
1258 | } |
1259 | ||
8a5c21dc | 1260 | arch_timers_present |= ARCH_TIMER_TYPE_CP15; |
ee34f1e6 | 1261 | for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) |
b09ca1ec HG |
1262 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); |
1263 | ||
ee793049 | 1264 | arch_timer_populate_kvm_info(); |
ca0e1b52 | 1265 | |
c389d701 | 1266 | rate = arch_timer_get_cntfrq(); |
5d3dfa96 | 1267 | arch_timer_of_configure_rate(rate, np); |
b09ca1ec HG |
1268 | |
1269 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); | |
1270 | ||
651bb2e9 MZ |
1271 | /* Check for globally applicable workarounds */ |
1272 | arch_timer_check_ool_workaround(ate_match_dt, np); | |
f6dc1576 | 1273 | |
b09ca1ec HG |
1274 | /* |
1275 | * If we cannot rely on firmware initializing the timer registers then | |
1276 | * we should use the physical timers instead. | |
1277 | */ | |
1278 | if (IS_ENABLED(CONFIG_ARM) && | |
1279 | of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) | |
ee34f1e6 | 1280 | arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; |
4502b6bb FW |
1281 | else |
1282 | arch_timer_uses_ppi = arch_timer_select_ppi(); | |
1283 | ||
1284 | if (!arch_timer_ppi[arch_timer_uses_ppi]) { | |
1285 | pr_err("No interrupt available, giving up\n"); | |
1286 | return -EINVAL; | |
1287 | } | |
b09ca1ec | 1288 | |
d8ec7595 BN |
1289 | /* On some systems, the counter stops ticking when in suspend. */ |
1290 | arch_counter_suspend_stop = of_property_read_bool(np, | |
1291 | "arm,no-tick-in-suspend"); | |
1292 | ||
ca0e1b52 FW |
1293 | ret = arch_timer_register(); |
1294 | if (ret) | |
1295 | return ret; | |
1296 | ||
1297 | if (arch_timer_needs_of_probing()) | |
1298 | return 0; | |
1299 | ||
1300 | return arch_timer_common_init(); | |
b09ca1ec | 1301 | } |
17273395 DL |
1302 | TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); |
1303 | TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); | |
22006994 | 1304 | |
c389d701 FW |
1305 | static u32 __init |
1306 | arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame) | |
22006994 | 1307 | { |
c389d701 FW |
1308 | void __iomem *base; |
1309 | u32 rate; | |
22006994 | 1310 | |
c389d701 FW |
1311 | base = ioremap(frame->cntbase, frame->size); |
1312 | if (!base) { | |
1313 | pr_err("Unable to map frame @ %pa\n", &frame->cntbase); | |
1314 | return 0; | |
1315 | } | |
1316 | ||
3db1200c | 1317 | rate = readl_relaxed(base + CNTFRQ); |
c389d701 | 1318 | |
3db1200c | 1319 | iounmap(base); |
c389d701 FW |
1320 | |
1321 | return rate; | |
1322 | } | |
1323 | ||
1324 | static struct arch_timer_mem_frame * __init | |
1325 | arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem) | |
1326 | { | |
1327 | struct arch_timer_mem_frame *frame, *best_frame = NULL; | |
1328 | void __iomem *cntctlbase; | |
1329 | u32 cnttidr; | |
1330 | int i; | |
1331 | ||
1332 | cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size); | |
22006994 | 1333 | if (!cntctlbase) { |
c389d701 FW |
1334 | pr_err("Can't map CNTCTLBase @ %pa\n", |
1335 | &timer_mem->cntctlbase); | |
1336 | return NULL; | |
22006994 SB |
1337 | } |
1338 | ||
1339 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
22006994 SB |
1340 | |
1341 | /* | |
1342 | * Try to find a virtual capable frame. Otherwise fall back to a | |
1343 | * physical capable frame. | |
1344 | */ | |
c389d701 FW |
1345 | for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) { |
1346 | u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | | |
1347 | CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; | |
22006994 | 1348 | |
c389d701 FW |
1349 | frame = &timer_mem->frame[i]; |
1350 | if (!frame->valid) | |
1351 | continue; | |
22006994 | 1352 | |
e392d603 | 1353 | /* Try enabling everything, and see what sticks */ |
c389d701 FW |
1354 | writel_relaxed(cntacr, cntctlbase + CNTACR(i)); |
1355 | cntacr = readl_relaxed(cntctlbase + CNTACR(i)); | |
e392d603 | 1356 | |
c389d701 | 1357 | if ((cnttidr & CNTTIDR_VIRT(i)) && |
e392d603 | 1358 | !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { |
22006994 SB |
1359 | best_frame = frame; |
1360 | arch_timer_mem_use_virtual = true; | |
1361 | break; | |
1362 | } | |
e392d603 RM |
1363 | |
1364 | if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) | |
1365 | continue; | |
1366 | ||
c389d701 | 1367 | best_frame = frame; |
22006994 SB |
1368 | } |
1369 | ||
c389d701 FW |
1370 | iounmap(cntctlbase); |
1371 | ||
f63d947c | 1372 | return best_frame; |
c389d701 FW |
1373 | } |
1374 | ||
1375 | static int __init | |
1376 | arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame) | |
1377 | { | |
1378 | void __iomem *base; | |
1379 | int ret, irq = 0; | |
22006994 SB |
1380 | |
1381 | if (arch_timer_mem_use_virtual) | |
c389d701 | 1382 | irq = frame->virt_irq; |
22006994 | 1383 | else |
c389d701 | 1384 | irq = frame->phys_irq; |
e392d603 | 1385 | |
22006994 | 1386 | if (!irq) { |
ded24019 | 1387 | pr_err("Frame missing %s irq.\n", |
cfb6d656 | 1388 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
c389d701 FW |
1389 | return -EINVAL; |
1390 | } | |
1391 | ||
1392 | if (!request_mem_region(frame->cntbase, frame->size, | |
1393 | "arch_mem_timer")) | |
1394 | return -EBUSY; | |
1395 | ||
1396 | base = ioremap(frame->cntbase, frame->size); | |
1397 | if (!base) { | |
1398 | pr_err("Can't map frame's registers\n"); | |
1399 | return -ENXIO; | |
22006994 SB |
1400 | } |
1401 | ||
3c0731db | 1402 | ret = arch_timer_mem_register(base, irq); |
c389d701 FW |
1403 | if (ret) { |
1404 | iounmap(base); | |
1405 | return ret; | |
1406 | } | |
1407 | ||
1408 | arch_counter_base = base; | |
1409 | arch_timers_present |= ARCH_TIMER_TYPE_MEM; | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | static int __init arch_timer_mem_of_init(struct device_node *np) | |
1415 | { | |
1416 | struct arch_timer_mem *timer_mem; | |
1417 | struct arch_timer_mem_frame *frame; | |
1418 | struct device_node *frame_node; | |
1419 | struct resource res; | |
1420 | int ret = -EINVAL; | |
1421 | u32 rate; | |
1422 | ||
1423 | timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL); | |
1424 | if (!timer_mem) | |
1425 | return -ENOMEM; | |
1426 | ||
1427 | if (of_address_to_resource(np, 0, &res)) | |
3c0731db | 1428 | goto out; |
c389d701 FW |
1429 | timer_mem->cntctlbase = res.start; |
1430 | timer_mem->size = resource_size(&res); | |
3c0731db | 1431 | |
c389d701 FW |
1432 | for_each_available_child_of_node(np, frame_node) { |
1433 | u32 n; | |
1434 | struct arch_timer_mem_frame *frame; | |
1435 | ||
1436 | if (of_property_read_u32(frame_node, "frame-number", &n)) { | |
1437 | pr_err(FW_BUG "Missing frame-number.\n"); | |
1438 | of_node_put(frame_node); | |
1439 | goto out; | |
1440 | } | |
1441 | if (n >= ARCH_TIMER_MEM_MAX_FRAMES) { | |
1442 | pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n", | |
1443 | ARCH_TIMER_MEM_MAX_FRAMES - 1); | |
1444 | of_node_put(frame_node); | |
1445 | goto out; | |
1446 | } | |
1447 | frame = &timer_mem->frame[n]; | |
1448 | ||
1449 | if (frame->valid) { | |
1450 | pr_err(FW_BUG "Duplicated frame-number.\n"); | |
1451 | of_node_put(frame_node); | |
1452 | goto out; | |
1453 | } | |
1454 | ||
1455 | if (of_address_to_resource(frame_node, 0, &res)) { | |
1456 | of_node_put(frame_node); | |
1457 | goto out; | |
1458 | } | |
1459 | frame->cntbase = res.start; | |
1460 | frame->size = resource_size(&res); | |
1461 | ||
1462 | frame->virt_irq = irq_of_parse_and_map(frame_node, | |
1463 | ARCH_TIMER_VIRT_SPI); | |
1464 | frame->phys_irq = irq_of_parse_and_map(frame_node, | |
1465 | ARCH_TIMER_PHYS_SPI); | |
1466 | ||
1467 | frame->valid = true; | |
1468 | } | |
1469 | ||
1470 | frame = arch_timer_mem_find_best_frame(timer_mem); | |
1471 | if (!frame) { | |
21492e13 AB |
1472 | pr_err("Unable to find a suitable frame in timer @ %pa\n", |
1473 | &timer_mem->cntctlbase); | |
c389d701 FW |
1474 | ret = -EINVAL; |
1475 | goto out; | |
1476 | } | |
1477 | ||
1478 | rate = arch_timer_mem_frame_get_cntfrq(frame); | |
1479 | arch_timer_of_configure_rate(rate, np); | |
1480 | ||
1481 | ret = arch_timer_mem_frame_register(frame); | |
1482 | if (!ret && !arch_timer_needs_of_probing()) | |
ca0e1b52 | 1483 | ret = arch_timer_common_init(); |
e392d603 | 1484 | out: |
c389d701 | 1485 | kfree(timer_mem); |
3c0731db | 1486 | return ret; |
22006994 | 1487 | } |
17273395 | 1488 | TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", |
c389d701 | 1489 | arch_timer_mem_of_init); |
b09ca1ec | 1490 | |
f79d2094 | 1491 | #ifdef CONFIG_ACPI_GTDT |
c2743a36 FW |
1492 | static int __init |
1493 | arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem) | |
1494 | { | |
1495 | struct arch_timer_mem_frame *frame; | |
1496 | u32 rate; | |
1497 | int i; | |
1498 | ||
1499 | for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) { | |
1500 | frame = &timer_mem->frame[i]; | |
1501 | ||
1502 | if (!frame->valid) | |
1503 | continue; | |
1504 | ||
1505 | rate = arch_timer_mem_frame_get_cntfrq(frame); | |
1506 | if (rate == arch_timer_rate) | |
1507 | continue; | |
1508 | ||
1509 | pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n", | |
1510 | &frame->cntbase, | |
1511 | (unsigned long)rate, (unsigned long)arch_timer_rate); | |
1512 | ||
1513 | return -EINVAL; | |
1514 | } | |
1515 | ||
1516 | return 0; | |
1517 | } | |
1518 | ||
1519 | static int __init arch_timer_mem_acpi_init(int platform_timer_count) | |
1520 | { | |
1521 | struct arch_timer_mem *timers, *timer; | |
21492e13 | 1522 | struct arch_timer_mem_frame *frame, *best_frame = NULL; |
c2743a36 FW |
1523 | int timer_count, i, ret = 0; |
1524 | ||
1525 | timers = kcalloc(platform_timer_count, sizeof(*timers), | |
1526 | GFP_KERNEL); | |
1527 | if (!timers) | |
1528 | return -ENOMEM; | |
1529 | ||
1530 | ret = acpi_arch_timer_mem_init(timers, &timer_count); | |
1531 | if (ret || !timer_count) | |
1532 | goto out; | |
1533 | ||
c2743a36 FW |
1534 | /* |
1535 | * While unlikely, it's theoretically possible that none of the frames | |
1536 | * in a timer expose the combination of feature we want. | |
1537 | */ | |
d197f798 | 1538 | for (i = 0; i < timer_count; i++) { |
c2743a36 FW |
1539 | timer = &timers[i]; |
1540 | ||
1541 | frame = arch_timer_mem_find_best_frame(timer); | |
21492e13 AB |
1542 | if (!best_frame) |
1543 | best_frame = frame; | |
1544 | ||
1545 | ret = arch_timer_mem_verify_cntfrq(timer); | |
1546 | if (ret) { | |
1547 | pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n"); | |
1548 | goto out; | |
1549 | } | |
1550 | ||
1551 | if (!best_frame) /* implies !frame */ | |
1552 | /* | |
1553 | * Only complain about missing suitable frames if we | |
1554 | * haven't already found one in a previous iteration. | |
1555 | */ | |
1556 | pr_err("Unable to find a suitable frame in timer @ %pa\n", | |
1557 | &timer->cntctlbase); | |
c2743a36 FW |
1558 | } |
1559 | ||
21492e13 AB |
1560 | if (best_frame) |
1561 | ret = arch_timer_mem_frame_register(best_frame); | |
c2743a36 FW |
1562 | out: |
1563 | kfree(timers); | |
1564 | return ret; | |
1565 | } | |
1566 | ||
1567 | /* Initialize per-processor generic timer and memory-mapped timer(if present) */ | |
b09ca1ec HG |
1568 | static int __init arch_timer_acpi_init(struct acpi_table_header *table) |
1569 | { | |
c2743a36 | 1570 | int ret, platform_timer_count; |
b09ca1ec | 1571 | |
8a5c21dc | 1572 | if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { |
ded24019 | 1573 | pr_warn("already initialized, skipping\n"); |
b09ca1ec HG |
1574 | return -EINVAL; |
1575 | } | |
1576 | ||
8a5c21dc | 1577 | arch_timers_present |= ARCH_TIMER_TYPE_CP15; |
b09ca1ec | 1578 | |
c2743a36 | 1579 | ret = acpi_gtdt_init(table, &platform_timer_count); |
d1b5e552 | 1580 | if (ret) |
f79d2094 | 1581 | return ret; |
b09ca1ec | 1582 | |
ee34f1e6 | 1583 | arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] = |
f79d2094 | 1584 | acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI); |
b09ca1ec | 1585 | |
ee34f1e6 | 1586 | arch_timer_ppi[ARCH_TIMER_VIRT_PPI] = |
f79d2094 | 1587 | acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI); |
b09ca1ec | 1588 | |
ee34f1e6 | 1589 | arch_timer_ppi[ARCH_TIMER_HYP_PPI] = |
f79d2094 | 1590 | acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI); |
b09ca1ec | 1591 | |
ee793049 | 1592 | arch_timer_populate_kvm_info(); |
ca0e1b52 | 1593 | |
5d3dfa96 FW |
1594 | /* |
1595 | * When probing via ACPI, we have no mechanism to override the sysreg | |
1596 | * CNTFRQ value. This *must* be correct. | |
1597 | */ | |
1598 | arch_timer_rate = arch_timer_get_cntfrq(); | |
1599 | if (!arch_timer_rate) { | |
1600 | pr_err(FW_BUG "frequency not available.\n"); | |
1601 | return -EINVAL; | |
1602 | } | |
b09ca1ec | 1603 | |
4502b6bb FW |
1604 | arch_timer_uses_ppi = arch_timer_select_ppi(); |
1605 | if (!arch_timer_ppi[arch_timer_uses_ppi]) { | |
1606 | pr_err("No interrupt available, giving up\n"); | |
1607 | return -EINVAL; | |
1608 | } | |
1609 | ||
b09ca1ec | 1610 | /* Always-on capability */ |
f79d2094 | 1611 | arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi); |
b09ca1ec | 1612 | |
5a38bcac MZ |
1613 | /* Check for globally applicable workarounds */ |
1614 | arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table); | |
1615 | ||
ca0e1b52 FW |
1616 | ret = arch_timer_register(); |
1617 | if (ret) | |
1618 | return ret; | |
1619 | ||
c2743a36 FW |
1620 | if (platform_timer_count && |
1621 | arch_timer_mem_acpi_init(platform_timer_count)) | |
1622 | pr_err("Failed to initialize memory-mapped timer.\n"); | |
1623 | ||
ca0e1b52 | 1624 | return arch_timer_common_init(); |
b09ca1ec | 1625 | } |
77d62f53 | 1626 | TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); |
b09ca1ec | 1627 | #endif |