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Commit | Line | Data |
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8a4da6e3 MR |
1 | /* |
2 | * linux/drivers/clocksource/arm_arch_timer.c | |
3 | * | |
4 | * Copyright (C) 2011 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
f005bd7e MZ |
11 | |
12 | #define pr_fmt(fmt) "arm_arch_timer: " fmt | |
13 | ||
8a4da6e3 MR |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/cpu.h> | |
346e7480 | 19 | #include <linux/cpu_pm.h> |
8a4da6e3 | 20 | #include <linux/clockchips.h> |
7c8f1e78 | 21 | #include <linux/clocksource.h> |
8a4da6e3 MR |
22 | #include <linux/interrupt.h> |
23 | #include <linux/of_irq.h> | |
22006994 | 24 | #include <linux/of_address.h> |
8a4da6e3 | 25 | #include <linux/io.h> |
22006994 | 26 | #include <linux/slab.h> |
e6017571 | 27 | #include <linux/sched/clock.h> |
65cd4f6c | 28 | #include <linux/sched_clock.h> |
b09ca1ec | 29 | #include <linux/acpi.h> |
8a4da6e3 MR |
30 | |
31 | #include <asm/arch_timer.h> | |
8266891e | 32 | #include <asm/virt.h> |
8a4da6e3 MR |
33 | |
34 | #include <clocksource/arm_arch_timer.h> | |
35 | ||
22006994 SB |
36 | #define CNTTIDR 0x08 |
37 | #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) | |
38 | ||
e392d603 RM |
39 | #define CNTACR(n) (0x40 + ((n) * 4)) |
40 | #define CNTACR_RPCT BIT(0) | |
41 | #define CNTACR_RVCT BIT(1) | |
42 | #define CNTACR_RFRQ BIT(2) | |
43 | #define CNTACR_RVOFF BIT(3) | |
44 | #define CNTACR_RWVT BIT(4) | |
45 | #define CNTACR_RWPT BIT(5) | |
46 | ||
22006994 SB |
47 | #define CNTVCT_LO 0x08 |
48 | #define CNTVCT_HI 0x0c | |
49 | #define CNTFRQ 0x10 | |
50 | #define CNTP_TVAL 0x28 | |
51 | #define CNTP_CTL 0x2c | |
52 | #define CNTV_TVAL 0x38 | |
53 | #define CNTV_CTL 0x3c | |
54 | ||
55 | #define ARCH_CP15_TIMER BIT(0) | |
56 | #define ARCH_MEM_TIMER BIT(1) | |
57 | static unsigned arch_timers_present __initdata; | |
58 | ||
59 | static void __iomem *arch_counter_base; | |
60 | ||
61 | struct arch_timer { | |
62 | void __iomem *base; | |
63 | struct clock_event_device evt; | |
64 | }; | |
65 | ||
66 | #define to_arch_timer(e) container_of(e, struct arch_timer, evt) | |
67 | ||
8a4da6e3 MR |
68 | static u32 arch_timer_rate; |
69 | ||
70 | enum ppi_nr { | |
71 | PHYS_SECURE_PPI, | |
72 | PHYS_NONSECURE_PPI, | |
73 | VIRT_PPI, | |
74 | HYP_PPI, | |
75 | MAX_TIMER_PPI | |
76 | }; | |
77 | ||
78 | static int arch_timer_ppi[MAX_TIMER_PPI]; | |
79 | ||
80 | static struct clock_event_device __percpu *arch_timer_evt; | |
81 | ||
f81f03fa | 82 | static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI; |
82a56194 | 83 | static bool arch_timer_c3stop; |
22006994 | 84 | static bool arch_timer_mem_use_virtual; |
d8ec7595 | 85 | static bool arch_counter_suspend_stop; |
8a4da6e3 | 86 | |
46fd5c6b WD |
87 | static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); |
88 | ||
89 | static int __init early_evtstrm_cfg(char *buf) | |
90 | { | |
91 | return strtobool(buf, &evtstrm_enable); | |
92 | } | |
93 | early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg); | |
94 | ||
8a4da6e3 MR |
95 | /* |
96 | * Architected system timer support. | |
97 | */ | |
98 | ||
f6dc1576 | 99 | #ifdef CONFIG_FSL_ERRATUM_A008585 |
16d10ef2 DT |
100 | /* |
101 | * The number of retries is an arbitrary value well beyond the highest number | |
102 | * of iterations the loop has been observed to take. | |
103 | */ | |
104 | #define __fsl_a008585_read_reg(reg) ({ \ | |
105 | u64 _old, _new; \ | |
106 | int _retries = 200; \ | |
107 | \ | |
108 | do { \ | |
109 | _old = read_sysreg(reg); \ | |
110 | _new = read_sysreg(reg); \ | |
111 | _retries--; \ | |
112 | } while (unlikely(_old != _new) && _retries); \ | |
113 | \ | |
114 | WARN_ON_ONCE(!_retries); \ | |
115 | _new; \ | |
116 | }) | |
117 | ||
118 | static u32 notrace fsl_a008585_read_cntp_tval_el0(void) | |
f6dc1576 SW |
119 | { |
120 | return __fsl_a008585_read_reg(cntp_tval_el0); | |
121 | } | |
122 | ||
16d10ef2 | 123 | static u32 notrace fsl_a008585_read_cntv_tval_el0(void) |
f6dc1576 SW |
124 | { |
125 | return __fsl_a008585_read_reg(cntv_tval_el0); | |
126 | } | |
127 | ||
16d10ef2 | 128 | static u64 notrace fsl_a008585_read_cntvct_el0(void) |
f6dc1576 SW |
129 | { |
130 | return __fsl_a008585_read_reg(cntvct_el0); | |
131 | } | |
16d10ef2 DT |
132 | #endif |
133 | ||
bb42ca47 DT |
134 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
135 | /* | |
136 | * Verify whether the value of the second read is larger than the first by | |
137 | * less than 32 is the only way to confirm the value is correct, so clear the | |
138 | * lower 5 bits to check whether the difference is greater than 32 or not. | |
139 | * Theoretically the erratum should not occur more than twice in succession | |
140 | * when reading the system counter, but it is possible that some interrupts | |
141 | * may lead to more than twice read errors, triggering the warning, so setting | |
142 | * the number of retries far beyond the number of iterations the loop has been | |
143 | * observed to take. | |
144 | */ | |
145 | #define __hisi_161010101_read_reg(reg) ({ \ | |
146 | u64 _old, _new; \ | |
147 | int _retries = 50; \ | |
148 | \ | |
149 | do { \ | |
150 | _old = read_sysreg(reg); \ | |
151 | _new = read_sysreg(reg); \ | |
152 | _retries--; \ | |
153 | } while (unlikely((_new - _old) >> 5) && _retries); \ | |
154 | \ | |
155 | WARN_ON_ONCE(!_retries); \ | |
156 | _new; \ | |
157 | }) | |
158 | ||
159 | static u32 notrace hisi_161010101_read_cntp_tval_el0(void) | |
160 | { | |
161 | return __hisi_161010101_read_reg(cntp_tval_el0); | |
162 | } | |
163 | ||
164 | static u32 notrace hisi_161010101_read_cntv_tval_el0(void) | |
165 | { | |
166 | return __hisi_161010101_read_reg(cntv_tval_el0); | |
167 | } | |
168 | ||
169 | static u64 notrace hisi_161010101_read_cntvct_el0(void) | |
170 | { | |
171 | return __hisi_161010101_read_reg(cntvct_el0); | |
172 | } | |
173 | #endif | |
174 | ||
16d10ef2 DT |
175 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
176 | const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL; | |
177 | EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); | |
178 | ||
179 | DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled); | |
180 | EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled); | |
181 | ||
182 | static const struct arch_timer_erratum_workaround ool_workarounds[] = { | |
183 | #ifdef CONFIG_FSL_ERRATUM_A008585 | |
184 | { | |
185 | .id = "fsl,erratum-a008585", | |
186 | .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0, | |
187 | .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0, | |
188 | .read_cntvct_el0 = fsl_a008585_read_cntvct_el0, | |
189 | }, | |
190 | #endif | |
bb42ca47 DT |
191 | #ifdef CONFIG_HISILICON_ERRATUM_161010101 |
192 | { | |
193 | .id = "hisilicon,erratum-161010101", | |
194 | .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0, | |
195 | .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0, | |
196 | .read_cntvct_el0 = hisi_161010101_read_cntvct_el0, | |
197 | }, | |
198 | #endif | |
16d10ef2 DT |
199 | }; |
200 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ | |
f6dc1576 | 201 | |
60faddf6 SB |
202 | static __always_inline |
203 | void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, | |
cfb6d656 | 204 | struct clock_event_device *clk) |
60faddf6 | 205 | { |
22006994 SB |
206 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { |
207 | struct arch_timer *timer = to_arch_timer(clk); | |
208 | switch (reg) { | |
209 | case ARCH_TIMER_REG_CTRL: | |
210 | writel_relaxed(val, timer->base + CNTP_CTL); | |
211 | break; | |
212 | case ARCH_TIMER_REG_TVAL: | |
213 | writel_relaxed(val, timer->base + CNTP_TVAL); | |
214 | break; | |
215 | } | |
216 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
217 | struct arch_timer *timer = to_arch_timer(clk); | |
218 | switch (reg) { | |
219 | case ARCH_TIMER_REG_CTRL: | |
220 | writel_relaxed(val, timer->base + CNTV_CTL); | |
221 | break; | |
222 | case ARCH_TIMER_REG_TVAL: | |
223 | writel_relaxed(val, timer->base + CNTV_TVAL); | |
224 | break; | |
225 | } | |
226 | } else { | |
227 | arch_timer_reg_write_cp15(access, reg, val); | |
228 | } | |
60faddf6 SB |
229 | } |
230 | ||
231 | static __always_inline | |
232 | u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, | |
cfb6d656 | 233 | struct clock_event_device *clk) |
60faddf6 | 234 | { |
22006994 SB |
235 | u32 val; |
236 | ||
237 | if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { | |
238 | struct arch_timer *timer = to_arch_timer(clk); | |
239 | switch (reg) { | |
240 | case ARCH_TIMER_REG_CTRL: | |
241 | val = readl_relaxed(timer->base + CNTP_CTL); | |
242 | break; | |
243 | case ARCH_TIMER_REG_TVAL: | |
244 | val = readl_relaxed(timer->base + CNTP_TVAL); | |
245 | break; | |
246 | } | |
247 | } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { | |
248 | struct arch_timer *timer = to_arch_timer(clk); | |
249 | switch (reg) { | |
250 | case ARCH_TIMER_REG_CTRL: | |
251 | val = readl_relaxed(timer->base + CNTV_CTL); | |
252 | break; | |
253 | case ARCH_TIMER_REG_TVAL: | |
254 | val = readl_relaxed(timer->base + CNTV_TVAL); | |
255 | break; | |
256 | } | |
257 | } else { | |
258 | val = arch_timer_reg_read_cp15(access, reg); | |
259 | } | |
260 | ||
261 | return val; | |
60faddf6 SB |
262 | } |
263 | ||
e09f3cc0 | 264 | static __always_inline irqreturn_t timer_handler(const int access, |
8a4da6e3 MR |
265 | struct clock_event_device *evt) |
266 | { | |
267 | unsigned long ctrl; | |
cfb6d656 | 268 | |
60faddf6 | 269 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); |
8a4da6e3 MR |
270 | if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { |
271 | ctrl |= ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 | 272 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); |
8a4da6e3 MR |
273 | evt->event_handler(evt); |
274 | return IRQ_HANDLED; | |
275 | } | |
276 | ||
277 | return IRQ_NONE; | |
278 | } | |
279 | ||
280 | static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id) | |
281 | { | |
282 | struct clock_event_device *evt = dev_id; | |
283 | ||
284 | return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt); | |
285 | } | |
286 | ||
287 | static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id) | |
288 | { | |
289 | struct clock_event_device *evt = dev_id; | |
290 | ||
291 | return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); | |
292 | } | |
293 | ||
22006994 SB |
294 | static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) |
295 | { | |
296 | struct clock_event_device *evt = dev_id; | |
297 | ||
298 | return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); | |
299 | } | |
300 | ||
301 | static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) | |
302 | { | |
303 | struct clock_event_device *evt = dev_id; | |
304 | ||
305 | return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); | |
306 | } | |
307 | ||
46c5bfdd VK |
308 | static __always_inline int timer_shutdown(const int access, |
309 | struct clock_event_device *clk) | |
8a4da6e3 MR |
310 | { |
311 | unsigned long ctrl; | |
46c5bfdd VK |
312 | |
313 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
314 | ctrl &= ~ARCH_TIMER_CTRL_ENABLE; | |
315 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
316 | ||
317 | return 0; | |
8a4da6e3 MR |
318 | } |
319 | ||
46c5bfdd | 320 | static int arch_timer_shutdown_virt(struct clock_event_device *clk) |
8a4da6e3 | 321 | { |
46c5bfdd | 322 | return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk); |
8a4da6e3 MR |
323 | } |
324 | ||
46c5bfdd | 325 | static int arch_timer_shutdown_phys(struct clock_event_device *clk) |
8a4da6e3 | 326 | { |
46c5bfdd | 327 | return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); |
8a4da6e3 MR |
328 | } |
329 | ||
46c5bfdd | 330 | static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) |
22006994 | 331 | { |
46c5bfdd | 332 | return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); |
8a4da6e3 MR |
333 | } |
334 | ||
46c5bfdd | 335 | static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) |
22006994 | 336 | { |
46c5bfdd | 337 | return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); |
22006994 SB |
338 | } |
339 | ||
60faddf6 | 340 | static __always_inline void set_next_event(const int access, unsigned long evt, |
cfb6d656 | 341 | struct clock_event_device *clk) |
8a4da6e3 MR |
342 | { |
343 | unsigned long ctrl; | |
60faddf6 | 344 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); |
8a4da6e3 MR |
345 | ctrl |= ARCH_TIMER_CTRL_ENABLE; |
346 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
60faddf6 SB |
347 | arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); |
348 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
8a4da6e3 MR |
349 | } |
350 | ||
16d10ef2 DT |
351 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
352 | static __always_inline void erratum_set_next_event_generic(const int access, | |
f6dc1576 SW |
353 | unsigned long evt, struct clock_event_device *clk) |
354 | { | |
355 | unsigned long ctrl; | |
356 | u64 cval = evt + arch_counter_get_cntvct(); | |
357 | ||
358 | ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); | |
359 | ctrl |= ARCH_TIMER_CTRL_ENABLE; | |
360 | ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; | |
361 | ||
362 | if (access == ARCH_TIMER_PHYS_ACCESS) | |
363 | write_sysreg(cval, cntp_cval_el0); | |
364 | else if (access == ARCH_TIMER_VIRT_ACCESS) | |
365 | write_sysreg(cval, cntv_cval_el0); | |
366 | ||
367 | arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); | |
368 | } | |
369 | ||
16d10ef2 | 370 | static int erratum_set_next_event_virt(unsigned long evt, |
f6dc1576 SW |
371 | struct clock_event_device *clk) |
372 | { | |
16d10ef2 | 373 | erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
f6dc1576 SW |
374 | return 0; |
375 | } | |
376 | ||
16d10ef2 | 377 | static int erratum_set_next_event_phys(unsigned long evt, |
f6dc1576 SW |
378 | struct clock_event_device *clk) |
379 | { | |
16d10ef2 | 380 | erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
f6dc1576 SW |
381 | return 0; |
382 | } | |
16d10ef2 | 383 | #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ |
f6dc1576 | 384 | |
8a4da6e3 | 385 | static int arch_timer_set_next_event_virt(unsigned long evt, |
60faddf6 | 386 | struct clock_event_device *clk) |
8a4da6e3 | 387 | { |
60faddf6 | 388 | set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk); |
8a4da6e3 MR |
389 | return 0; |
390 | } | |
391 | ||
392 | static int arch_timer_set_next_event_phys(unsigned long evt, | |
60faddf6 | 393 | struct clock_event_device *clk) |
8a4da6e3 | 394 | { |
60faddf6 | 395 | set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); |
8a4da6e3 MR |
396 | return 0; |
397 | } | |
398 | ||
22006994 SB |
399 | static int arch_timer_set_next_event_virt_mem(unsigned long evt, |
400 | struct clock_event_device *clk) | |
8a4da6e3 | 401 | { |
22006994 SB |
402 | set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); |
403 | return 0; | |
404 | } | |
405 | ||
406 | static int arch_timer_set_next_event_phys_mem(unsigned long evt, | |
407 | struct clock_event_device *clk) | |
408 | { | |
409 | set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); | |
410 | return 0; | |
411 | } | |
412 | ||
16d10ef2 | 413 | static void erratum_workaround_set_sne(struct clock_event_device *clk) |
f6dc1576 | 414 | { |
16d10ef2 | 415 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
f6dc1576 SW |
416 | if (!static_branch_unlikely(&arch_timer_read_ool_enabled)) |
417 | return; | |
418 | ||
419 | if (arch_timer_uses_ppi == VIRT_PPI) | |
16d10ef2 | 420 | clk->set_next_event = erratum_set_next_event_virt; |
f6dc1576 | 421 | else |
16d10ef2 | 422 | clk->set_next_event = erratum_set_next_event_phys; |
f6dc1576 SW |
423 | #endif |
424 | } | |
425 | ||
cfb6d656 TG |
426 | static void __arch_timer_setup(unsigned type, |
427 | struct clock_event_device *clk) | |
22006994 SB |
428 | { |
429 | clk->features = CLOCK_EVT_FEAT_ONESHOT; | |
430 | ||
431 | if (type == ARCH_CP15_TIMER) { | |
82a56194 LP |
432 | if (arch_timer_c3stop) |
433 | clk->features |= CLOCK_EVT_FEAT_C3STOP; | |
22006994 SB |
434 | clk->name = "arch_sys_timer"; |
435 | clk->rating = 450; | |
436 | clk->cpumask = cpumask_of(smp_processor_id()); | |
f81f03fa MZ |
437 | clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; |
438 | switch (arch_timer_uses_ppi) { | |
439 | case VIRT_PPI: | |
46c5bfdd | 440 | clk->set_state_shutdown = arch_timer_shutdown_virt; |
cf8c5009 | 441 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; |
22006994 | 442 | clk->set_next_event = arch_timer_set_next_event_virt; |
f81f03fa MZ |
443 | break; |
444 | case PHYS_SECURE_PPI: | |
445 | case PHYS_NONSECURE_PPI: | |
446 | case HYP_PPI: | |
46c5bfdd | 447 | clk->set_state_shutdown = arch_timer_shutdown_phys; |
cf8c5009 | 448 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; |
22006994 | 449 | clk->set_next_event = arch_timer_set_next_event_phys; |
f81f03fa MZ |
450 | break; |
451 | default: | |
452 | BUG(); | |
22006994 | 453 | } |
f6dc1576 | 454 | |
16d10ef2 | 455 | erratum_workaround_set_sne(clk); |
8a4da6e3 | 456 | } else { |
7b52ad2e | 457 | clk->features |= CLOCK_EVT_FEAT_DYNIRQ; |
22006994 SB |
458 | clk->name = "arch_mem_timer"; |
459 | clk->rating = 400; | |
460 | clk->cpumask = cpu_all_mask; | |
461 | if (arch_timer_mem_use_virtual) { | |
46c5bfdd | 462 | clk->set_state_shutdown = arch_timer_shutdown_virt_mem; |
cf8c5009 | 463 | clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; |
22006994 SB |
464 | clk->set_next_event = |
465 | arch_timer_set_next_event_virt_mem; | |
466 | } else { | |
46c5bfdd | 467 | clk->set_state_shutdown = arch_timer_shutdown_phys_mem; |
cf8c5009 | 468 | clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; |
22006994 SB |
469 | clk->set_next_event = |
470 | arch_timer_set_next_event_phys_mem; | |
471 | } | |
8a4da6e3 MR |
472 | } |
473 | ||
46c5bfdd | 474 | clk->set_state_shutdown(clk); |
8a4da6e3 | 475 | |
22006994 SB |
476 | clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff); |
477 | } | |
8a4da6e3 | 478 | |
e1ce5c7a NL |
479 | static void arch_timer_evtstrm_enable(int divider) |
480 | { | |
481 | u32 cntkctl = arch_timer_get_cntkctl(); | |
482 | ||
483 | cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; | |
484 | /* Set the divider and enable virtual event stream */ | |
485 | cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | |
486 | | ARCH_TIMER_VIRT_EVT_EN; | |
487 | arch_timer_set_cntkctl(cntkctl); | |
488 | elf_hwcap |= HWCAP_EVTSTRM; | |
489 | #ifdef CONFIG_COMPAT | |
490 | compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; | |
491 | #endif | |
492 | } | |
493 | ||
037f6377 WD |
494 | static void arch_timer_configure_evtstream(void) |
495 | { | |
496 | int evt_stream_div, pos; | |
497 | ||
498 | /* Find the closest power of two to the divisor */ | |
499 | evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; | |
500 | pos = fls(evt_stream_div); | |
501 | if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) | |
502 | pos--; | |
503 | /* enable event stream */ | |
504 | arch_timer_evtstrm_enable(min(pos, 15)); | |
505 | } | |
506 | ||
8b8dde00 NL |
507 | static void arch_counter_set_user_access(void) |
508 | { | |
509 | u32 cntkctl = arch_timer_get_cntkctl(); | |
510 | ||
511 | /* Disable user access to the timers and the physical counter */ | |
512 | /* Also disable virtual event stream */ | |
513 | cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | |
514 | | ARCH_TIMER_USR_VT_ACCESS_EN | |
515 | | ARCH_TIMER_VIRT_EVT_EN | |
516 | | ARCH_TIMER_USR_PCT_ACCESS_EN); | |
517 | ||
518 | /* Enable user access to the virtual counter */ | |
519 | cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; | |
520 | ||
521 | arch_timer_set_cntkctl(cntkctl); | |
522 | } | |
523 | ||
f81f03fa MZ |
524 | static bool arch_timer_has_nonsecure_ppi(void) |
525 | { | |
526 | return (arch_timer_uses_ppi == PHYS_SECURE_PPI && | |
527 | arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
528 | } | |
529 | ||
f005bd7e MZ |
530 | static u32 check_ppi_trigger(int irq) |
531 | { | |
532 | u32 flags = irq_get_trigger_type(irq); | |
533 | ||
534 | if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { | |
535 | pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); | |
536 | pr_warn("WARNING: Please fix your firmware\n"); | |
537 | flags = IRQF_TRIGGER_LOW; | |
538 | } | |
539 | ||
540 | return flags; | |
541 | } | |
542 | ||
7e86e8bd | 543 | static int arch_timer_starting_cpu(unsigned int cpu) |
22006994 | 544 | { |
7e86e8bd | 545 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
f005bd7e | 546 | u32 flags; |
7e86e8bd | 547 | |
22006994 | 548 | __arch_timer_setup(ARCH_CP15_TIMER, clk); |
8a4da6e3 | 549 | |
f005bd7e MZ |
550 | flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); |
551 | enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); | |
f81f03fa | 552 | |
f005bd7e MZ |
553 | if (arch_timer_has_nonsecure_ppi()) { |
554 | flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
555 | enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags); | |
556 | } | |
8a4da6e3 MR |
557 | |
558 | arch_counter_set_user_access(); | |
46fd5c6b | 559 | if (evtstrm_enable) |
037f6377 | 560 | arch_timer_configure_evtstream(); |
8a4da6e3 MR |
561 | |
562 | return 0; | |
563 | } | |
564 | ||
22006994 SB |
565 | static void |
566 | arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) | |
8a4da6e3 | 567 | { |
22006994 SB |
568 | /* Who has more than one independent system counter? */ |
569 | if (arch_timer_rate) | |
570 | return; | |
8a4da6e3 | 571 | |
b09ca1ec HG |
572 | /* |
573 | * Try to determine the frequency from the device tree or CNTFRQ, | |
574 | * if ACPI is enabled, get the frequency from CNTFRQ ONLY. | |
575 | */ | |
576 | if (!acpi_disabled || | |
577 | of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { | |
22006994 SB |
578 | if (cntbase) |
579 | arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); | |
580 | else | |
581 | arch_timer_rate = arch_timer_get_cntfrq(); | |
8a4da6e3 MR |
582 | } |
583 | ||
22006994 SB |
584 | /* Check the timer frequency. */ |
585 | if (arch_timer_rate == 0) | |
586 | pr_warn("Architected timer frequency not available\n"); | |
587 | } | |
588 | ||
589 | static void arch_timer_banner(unsigned type) | |
590 | { | |
591 | pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", | |
592 | type & ARCH_CP15_TIMER ? "cp15" : "", | |
593 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "", | |
594 | type & ARCH_MEM_TIMER ? "mmio" : "", | |
8a4da6e3 MR |
595 | (unsigned long)arch_timer_rate / 1000000, |
596 | (unsigned long)(arch_timer_rate / 10000) % 100, | |
22006994 | 597 | type & ARCH_CP15_TIMER ? |
f81f03fa | 598 | (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" : |
22006994 SB |
599 | "", |
600 | type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "", | |
601 | type & ARCH_MEM_TIMER ? | |
602 | arch_timer_mem_use_virtual ? "virt" : "phys" : | |
603 | ""); | |
8a4da6e3 MR |
604 | } |
605 | ||
606 | u32 arch_timer_get_rate(void) | |
607 | { | |
608 | return arch_timer_rate; | |
609 | } | |
610 | ||
22006994 | 611 | static u64 arch_counter_get_cntvct_mem(void) |
8a4da6e3 | 612 | { |
22006994 SB |
613 | u32 vct_lo, vct_hi, tmp_hi; |
614 | ||
615 | do { | |
616 | vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
617 | vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); | |
618 | tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); | |
619 | } while (vct_hi != tmp_hi); | |
620 | ||
621 | return ((u64) vct_hi << 32) | vct_lo; | |
8a4da6e3 MR |
622 | } |
623 | ||
22006994 SB |
624 | /* |
625 | * Default to cp15 based access because arm64 uses this function for | |
626 | * sched_clock() before DT is probed and the cp15 method is guaranteed | |
627 | * to exist on arm64. arm doesn't use this before DT is probed so even | |
628 | * if we don't have the cp15 accessors we won't have a problem. | |
629 | */ | |
630 | u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; | |
631 | ||
a5a1d1c2 | 632 | static u64 arch_counter_read(struct clocksource *cs) |
8a4da6e3 | 633 | { |
22006994 | 634 | return arch_timer_read_counter(); |
8a4da6e3 MR |
635 | } |
636 | ||
a5a1d1c2 | 637 | static u64 arch_counter_read_cc(const struct cyclecounter *cc) |
8a4da6e3 | 638 | { |
22006994 | 639 | return arch_timer_read_counter(); |
8a4da6e3 MR |
640 | } |
641 | ||
642 | static struct clocksource clocksource_counter = { | |
643 | .name = "arch_sys_counter", | |
644 | .rating = 400, | |
645 | .read = arch_counter_read, | |
646 | .mask = CLOCKSOURCE_MASK(56), | |
d8ec7595 | 647 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8a4da6e3 MR |
648 | }; |
649 | ||
3d837bc0 | 650 | static struct cyclecounter cyclecounter __ro_after_init = { |
8a4da6e3 MR |
651 | .read = arch_counter_read_cc, |
652 | .mask = CLOCKSOURCE_MASK(56), | |
653 | }; | |
654 | ||
b4d6ce97 JG |
655 | static struct arch_timer_kvm_info arch_timer_kvm_info; |
656 | ||
657 | struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) | |
658 | { | |
659 | return &arch_timer_kvm_info; | |
660 | } | |
8a4da6e3 | 661 | |
22006994 SB |
662 | static void __init arch_counter_register(unsigned type) |
663 | { | |
664 | u64 start_count; | |
665 | ||
666 | /* Register the CP15 based counter if we have one */ | |
423bd69e | 667 | if (type & ARCH_CP15_TIMER) { |
f81f03fa | 668 | if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI) |
0b46b8a7 SR |
669 | arch_timer_read_counter = arch_counter_get_cntvct; |
670 | else | |
671 | arch_timer_read_counter = arch_counter_get_cntpct; | |
f6dc1576 | 672 | |
1d8f51d4 SW |
673 | clocksource_counter.archdata.vdso_direct = true; |
674 | ||
16d10ef2 | 675 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
f6dc1576 SW |
676 | /* |
677 | * Don't use the vdso fastpath if errata require using | |
678 | * the out-of-line counter accessor. | |
679 | */ | |
680 | if (static_branch_unlikely(&arch_timer_read_ool_enabled)) | |
1d8f51d4 | 681 | clocksource_counter.archdata.vdso_direct = false; |
f6dc1576 | 682 | #endif |
423bd69e | 683 | } else { |
22006994 | 684 | arch_timer_read_counter = arch_counter_get_cntvct_mem; |
423bd69e NL |
685 | } |
686 | ||
d8ec7595 BN |
687 | if (!arch_counter_suspend_stop) |
688 | clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
22006994 SB |
689 | start_count = arch_timer_read_counter(); |
690 | clocksource_register_hz(&clocksource_counter, arch_timer_rate); | |
691 | cyclecounter.mult = clocksource_counter.mult; | |
692 | cyclecounter.shift = clocksource_counter.shift; | |
b4d6ce97 JG |
693 | timecounter_init(&arch_timer_kvm_info.timecounter, |
694 | &cyclecounter, start_count); | |
4a7d3e8a TR |
695 | |
696 | /* 56 bits minimum, so we assume worst case rollover */ | |
697 | sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); | |
22006994 SB |
698 | } |
699 | ||
8c37bb3a | 700 | static void arch_timer_stop(struct clock_event_device *clk) |
8a4da6e3 MR |
701 | { |
702 | pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n", | |
703 | clk->irq, smp_processor_id()); | |
704 | ||
f81f03fa MZ |
705 | disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]); |
706 | if (arch_timer_has_nonsecure_ppi()) | |
707 | disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
8a4da6e3 | 708 | |
46c5bfdd | 709 | clk->set_state_shutdown(clk); |
8a4da6e3 MR |
710 | } |
711 | ||
7e86e8bd | 712 | static int arch_timer_dying_cpu(unsigned int cpu) |
8a4da6e3 | 713 | { |
7e86e8bd | 714 | struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); |
8a4da6e3 | 715 | |
7e86e8bd RC |
716 | arch_timer_stop(clk); |
717 | return 0; | |
8a4da6e3 MR |
718 | } |
719 | ||
346e7480 SH |
720 | #ifdef CONFIG_CPU_PM |
721 | static unsigned int saved_cntkctl; | |
722 | static int arch_timer_cpu_pm_notify(struct notifier_block *self, | |
723 | unsigned long action, void *hcpu) | |
724 | { | |
725 | if (action == CPU_PM_ENTER) | |
726 | saved_cntkctl = arch_timer_get_cntkctl(); | |
727 | else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) | |
728 | arch_timer_set_cntkctl(saved_cntkctl); | |
729 | return NOTIFY_OK; | |
730 | } | |
731 | ||
732 | static struct notifier_block arch_timer_cpu_pm_notifier = { | |
733 | .notifier_call = arch_timer_cpu_pm_notify, | |
734 | }; | |
735 | ||
736 | static int __init arch_timer_cpu_pm_init(void) | |
737 | { | |
738 | return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier); | |
739 | } | |
7e86e8bd RC |
740 | |
741 | static void __init arch_timer_cpu_pm_deinit(void) | |
742 | { | |
743 | WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier)); | |
744 | } | |
745 | ||
346e7480 SH |
746 | #else |
747 | static int __init arch_timer_cpu_pm_init(void) | |
748 | { | |
749 | return 0; | |
750 | } | |
7e86e8bd RC |
751 | |
752 | static void __init arch_timer_cpu_pm_deinit(void) | |
753 | { | |
754 | } | |
346e7480 SH |
755 | #endif |
756 | ||
8a4da6e3 MR |
757 | static int __init arch_timer_register(void) |
758 | { | |
759 | int err; | |
760 | int ppi; | |
761 | ||
8a4da6e3 MR |
762 | arch_timer_evt = alloc_percpu(struct clock_event_device); |
763 | if (!arch_timer_evt) { | |
764 | err = -ENOMEM; | |
765 | goto out; | |
766 | } | |
767 | ||
f81f03fa MZ |
768 | ppi = arch_timer_ppi[arch_timer_uses_ppi]; |
769 | switch (arch_timer_uses_ppi) { | |
770 | case VIRT_PPI: | |
8a4da6e3 MR |
771 | err = request_percpu_irq(ppi, arch_timer_handler_virt, |
772 | "arch_timer", arch_timer_evt); | |
f81f03fa MZ |
773 | break; |
774 | case PHYS_SECURE_PPI: | |
775 | case PHYS_NONSECURE_PPI: | |
8a4da6e3 MR |
776 | err = request_percpu_irq(ppi, arch_timer_handler_phys, |
777 | "arch_timer", arch_timer_evt); | |
778 | if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) { | |
779 | ppi = arch_timer_ppi[PHYS_NONSECURE_PPI]; | |
780 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
781 | "arch_timer", arch_timer_evt); | |
782 | if (err) | |
783 | free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], | |
784 | arch_timer_evt); | |
785 | } | |
f81f03fa MZ |
786 | break; |
787 | case HYP_PPI: | |
788 | err = request_percpu_irq(ppi, arch_timer_handler_phys, | |
789 | "arch_timer", arch_timer_evt); | |
790 | break; | |
791 | default: | |
792 | BUG(); | |
8a4da6e3 MR |
793 | } |
794 | ||
795 | if (err) { | |
796 | pr_err("arch_timer: can't register interrupt %d (%d)\n", | |
797 | ppi, err); | |
798 | goto out_free; | |
799 | } | |
800 | ||
346e7480 SH |
801 | err = arch_timer_cpu_pm_init(); |
802 | if (err) | |
803 | goto out_unreg_notify; | |
804 | ||
8a4da6e3 | 805 | |
7e86e8bd RC |
806 | /* Register and immediately configure the timer on the boot CPU */ |
807 | err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, | |
73c1b41e | 808 | "clockevents/arm/arch_timer:starting", |
7e86e8bd RC |
809 | arch_timer_starting_cpu, arch_timer_dying_cpu); |
810 | if (err) | |
811 | goto out_unreg_cpupm; | |
8a4da6e3 MR |
812 | return 0; |
813 | ||
7e86e8bd RC |
814 | out_unreg_cpupm: |
815 | arch_timer_cpu_pm_deinit(); | |
816 | ||
346e7480 | 817 | out_unreg_notify: |
f81f03fa MZ |
818 | free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt); |
819 | if (arch_timer_has_nonsecure_ppi()) | |
820 | free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], | |
8a4da6e3 | 821 | arch_timer_evt); |
8a4da6e3 MR |
822 | |
823 | out_free: | |
824 | free_percpu(arch_timer_evt); | |
825 | out: | |
826 | return err; | |
827 | } | |
828 | ||
22006994 SB |
829 | static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) |
830 | { | |
831 | int ret; | |
832 | irq_handler_t func; | |
833 | struct arch_timer *t; | |
834 | ||
835 | t = kzalloc(sizeof(*t), GFP_KERNEL); | |
836 | if (!t) | |
837 | return -ENOMEM; | |
838 | ||
839 | t->base = base; | |
840 | t->evt.irq = irq; | |
841 | __arch_timer_setup(ARCH_MEM_TIMER, &t->evt); | |
842 | ||
843 | if (arch_timer_mem_use_virtual) | |
844 | func = arch_timer_handler_virt_mem; | |
845 | else | |
846 | func = arch_timer_handler_phys_mem; | |
847 | ||
848 | ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt); | |
849 | if (ret) { | |
850 | pr_err("arch_timer: Failed to request mem timer irq\n"); | |
851 | kfree(t); | |
852 | } | |
853 | ||
854 | return ret; | |
855 | } | |
856 | ||
857 | static const struct of_device_id arch_timer_of_match[] __initconst = { | |
858 | { .compatible = "arm,armv7-timer", }, | |
859 | { .compatible = "arm,armv8-timer", }, | |
860 | {}, | |
861 | }; | |
862 | ||
863 | static const struct of_device_id arch_timer_mem_of_match[] __initconst = { | |
864 | { .compatible = "arm,armv7-timer-mem", }, | |
865 | {}, | |
866 | }; | |
867 | ||
c387f07e | 868 | static bool __init |
566e6dfa | 869 | arch_timer_needs_probing(int type, const struct of_device_id *matches) |
c387f07e SH |
870 | { |
871 | struct device_node *dn; | |
566e6dfa | 872 | bool needs_probing = false; |
c387f07e SH |
873 | |
874 | dn = of_find_matching_node(NULL, matches); | |
59aa896d | 875 | if (dn && of_device_is_available(dn) && !(arch_timers_present & type)) |
566e6dfa | 876 | needs_probing = true; |
c387f07e SH |
877 | of_node_put(dn); |
878 | ||
566e6dfa | 879 | return needs_probing; |
c387f07e SH |
880 | } |
881 | ||
3c0731db | 882 | static int __init arch_timer_common_init(void) |
22006994 SB |
883 | { |
884 | unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER; | |
885 | ||
886 | /* Wait until both nodes are probed if we have two timers */ | |
887 | if ((arch_timers_present & mask) != mask) { | |
566e6dfa | 888 | if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match)) |
3c0731db | 889 | return 0; |
566e6dfa | 890 | if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match)) |
3c0731db | 891 | return 0; |
22006994 SB |
892 | } |
893 | ||
894 | arch_timer_banner(arch_timers_present); | |
895 | arch_counter_register(arch_timers_present); | |
3c0731db | 896 | return arch_timer_arch_init(); |
22006994 SB |
897 | } |
898 | ||
3c0731db | 899 | static int __init arch_timer_init(void) |
8a4da6e3 | 900 | { |
3c0731db | 901 | int ret; |
8a4da6e3 | 902 | /* |
8266891e MZ |
903 | * If HYP mode is available, we know that the physical timer |
904 | * has been configured to be accessible from PL1. Use it, so | |
905 | * that a guest can use the virtual timer instead. | |
906 | * | |
8a4da6e3 MR |
907 | * If no interrupt provided for virtual timer, we'll have to |
908 | * stick to the physical timer. It'd better be accessible... | |
f81f03fa MZ |
909 | * |
910 | * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE | |
911 | * accesses to CNTP_*_EL1 registers are silently redirected to | |
912 | * their CNTHP_*_EL2 counterparts, and use a different PPI | |
913 | * number. | |
8a4da6e3 | 914 | */ |
8266891e | 915 | if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { |
f81f03fa MZ |
916 | bool has_ppi; |
917 | ||
918 | if (is_kernel_in_hyp_mode()) { | |
919 | arch_timer_uses_ppi = HYP_PPI; | |
920 | has_ppi = !!arch_timer_ppi[HYP_PPI]; | |
921 | } else { | |
922 | arch_timer_uses_ppi = PHYS_SECURE_PPI; | |
923 | has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] || | |
924 | !!arch_timer_ppi[PHYS_NONSECURE_PPI]); | |
925 | } | |
8a4da6e3 | 926 | |
f81f03fa | 927 | if (!has_ppi) { |
8a4da6e3 | 928 | pr_warn("arch_timer: No interrupt available, giving up\n"); |
3c0731db | 929 | return -EINVAL; |
8a4da6e3 MR |
930 | } |
931 | } | |
932 | ||
3c0731db DL |
933 | ret = arch_timer_register(); |
934 | if (ret) | |
935 | return ret; | |
936 | ||
937 | ret = arch_timer_common_init(); | |
938 | if (ret) | |
939 | return ret; | |
d9b5e415 JG |
940 | |
941 | arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI]; | |
3c0731db DL |
942 | |
943 | return 0; | |
8a4da6e3 | 944 | } |
b09ca1ec | 945 | |
3c0731db | 946 | static int __init arch_timer_of_init(struct device_node *np) |
b09ca1ec HG |
947 | { |
948 | int i; | |
949 | ||
950 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
951 | pr_warn("arch_timer: multiple nodes in dt, skipping\n"); | |
3c0731db | 952 | return 0; |
b09ca1ec HG |
953 | } |
954 | ||
955 | arch_timers_present |= ARCH_CP15_TIMER; | |
956 | for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) | |
957 | arch_timer_ppi[i] = irq_of_parse_and_map(np, i); | |
958 | ||
959 | arch_timer_detect_rate(NULL, np); | |
960 | ||
961 | arch_timer_c3stop = !of_property_read_bool(np, "always-on"); | |
962 | ||
16d10ef2 DT |
963 | #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND |
964 | for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) { | |
965 | if (of_property_read_bool(np, ool_workarounds[i].id)) { | |
966 | timer_unstable_counter_workaround = &ool_workarounds[i]; | |
967 | static_branch_enable(&arch_timer_read_ool_enabled); | |
968 | pr_info("arch_timer: Enabling workaround for %s\n", | |
969 | timer_unstable_counter_workaround->id); | |
970 | break; | |
971 | } | |
f6dc1576 SW |
972 | } |
973 | #endif | |
974 | ||
b09ca1ec HG |
975 | /* |
976 | * If we cannot rely on firmware initializing the timer registers then | |
977 | * we should use the physical timers instead. | |
978 | */ | |
979 | if (IS_ENABLED(CONFIG_ARM) && | |
980 | of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) | |
f81f03fa | 981 | arch_timer_uses_ppi = PHYS_SECURE_PPI; |
b09ca1ec | 982 | |
d8ec7595 BN |
983 | /* On some systems, the counter stops ticking when in suspend. */ |
984 | arch_counter_suspend_stop = of_property_read_bool(np, | |
985 | "arm,no-tick-in-suspend"); | |
986 | ||
3c0731db | 987 | return arch_timer_init(); |
b09ca1ec | 988 | } |
177cf6e5 DL |
989 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); |
990 | CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); | |
22006994 | 991 | |
3c0731db | 992 | static int __init arch_timer_mem_init(struct device_node *np) |
22006994 SB |
993 | { |
994 | struct device_node *frame, *best_frame = NULL; | |
995 | void __iomem *cntctlbase, *base; | |
3c0731db | 996 | unsigned int irq, ret = -EINVAL; |
22006994 SB |
997 | u32 cnttidr; |
998 | ||
999 | arch_timers_present |= ARCH_MEM_TIMER; | |
1000 | cntctlbase = of_iomap(np, 0); | |
1001 | if (!cntctlbase) { | |
1002 | pr_err("arch_timer: Can't find CNTCTLBase\n"); | |
3c0731db | 1003 | return -ENXIO; |
22006994 SB |
1004 | } |
1005 | ||
1006 | cnttidr = readl_relaxed(cntctlbase + CNTTIDR); | |
22006994 SB |
1007 | |
1008 | /* | |
1009 | * Try to find a virtual capable frame. Otherwise fall back to a | |
1010 | * physical capable frame. | |
1011 | */ | |
1012 | for_each_available_child_of_node(np, frame) { | |
1013 | int n; | |
e392d603 | 1014 | u32 cntacr; |
22006994 SB |
1015 | |
1016 | if (of_property_read_u32(frame, "frame-number", &n)) { | |
1017 | pr_err("arch_timer: Missing frame-number\n"); | |
22006994 | 1018 | of_node_put(frame); |
e392d603 | 1019 | goto out; |
22006994 SB |
1020 | } |
1021 | ||
e392d603 RM |
1022 | /* Try enabling everything, and see what sticks */ |
1023 | cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | | |
1024 | CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; | |
1025 | writel_relaxed(cntacr, cntctlbase + CNTACR(n)); | |
1026 | cntacr = readl_relaxed(cntctlbase + CNTACR(n)); | |
1027 | ||
1028 | if ((cnttidr & CNTTIDR_VIRT(n)) && | |
1029 | !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { | |
22006994 SB |
1030 | of_node_put(best_frame); |
1031 | best_frame = frame; | |
1032 | arch_timer_mem_use_virtual = true; | |
1033 | break; | |
1034 | } | |
e392d603 RM |
1035 | |
1036 | if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) | |
1037 | continue; | |
1038 | ||
22006994 SB |
1039 | of_node_put(best_frame); |
1040 | best_frame = of_node_get(frame); | |
1041 | } | |
1042 | ||
3c0731db | 1043 | ret= -ENXIO; |
f947ee14 SB |
1044 | base = arch_counter_base = of_io_request_and_map(best_frame, 0, |
1045 | "arch_mem_timer"); | |
1046 | if (IS_ERR(base)) { | |
22006994 | 1047 | pr_err("arch_timer: Can't map frame's registers\n"); |
e392d603 | 1048 | goto out; |
22006994 SB |
1049 | } |
1050 | ||
1051 | if (arch_timer_mem_use_virtual) | |
1052 | irq = irq_of_parse_and_map(best_frame, 1); | |
1053 | else | |
1054 | irq = irq_of_parse_and_map(best_frame, 0); | |
e392d603 | 1055 | |
3c0731db | 1056 | ret = -EINVAL; |
22006994 SB |
1057 | if (!irq) { |
1058 | pr_err("arch_timer: Frame missing %s irq", | |
cfb6d656 | 1059 | arch_timer_mem_use_virtual ? "virt" : "phys"); |
e392d603 | 1060 | goto out; |
22006994 SB |
1061 | } |
1062 | ||
1063 | arch_timer_detect_rate(base, np); | |
3c0731db DL |
1064 | ret = arch_timer_mem_register(base, irq); |
1065 | if (ret) | |
1066 | goto out; | |
1067 | ||
1068 | return arch_timer_common_init(); | |
e392d603 RM |
1069 | out: |
1070 | iounmap(cntctlbase); | |
1071 | of_node_put(best_frame); | |
3c0731db | 1072 | return ret; |
22006994 | 1073 | } |
177cf6e5 | 1074 | CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", |
22006994 | 1075 | arch_timer_mem_init); |
b09ca1ec HG |
1076 | |
1077 | #ifdef CONFIG_ACPI | |
1078 | static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) | |
1079 | { | |
1080 | int trigger, polarity; | |
1081 | ||
1082 | if (!interrupt) | |
1083 | return 0; | |
1084 | ||
1085 | trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE | |
1086 | : ACPI_LEVEL_SENSITIVE; | |
1087 | ||
1088 | polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW | |
1089 | : ACPI_ACTIVE_HIGH; | |
1090 | ||
1091 | return acpi_register_gsi(NULL, interrupt, trigger, polarity); | |
1092 | } | |
1093 | ||
1094 | /* Initialize per-processor generic timer */ | |
1095 | static int __init arch_timer_acpi_init(struct acpi_table_header *table) | |
1096 | { | |
1097 | struct acpi_table_gtdt *gtdt; | |
1098 | ||
1099 | if (arch_timers_present & ARCH_CP15_TIMER) { | |
1100 | pr_warn("arch_timer: already initialized, skipping\n"); | |
1101 | return -EINVAL; | |
1102 | } | |
1103 | ||
1104 | gtdt = container_of(table, struct acpi_table_gtdt, header); | |
1105 | ||
1106 | arch_timers_present |= ARCH_CP15_TIMER; | |
1107 | ||
1108 | arch_timer_ppi[PHYS_SECURE_PPI] = | |
1109 | map_generic_timer_interrupt(gtdt->secure_el1_interrupt, | |
1110 | gtdt->secure_el1_flags); | |
1111 | ||
1112 | arch_timer_ppi[PHYS_NONSECURE_PPI] = | |
1113 | map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt, | |
1114 | gtdt->non_secure_el1_flags); | |
1115 | ||
1116 | arch_timer_ppi[VIRT_PPI] = | |
1117 | map_generic_timer_interrupt(gtdt->virtual_timer_interrupt, | |
1118 | gtdt->virtual_timer_flags); | |
1119 | ||
1120 | arch_timer_ppi[HYP_PPI] = | |
1121 | map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt, | |
1122 | gtdt->non_secure_el2_flags); | |
1123 | ||
1124 | /* Get the frequency from CNTFRQ */ | |
1125 | arch_timer_detect_rate(NULL, NULL); | |
1126 | ||
1127 | /* Always-on capability */ | |
1128 | arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON); | |
1129 | ||
1130 | arch_timer_init(); | |
1131 | return 0; | |
1132 | } | |
ae281cbd | 1133 | CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init); |
b09ca1ec | 1134 | #endif |