[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / cadence_ttc_timer.c

/*
 * This file contains driver for the Cadence Triple Timer Counter Rev 06
 *
 *  Copyright (C) 2011-2013 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>

/*
 * This driver configures the 2 16-bit count-up timers as follows:
 *
 * T1: Timer 1, clocksource for generic timekeeping
 * T2: Timer 2, clockevent source for hrtimers
 * T3: Timer 3, <unused>
 *
 * The input frequency to the timer module for emulation is 2.5MHz which is
 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
 * the timers are clocked at 78.125KHz (12.8 us resolution).

 * The input frequency to the timer module in silicon is configurable and
 * obtained from device tree. The pre-scaler of 32 is used.
 */

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define TTC_CNT_CNTRL_DISABLE_MASK	0x1

#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */

/*
 * Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1 << 4)

/**
 * struct ttc_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 * @freq:	Timer input clock frequency
 * @clk:	Associated clock source
 * @clk_rate_change_nb	Notifier block for clock rate changes
 */
struct ttc_timer {
	void __iomem *base_addr;
	unsigned long freq;
	struct clk *clk;
	struct notifier_block clk_rate_change_nb;
};

#define to_ttc_timer(x) \
		container_of(x, struct ttc_timer, clk_rate_change_nb)

struct ttc_timer_clocksource {
	struct ttc_timer	ttc;
	struct clocksource	cs;
};

#define to_ttc_timer_clksrc(x) \
		container_of(x, struct ttc_timer_clocksource, cs)

struct ttc_timer_clockevent {
	struct ttc_timer		ttc;
	struct clock_event_device	ce;
};

#define to_ttc_timer_clkevent(x) \
		container_of(x, struct ttc_timer_clockevent, ce)

static void __iomem *ttc_sched_clock_val_reg;

/**
 * ttc_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void ttc_set_interval(struct ttc_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

	__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);

	/*
	 * Reset the counter (0x10) so that it starts from 0, one-shot
	 * mode makes this needed for timing to be right.
	 */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
}

/**
 * ttc_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the ttc_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
{
	struct ttc_timer_clockevent *ttce = dev_id;
	struct ttc_timer *timer = &ttce->ttc;

	/* Acknowledge the interrupt and call event handler */
	__raw_readl(timer->base_addr + TTC_ISR_OFFSET);

	ttce->ce.event_handler(&ttce->ce);

	return IRQ_HANDLED;
}

/**
 * __ttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static cycle_t __ttc_clocksource_read(struct clocksource *cs)
{
	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;

	return (cycle_t)__raw_readl(timer->base_addr +
				TTC_COUNT_VAL_OFFSET);
}

static u64 notrace ttc_sched_clock_read(void)
{
	return __raw_readl(ttc_sched_clock_val_reg);
}

/**
 * ttc_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int ttc_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;

	ttc_set_interval(timer, cycles);
	return 0;
}

/**
 * ttc_set_mode - Sets the mode of timer
 *
 * @mode:	Mode to be set
 * @evt:	Address of clock event instance
 **/
static void ttc_set_mode(enum clock_event_mode mode,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
	u32 ctrl_reg;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
						PRESCALE * HZ));
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl_reg = __raw_readl(timer->base_addr +
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
		break;
	case CLOCK_EVT_MODE_RESUME:
		ctrl_reg = __raw_readl(timer->base_addr +
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
		break;
	}
}

static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clocksource *ttccs = container_of(ttc,
			struct ttc_timer_clocksource, ttc);

	switch (event) {
	case POST_RATE_CHANGE:
		/*
		 * Do whatever is necessary to maintain a proper time base
		 *
		 * I cannot find a way to adjust the currently used clocksource
		 * to the new frequency. __clocksource_updatefreq_hz() sounds
		 * good, but does not work. Not sure what's that missing.
		 *
		 * This approach works, but triggers two clocksource switches.
		 * The first after unregister to clocksource jiffies. And
		 * another one after the register to the newly registered timer.
		 *
		 * Alternatively we could 'waste' another HW timer to ping pong
		 * between clock sources. That would also use one register and
		 * one unregister call, but only trigger one clocksource switch
		 * for the cost of another HW timer used by the OS.
		 */
		clocksource_unregister(&ttccs->cs);
		clocksource_register_hz(&ttccs->cs,
				ndata->new_rate / PRESCALE);
		/* fall through */
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
{
	struct ttc_timer_clocksource *ttccs;
	int err;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (WARN_ON(!ttccs))
		return;

	ttccs->ttc.clk = clk;

	err = clk_prepare_enable(ttccs->ttc.clk);
	if (WARN_ON(err)) {
		kfree(ttccs);
		return;
	}

	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);

	ttccs->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clocksource_cb;
	ttccs->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttccs->ttc.clk,
				&ttccs->ttc.clk_rate_change_nb))
		pr_warn("Unable to register clock notifier.\n");

	ttccs->ttc.base_addr = base;
	ttccs->cs.name = "ttc_clocksource";
	ttccs->cs.rating = 200;
	ttccs->cs.read = __ttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	/*
	 * Setup the clock source counter to be an incrementing counter
	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
	 * it by 32 also. Let it start running now.
	 */
	__raw_writel(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	__raw_writel(CNT_CNTRL_RESET,
		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
	if (WARN_ON(err)) {
		kfree(ttccs);
		return;
	}

	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
	sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
}

static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clockevent *ttcce = container_of(ttc,
			struct ttc_timer_clockevent, ttc);

	switch (event) {
	case POST_RATE_CHANGE:
		/* update cached frequency */
		ttc->freq = ndata->new_rate;

		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);

		/* fall through */
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

static void __init ttc_setup_clockevent(struct clk *clk,
						void __iomem *base, u32 irq)
{
	struct ttc_timer_clockevent *ttcce;
	int err;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (WARN_ON(!ttcce))
		return;

	ttcce->ttc.clk = clk;

	err = clk_prepare_enable(ttcce->ttc.clk);
	if (WARN_ON(err)) {
		kfree(ttcce);
		return;
	}

	ttcce->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clockevent_cb;
	ttcce->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttcce->ttc.clk,
				&ttcce->ttc.clk_rate_change_nb))
		pr_warn("Unable to register clock notifier.\n");
	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);

	ttcce->ttc.base_addr = base;
	ttcce->ce.name = "ttc_clockevent";
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = ttc_set_next_event;
	ttcce->ce.set_mode = ttc_set_mode;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;
	ttcce->ce.cpumask = cpu_possible_mask;

	/*
	 * Setup the clock event timer to be an interval timer which
	 * is prescaled by 32 using the interval interrupt. Leave it
	 * disabled for now.
	 */
	__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	__raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);

	err = request_irq(irq, ttc_clock_event_interrupt,
			  IRQF_TIMER, ttcce->ce.name, ttcce);
	if (WARN_ON(err)) {
		kfree(ttcce);
		return;
	}

	clockevents_config_and_register(&ttcce->ce,
			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
}

/**
 * ttc_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 */
static void __init ttc_timer_init(struct device_node *timer)
{
	unsigned int irq;
	void __iomem *timer_baseaddr;
	struct clk *clk_cs, *clk_ce;
	static int initialized;
	int clksel;

	if (initialized)
		return;

	initialized = 1;

	/*
	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
	 * and use it. Note that the event timer uses the interrupt and it's the
	 * 2nd TTC hence the irq_of_parse_and_map(,1)
	 */
	timer_baseaddr = of_iomap(timer, 0);
	if (!timer_baseaddr) {
		pr_err("ERROR: invalid timer base address\n");
		BUG();
	}

	irq = irq_of_parse_and_map(timer, 1);
	if (irq <= 0) {
		pr_err("ERROR: invalid interrupt number\n");
		BUG();
	}

	clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_cs = of_clk_get(timer, clksel);
	if (IS_ERR(clk_cs)) {
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

	clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_ce = of_clk_get(timer, clksel);
	if (IS_ERR(clk_ce)) {
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

	ttc_setup_clocksource(clk_cs, timer_baseaddr);
	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);

	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
}

CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
Commit	Line	Data
b85a3ef4	1	/*
9e09dc5f	2	* This file contains driver for the Cadence Triple Timer Counter Rev 06
b85a3ef4	3	*
e932900a	4	* Copyright (C) 2011-2013 Xilinx
b85a3ef4 JL	5	*
	6	* based on arch/mips/kernel/time.c timer driver
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
e932900a	18	#include <linux/clk.h>
b85a3ef4	19	#include <linux/interrupt.h>
b85a3ef4	20	#include <linux/clockchips.h>
91dc985c JC	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
	23	#include <linux/slab.h>
3d77b30e	24	#include <linux/sched_clock.h>
b85a3ef4	25
e932900a MS	26	/*
	27	* This driver configures the 2 16-bit count-up timers as follows:
	28	*
	29	* T1: Timer 1, clocksource for generic timekeeping
	30	* T2: Timer 2, clockevent source for hrtimers
	31	* T3: Timer 3, <unused>
	32	*
	33	* The input frequency to the timer module for emulation is 2.5MHz which is
	34	* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
	35	* the timers are clocked at 78.125KHz (12.8 us resolution).
	36
	37	* The input frequency to the timer module in silicon is configurable and
	38	* obtained from device tree. The pre-scaler of 32 is used.
	39	*/
	40
b85a3ef4 JL	41	/*
	42	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	43	* and use same offsets for Timer 2
	44	*/
9e09dc5f MS	45	#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	46	#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	47	#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
	48	#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
	49	#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	50	#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
f184c5ca	51
9e09dc5f	52	#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
b85a3ef4	53
30e1e285 SB	54	#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
30e1e285 SB	55
03377e58 SB	56	/*
03377e58 SB	57	* Setup the timers to use pre-scaling, using a fixed value for now that will
91dc985c JC	58	* work across most input frequency, but it may need to be more dynamic
	59	*/
	60	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	61	#define PRESCALE 2048 /* The exponent must match this */
	62	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	63	#define CLK_CNTRL_PRESCALE_EN 1
e932900a	64	#define CNT_CNTRL_RESET (1 << 4)
b85a3ef4 JL	65
b85a3ef4 JL	66	/**
9e09dc5f	67	* struct ttc_timer - This definition defines local timer structure
b85a3ef4 JL	68	*
b85a3ef4 JL	69	* @base_addr: Base address of timer
c1dcc927	70	* @freq: Timer input clock frequency
e932900a MS	71	* @clk: Associated clock source
	72	* @clk_rate_change_nb Notifier block for clock rate changes
	73	*/
9e09dc5f	74	struct ttc_timer {
e932900a	75	void __iomem *base_addr;
c1dcc927	76	unsigned long freq;
e932900a MS	77	struct clk *clk;
e932900a MS	78	struct notifier_block clk_rate_change_nb;
91dc985c JC	79	};
91dc985c JC	80
9e09dc5f MS	81	#define to_ttc_timer(x) \
9e09dc5f MS	82	container_of(x, struct ttc_timer, clk_rate_change_nb)
e932900a	83
9e09dc5f MS	84	struct ttc_timer_clocksource {
9e09dc5f MS	85	struct ttc_timer ttc;
91dc985c	86	struct clocksource cs;
b85a3ef4 JL	87	};
b85a3ef4 JL	88
9e09dc5f MS	89	#define to_ttc_timer_clksrc(x) \
9e09dc5f MS	90	container_of(x, struct ttc_timer_clocksource, cs)
91dc985c	91
9e09dc5f MS	92	struct ttc_timer_clockevent {
9e09dc5f MS	93	struct ttc_timer ttc;
91dc985c	94	struct clock_event_device ce;
91dc985c JC	95	};
91dc985c JC	96
9e09dc5f MS	97	#define to_ttc_timer_clkevent(x) \
9e09dc5f MS	98	container_of(x, struct ttc_timer_clockevent, ce)
b85a3ef4	99
3d77b30e SB	100	static void __iomem *ttc_sched_clock_val_reg;
3d77b30e SB	101
b85a3ef4	102	/**
9e09dc5f	103	* ttc_set_interval - Set the timer interval value
b85a3ef4 JL	104	*
	105	* @timer: Pointer to the timer instance
	106	* @cycles: Timer interval ticks
	107	**/
9e09dc5f	108	static void ttc_set_interval(struct ttc_timer *timer,
b85a3ef4 JL	109	unsigned long cycles)
	110	{
	111	u32 ctrl_reg;
	112
	113	/* Disable the counter, set the counter value and re-enable counter */
9e09dc5f MS	114	ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	115	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
	116	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4	117
9e09dc5f	118	__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
b85a3ef4	119
03377e58 SB	120	/*
	121	* Reset the counter (0x10) so that it starts from 0, one-shot
	122	* mode makes this needed for timing to be right.
	123	*/
91dc985c	124	ctrl_reg \|= CNT_CNTRL_RESET;
9e09dc5f MS	125	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
9e09dc5f MS	126	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	127	}
	128
	129	/**
9e09dc5f	130	* ttc_clock_event_interrupt - Clock event timer interrupt handler
b85a3ef4 JL	131	*
b85a3ef4 JL	132	* @irq: IRQ number of the Timer
9e09dc5f	133	* @dev_id: void pointer to the ttc_timer instance
b85a3ef4 JL	134	*
	135	* returns: Always IRQ_HANDLED - success
	136	**/
9e09dc5f	137	static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
b85a3ef4	138	{
9e09dc5f MS	139	struct ttc_timer_clockevent *ttce = dev_id;
9e09dc5f MS	140	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	141
b85a3ef4 JL	142	/* Acknowledge the interrupt and call event handler */
9e09dc5f	143	__raw_readl(timer->base_addr + TTC_ISR_OFFSET);
b85a3ef4	144
9e09dc5f	145	ttce->ce.event_handler(&ttce->ce);
b85a3ef4 JL	146
	147	return IRQ_HANDLED;
	148	}
	149
b85a3ef4	150	/**
9e09dc5f	151	* __ttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	152	*
	153	* returns: Current timer counter register value
	154	**/
9e09dc5f	155	static cycle_t __ttc_clocksource_read(struct clocksource *cs)
b85a3ef4	156	{
9e09dc5f	157	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
b85a3ef4 JL	158
b85a3ef4 JL	159	return (cycle_t)__raw_readl(timer->base_addr +
9e09dc5f	160	TTC_COUNT_VAL_OFFSET);
b85a3ef4 JL	161	}
b85a3ef4 JL	162
dfded009	163	static u64 notrace ttc_sched_clock_read(void)
3d77b30e SB	164	{
	165	return __raw_readl(ttc_sched_clock_val_reg);
	166	}
	167
b85a3ef4	168	/**
9e09dc5f	169	* ttc_set_next_event - Sets the time interval for next event
b85a3ef4 JL	170	*
	171	* @cycles: Timer interval ticks
	172	* @evt: Address of clock event instance
	173	*
	174	* returns: Always 0 - success
	175	**/
9e09dc5f	176	static int ttc_set_next_event(unsigned long cycles,
b85a3ef4 JL	177	struct clock_event_device *evt)
b85a3ef4 JL	178	{
9e09dc5f MS	179	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	180	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4	181
9e09dc5f	182	ttc_set_interval(timer, cycles);
b85a3ef4 JL	183	return 0;
	184	}
	185
	186	/**
9e09dc5f	187	* ttc_set_mode - Sets the mode of timer
b85a3ef4 JL	188	*
	189	* @mode: Mode to be set
	190	* @evt: Address of clock event instance
	191	**/
9e09dc5f	192	static void ttc_set_mode(enum clock_event_mode mode,
b85a3ef4 JL	193	struct clock_event_device *evt)
b85a3ef4 JL	194	{
9e09dc5f MS	195	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	196	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	197	u32 ctrl_reg;
	198
	199	switch (mode) {
	200	case CLOCK_EVT_MODE_PERIODIC:
c1dcc927 SB	201	ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
c1dcc927 SB	202	PRESCALE * HZ));
b85a3ef4 JL	203	break;
	204	case CLOCK_EVT_MODE_ONESHOT:
	205	case CLOCK_EVT_MODE_UNUSED:
	206	case CLOCK_EVT_MODE_SHUTDOWN:
	207	ctrl_reg = __raw_readl(timer->base_addr +
9e09dc5f MS	208	TTC_CNT_CNTRL_OFFSET);
9e09dc5f MS	209	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	210	__raw_writel(ctrl_reg,
9e09dc5f	211	timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	212	break;
	213	case CLOCK_EVT_MODE_RESUME:
	214	ctrl_reg = __raw_readl(timer->base_addr +
9e09dc5f MS	215	TTC_CNT_CNTRL_OFFSET);
9e09dc5f MS	216	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	217	__raw_writel(ctrl_reg,
9e09dc5f	218	timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	219	break;
	220	}
	221	}
	222
9e09dc5f	223	static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
e932900a MS	224	unsigned long event, void *data)
	225	{
	226	struct clk_notifier_data *ndata = data;
9e09dc5f MS	227	struct ttc_timer *ttc = to_ttc_timer(nb);
	228	struct ttc_timer_clocksource *ttccs = container_of(ttc,
	229	struct ttc_timer_clocksource, ttc);
e932900a MS	230
	231	switch (event) {
	232	case POST_RATE_CHANGE:
	233	/*
	234	* Do whatever is necessary to maintain a proper time base
	235	*
	236	* I cannot find a way to adjust the currently used clocksource
	237	* to the new frequency. __clocksource_updatefreq_hz() sounds
	238	* good, but does not work. Not sure what's that missing.
	239	*
	240	* This approach works, but triggers two clocksource switches.
	241	* The first after unregister to clocksource jiffies. And
	242	* another one after the register to the newly registered timer.
	243	*
	244	* Alternatively we could 'waste' another HW timer to ping pong
	245	* between clock sources. That would also use one register and
	246	* one unregister call, but only trigger one clocksource switch
	247	* for the cost of another HW timer used by the OS.
	248	*/
9e09dc5f MS	249	clocksource_unregister(&ttccs->cs);
9e09dc5f MS	250	clocksource_register_hz(&ttccs->cs,
e932900a MS	251	ndata->new_rate / PRESCALE);
	252	/* fall through */
	253	case PRE_RATE_CHANGE:
	254	case ABORT_RATE_CHANGE:
	255	default:
	256	return NOTIFY_DONE;
	257	}
	258	}
	259
9e09dc5f	260	static void __init ttc_setup_clocksource(struct clk clk, void __iomem base)
91dc985c	261	{
9e09dc5f	262	struct ttc_timer_clocksource *ttccs;
91dc985c	263	int err;
91dc985c JC	264
	265	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	266	if (WARN_ON(!ttccs))
	267	return;
	268
9e09dc5f	269	ttccs->ttc.clk = clk;
91dc985c	270
9e09dc5f	271	err = clk_prepare_enable(ttccs->ttc.clk);
c5263bb8 MS	272	if (WARN_ON(err)) {
c5263bb8 MS	273	kfree(ttccs);
91dc985c	274	return;
c5263bb8	275	}
91dc985c	276
c1dcc927 SB	277	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
c1dcc927 SB	278
9e09dc5f MS	279	ttccs->ttc.clk_rate_change_nb.notifier_call =
	280	ttc_rate_change_clocksource_cb;
	281	ttccs->ttc.clk_rate_change_nb.next = NULL;
	282	if (clk_notifier_register(ttccs->ttc.clk,
	283	&ttccs->ttc.clk_rate_change_nb))
e932900a	284	pr_warn("Unable to register clock notifier.\n");
91dc985c	285
9e09dc5f MS	286	ttccs->ttc.base_addr = base;
9e09dc5f MS	287	ttccs->cs.name = "ttc_clocksource";
91dc985c	288	ttccs->cs.rating = 200;
9e09dc5f	289	ttccs->cs.read = __ttc_clocksource_read;
91dc985c JC	290	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	291	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	292
e932900a MS	293	/*
	294	* Setup the clock source counter to be an incrementing counter
	295	* with no interrupt and it rolls over at 0xFFFF. Pre-scale
	296	* it by 32 also. Let it start running now.
	297	*/
9e09dc5f	298	__raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
91dc985c	299	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	300	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
91dc985c	301	__raw_writel(CNT_CNTRL_RESET,
9e09dc5f	302	ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
91dc985c	303
c1dcc927	304	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
c5263bb8 MS	305	if (WARN_ON(err)) {
c5263bb8 MS	306	kfree(ttccs);
91dc985c	307	return;
c5263bb8	308	}
3d77b30e SB	309
3d77b30e SB	310	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
6c646143	311	sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
91dc985c JC	312	}
91dc985c JC	313
9e09dc5f	314	static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
e932900a MS	315	unsigned long event, void *data)
	316	{
	317	struct clk_notifier_data *ndata = data;
9e09dc5f MS	318	struct ttc_timer *ttc = to_ttc_timer(nb);
	319	struct ttc_timer_clockevent *ttcce = container_of(ttc,
	320	struct ttc_timer_clockevent, ttc);
e932900a MS	321
	322	switch (event) {
	323	case POST_RATE_CHANGE:
c1dcc927 SB	324	/* update cached frequency */
	325	ttc->freq = ndata->new_rate;
	326
5f0ba3b4 SB	327	clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
5f0ba3b4 SB	328
e932900a	329	/* fall through */
e932900a MS	330	case PRE_RATE_CHANGE:
	331	case ABORT_RATE_CHANGE:
	332	default:
	333	return NOTIFY_DONE;
	334	}
	335	}
	336
9e09dc5f	337	static void __init ttc_setup_clockevent(struct clk *clk,
e932900a	338	void __iomem *base, u32 irq)
91dc985c	339	{
9e09dc5f	340	struct ttc_timer_clockevent *ttcce;
e932900a	341	int err;
91dc985c JC	342
	343	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	344	if (WARN_ON(!ttcce))
	345	return;
	346
9e09dc5f	347	ttcce->ttc.clk = clk;
91dc985c	348
9e09dc5f	349	err = clk_prepare_enable(ttcce->ttc.clk);
c5263bb8 MS	350	if (WARN_ON(err)) {
c5263bb8 MS	351	kfree(ttcce);
91dc985c	352	return;
c5263bb8	353	}
91dc985c	354
9e09dc5f MS	355	ttcce->ttc.clk_rate_change_nb.notifier_call =
	356	ttc_rate_change_clockevent_cb;
	357	ttcce->ttc.clk_rate_change_nb.next = NULL;
	358	if (clk_notifier_register(ttcce->ttc.clk,
	359	&ttcce->ttc.clk_rate_change_nb))
e932900a	360	pr_warn("Unable to register clock notifier.\n");
c1dcc927	361	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
91dc985c	362
9e09dc5f MS	363	ttcce->ttc.base_addr = base;
9e09dc5f MS	364	ttcce->ce.name = "ttc_clockevent";
91dc985c	365	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
9e09dc5f MS	366	ttcce->ce.set_next_event = ttc_set_next_event;
9e09dc5f MS	367	ttcce->ce.set_mode = ttc_set_mode;
91dc985c JC	368	ttcce->ce.rating = 200;
91dc985c JC	369	ttcce->ce.irq = irq;
87e4ee75	370	ttcce->ce.cpumask = cpu_possible_mask;
91dc985c	371
e932900a MS	372	/*
	373	* Setup the clock event timer to be an interval timer which
	374	* is prescaled by 32 using the interval interrupt. Leave it
	375	* disabled for now.
	376	*/
9e09dc5f	377	__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
91dc985c	378	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f MS	379	ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
9e09dc5f MS	380	__raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
91dc985c	381
9e09dc5f	382	err = request_irq(irq, ttc_clock_event_interrupt,
38c30a84	383	IRQF_TIMER, ttcce->ce.name, ttcce);
c5263bb8 MS	384	if (WARN_ON(err)) {
c5263bb8 MS	385	kfree(ttcce);
91dc985c	386	return;
c5263bb8	387	}
91dc985c JC	388
91dc985c JC	389	clockevents_config_and_register(&ttcce->ce,
c1dcc927	390	ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
91dc985c JC	391	}
91dc985c JC	392
b85a3ef4	393	/**
9e09dc5f	394	* ttc_timer_init - Initialize the timer
b85a3ef4 JL	395	*
	396	* Initializes the timer hardware and register the clock source and clock event
	397	* timers with Linux kernal timer framework
e932900a	398	*/
9e09dc5f	399	static void __init ttc_timer_init(struct device_node *timer)
e932900a MS	400	{
	401	unsigned int irq;
	402	void __iomem *timer_baseaddr;
30e1e285	403	struct clk clk_cs, clk_ce;
c5263bb8	404	static int initialized;
30e1e285	405	int clksel;
c5263bb8 MS	406
	407	if (initialized)
	408	return;
	409
	410	initialized = 1;
e932900a MS	411
	412	/*
	413	* Get the 1st Triple Timer Counter (TTC) block from the device tree
	414	* and use it. Note that the event timer uses the interrupt and it's the
	415	* 2nd TTC hence the irq_of_parse_and_map(,1)
	416	*/
	417	timer_baseaddr = of_iomap(timer, 0);
	418	if (!timer_baseaddr) {
	419	pr_err("ERROR: invalid timer base address\n");
	420	BUG();
	421	}
	422
	423	irq = irq_of_parse_and_map(timer, 1);
	424	if (irq <= 0) {
	425	pr_err("ERROR: invalid interrupt number\n");
	426	BUG();
	427	}
	428
30e1e285 SB	429	clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	430	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	431	clk_cs = of_clk_get(timer, clksel);
	432	if (IS_ERR(clk_cs)) {
	433	pr_err("ERROR: timer input clock not found\n");
	434	BUG();
	435	}
	436
	437	clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	438	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	439	clk_ce = of_clk_get(timer, clksel);
	440	if (IS_ERR(clk_ce)) {
e932900a MS	441	pr_err("ERROR: timer input clock not found\n");
	442	BUG();
	443	}
	444
30e1e285 SB	445	ttc_setup_clocksource(clk_cs, timer_baseaddr);
30e1e285 SB	446	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
e932900a MS	447
	448	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
	449	}
	450
9e09dc5f	451	CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);