[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / exynos_mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>

#define EXYNOS4_MCTREG(x)		(x)
#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
#define EXYNOS4_MCT_L_MASK		(0xffffff00)

#define MCT_L_TCNTB_OFFSET		(0x00)
#define MCT_L_ICNTB_OFFSET		(0x08)
#define MCT_L_TCON_OFFSET		(0x20)
#define MCT_L_INT_CSTAT_OFFSET		(0x30)
#define MCT_L_INT_ENB_OFFSET		(0x34)
#define MCT_L_WSTAT_OFFSET		(0x40)
#define MCT_G_TCON_START		(1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
#define MCT_L_TCON_INT_START		(1 << 1)
#define MCT_L_TCON_TIMER_START		(1 << 0)

#define TICK_BASE_CNT	1

enum {
	MCT_INT_SPI,
	MCT_INT_PPI
};

enum {
	MCT_G0_IRQ,
	MCT_G1_IRQ,
	MCT_G2_IRQ,
	MCT_G3_IRQ,
	MCT_L0_IRQ,
	MCT_L1_IRQ,
	MCT_L2_IRQ,
	MCT_L3_IRQ,
	MCT_L4_IRQ,
	MCT_L5_IRQ,
	MCT_L6_IRQ,
	MCT_L7_IRQ,
	MCT_NR_IRQS,
};

static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];

struct mct_clock_event_device {
	struct clock_event_device evt;
	unsigned long base;
	char name[10];
};

static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
	unsigned long stat_addr;
	u32 mask;
	u32 i;

	__raw_writel(value, reg_base + offset);

	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
		switch (offset & EXYNOS4_MCT_L_MASK) {
		case MCT_L_TCON_OFFSET:
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case MCT_L_ICNTB_OFFSET:
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case MCT_L_TCNTB_OFFSET:
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch (offset) {
		case EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (__raw_readl(reg_base + stat_addr) & mask) {
			__raw_writel(mask, reg_base + stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}

/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
{
	u32 reg;

	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);

	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

static cycle_t exynos4_frc_read(struct clocksource *cs)
{
	unsigned int lo, hi;
	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
		hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start(0, 0);
}

struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};

static u64 notrace exynos4_read_sched_clock(void)
{
	return exynos4_frc_read(&mct_frc);
}

static void __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start(0, 0);

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);

	sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
}

static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

static void exynos4_mct_comp0_start(enum clock_event_mode mode,
				    unsigned long cycles)
{
	unsigned int tcon;
	cycle_t comp_cycle;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);

	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(evt->mode, cycles);

	return 0;
}

static void exynos4_comp_set_mode(enum clock_event_mode mode,
				  struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;
	exynos4_mct_comp0_stop();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device mct_comp_device = {
	.name		= "mct-comp",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 250,
	.set_next_event	= exynos4_comp_set_next_event,
	.set_mode	= exynos4_comp_set_mode,
};

static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};

static void exynos4_clockevent_init(void)
{
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mct_comp_device, clk_rate,
					0xf, 0xffffffff);
	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
}

static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;

	tmp = __raw_readl(reg_base + offset);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, offset);
	}
}

static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);

	exynos4_mct_tick_start(cycles, mevt);

	return 0;
}

static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
					 struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	unsigned long cycles_per_jiffy;

	exynos4_mct_tick_stop(mevt);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	struct clock_event_device *evt = &mevt->evt;

	/*
	 * This is for supporting oneshot mode.
	 * Mct would generate interrupt periodically
	 * without explicit stopping.
	 */
	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
		return 1;
	} else {
		return 0;
	}
}

static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = &mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int exynos4_local_timer_setup(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu = smp_processor_id();

	mevt = container_of(evt, struct mct_clock_event_device, evt);

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_mode = exynos4_tick_set_mode;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {
		evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
		if (request_irq(evt->irq, exynos4_mct_tick_isr,
				IRQF_TIMER | IRQF_NOBALANCING,
				evt->name, mevt)) {
			pr_err("exynos-mct: cannot register IRQ %d\n",
				evt->irq);
			return -EIO;
		}
		irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
	} else {
		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
	}
	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
					0xf, 0x7fffffff);

	return 0;
}

static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	if (mct_int_type == MCT_INT_SPI)
		free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
	else
		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}

static int exynos4_mct_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	struct mct_clock_event_device *mevt;

	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_setup(&mevt->evt);
		break;
	case CPU_DYING:
		mevt = this_cpu_ptr(&percpu_mct_tick);
		exynos4_local_timer_stop(&mevt->evt);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos4_mct_cpu_nb = {
	.notifier_call = exynos4_mct_cpu_notify,
};

static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
{
	int err;
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	struct clk *mct_clk, *tick_clk;

	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
				clk_get(NULL, "fin_pll");
	if (IS_ERR(tick_clk))
		panic("%s: unable to determine tick clock rate\n", __func__);
	clk_rate = clk_get_rate(tick_clk);

	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	if (IS_ERR(mct_clk))
		panic("%s: unable to retrieve mct clock instance\n", __func__);
	clk_prepare_enable(mct_clk);

	reg_base = base;
	if (!reg_base)
		panic("%s: unable to ioremap mct address space\n", __func__);

	if (mct_int_type == MCT_INT_PPI) {

		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     mct_irqs[MCT_L0_IRQ], err);
	} else {
		irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
	}

	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	if (err)
		goto out_irq;

	/* Immediately configure the timer on the boot CPU */
	exynos4_local_timer_setup(&mevt->evt);
	return;

out_irq:
	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
}

void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
{
	mct_irqs[MCT_G0_IRQ] = irq_g0;
	mct_irqs[MCT_L0_IRQ] = irq_l0;
	mct_irqs[MCT_L1_IRQ] = irq_l1;
	mct_int_type = MCT_INT_SPI;

	exynos4_timer_resources(NULL, base);
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}

static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
{
	u32 nr_irqs, i;

	mct_int_type = int_type;

	/* This driver uses only one global timer interrupt */
	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);

	/*
	 * Find out the number of local irqs specified. The local
	 * timer irqs are specified after the four global timer
	 * irqs are specified.
	 */
#ifdef CONFIG_OF
	nr_irqs = of_irq_count(np);
#else
	nr_irqs = 0;
#endif
	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
		mct_irqs[i] = irq_of_parse_and_map(np, i);

	exynos4_timer_resources(np, of_iomap(np, 0));
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}


static void __init mct_init_spi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_SPI);
}

static void __init mct_init_ppi(struct device_node *np)
{
	return mct_init_dt(np, MCT_INT_PPI);
}
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Commit	Line	Data
30d8bead CY	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
ee98d27d	19	#include <linux/cpu.h>
30d8bead CY	20	#include <linux/platform_device.h>
	21	#include <linux/delay.h>
	22	#include <linux/percpu.h>
2edb36c4	23	#include <linux/of.h>
36ba5d52 TA	24	#include <linux/of_irq.h>
36ba5d52 TA	25	#include <linux/of_address.h>
9fbf0c85	26	#include <linux/clocksource.h>
93bfb769	27	#include <linux/sched_clock.h>
30d8bead	28
a1ba7a7a TA	29	#define EXYNOS4_MCTREG(x) (x)
	30	#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
	31	#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
	32	#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
	33	#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
	34	#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
	35	#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
	36	#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
	37	#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
	38	#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
	39	#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
	40	#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
	41	#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
	42	#define EXYNOS4_MCT_L_MASK (0xffffff00)
	43
	44	#define MCT_L_TCNTB_OFFSET (0x00)
	45	#define MCT_L_ICNTB_OFFSET (0x08)
	46	#define MCT_L_TCON_OFFSET (0x20)
	47	#define MCT_L_INT_CSTAT_OFFSET (0x30)
	48	#define MCT_L_INT_ENB_OFFSET (0x34)
	49	#define MCT_L_WSTAT_OFFSET (0x40)
	50	#define MCT_G_TCON_START (1 << 8)
	51	#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
	52	#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
	53	#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
	54	#define MCT_L_TCON_INT_START (1 << 1)
	55	#define MCT_L_TCON_TIMER_START (1 << 0)
	56
4d2e4d7f CY	57	#define TICK_BASE_CNT 1
4d2e4d7f CY	58
3a062281 CY	59	enum {
	60	MCT_INT_SPI,
	61	MCT_INT_PPI
	62	};
	63
c371dc60 TA	64	enum {
	65	MCT_G0_IRQ,
	66	MCT_G1_IRQ,
	67	MCT_G2_IRQ,
	68	MCT_G3_IRQ,
	69	MCT_L0_IRQ,
	70	MCT_L1_IRQ,
	71	MCT_L2_IRQ,
	72	MCT_L3_IRQ,
6c16dedf CK	73	MCT_L4_IRQ,
	74	MCT_L5_IRQ,
	75	MCT_L6_IRQ,
	76	MCT_L7_IRQ,
c371dc60 TA	77	MCT_NR_IRQS,
	78	};
	79
a1ba7a7a	80	static void __iomem *reg_base;
30d8bead	81	static unsigned long clk_rate;
3a062281	82	static unsigned int mct_int_type;
c371dc60	83	static int mct_irqs[MCT_NR_IRQS];
30d8bead CY	84
30d8bead CY	85	struct mct_clock_event_device {
ee98d27d	86	struct clock_event_device evt;
a1ba7a7a	87	unsigned long base;
c8987470	88	char name[10];
30d8bead CY	89	};
30d8bead CY	90
a1ba7a7a	91	static void exynos4_mct_write(unsigned int value, unsigned long offset)
30d8bead	92	{
a1ba7a7a	93	unsigned long stat_addr;
30d8bead CY	94	u32 mask;
	95	u32 i;
	96
a1ba7a7a	97	__raw_writel(value, reg_base + offset);
30d8bead	98
a1ba7a7a TA	99	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
	100	stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
	101	switch (offset & EXYNOS4_MCT_L_MASK) {
	102	case MCT_L_TCON_OFFSET:
c8987470 CY	103	mask = 1 << 3; /* L_TCON write status */
c8987470 CY	104	break;
a1ba7a7a	105	case MCT_L_ICNTB_OFFSET:
c8987470 CY	106	mask = 1 << 1; /* L_ICNTB write status */
c8987470 CY	107	break;
a1ba7a7a	108	case MCT_L_TCNTB_OFFSET:
c8987470 CY	109	mask = 1 << 0; /* L_TCNTB write status */
	110	break;
	111	default:
	112	return;
	113	}
	114	} else {
a1ba7a7a TA	115	switch (offset) {
a1ba7a7a TA	116	case EXYNOS4_MCT_G_TCON:
c8987470 CY	117	stat_addr = EXYNOS4_MCT_G_WSTAT;
	118	mask = 1 << 16; /* G_TCON write status */
	119	break;
a1ba7a7a	120	case EXYNOS4_MCT_G_COMP0_L:
c8987470 CY	121	stat_addr = EXYNOS4_MCT_G_WSTAT;
	122	mask = 1 << 0; /* G_COMP0_L write status */
	123	break;
a1ba7a7a	124	case EXYNOS4_MCT_G_COMP0_U:
c8987470 CY	125	stat_addr = EXYNOS4_MCT_G_WSTAT;
	126	mask = 1 << 1; /* G_COMP0_U write status */
	127	break;
a1ba7a7a	128	case EXYNOS4_MCT_G_COMP0_ADD_INCR:
c8987470 CY	129	stat_addr = EXYNOS4_MCT_G_WSTAT;
	130	mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
	131	break;
a1ba7a7a	132	case EXYNOS4_MCT_G_CNT_L:
c8987470 CY	133	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	134	mask = 1 << 0; /* G_CNT_L write status */
	135	break;
a1ba7a7a	136	case EXYNOS4_MCT_G_CNT_U:
c8987470 CY	137	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	138	mask = 1 << 1; /* G_CNT_U write status */
	139	break;
	140	default:
	141	return;
	142	}
30d8bead CY	143	}
	144
	145	/* Wait maximum 1 ms until written values are applied */
	146	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
a1ba7a7a TA	147	if (__raw_readl(reg_base + stat_addr) & mask) {
a1ba7a7a TA	148	__raw_writel(mask, reg_base + stat_addr);
30d8bead CY	149	return;
	150	}
	151
a1ba7a7a	152	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
30d8bead CY	153	}
	154
	155	/* Clocksource handling */
	156	static void exynos4_mct_frc_start(u32 hi, u32 lo)
	157	{
	158	u32 reg;
	159
	160	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	161	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
	162
a1ba7a7a	163	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	164	reg \|= MCT_G_TCON_START;
	165	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	166	}
	167
	168	static cycle_t exynos4_frc_read(struct clocksource *cs)
	169	{
	170	unsigned int lo, hi;
a1ba7a7a	171	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	172
	173	do {
	174	hi = hi2;
a1ba7a7a TA	175	lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
a1ba7a7a TA	176	hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	177	} while (hi != hi2);
	178
	179	return ((cycle_t)hi << 32) \| lo;
	180	}
	181
aa421c13 CY	182	static void exynos4_frc_resume(struct clocksource *cs)
	183	{
	184	exynos4_mct_frc_start(0, 0);
	185	}
	186
30d8bead CY	187	struct clocksource mct_frc = {
	188	.name = "mct-frc",
	189	.rating = 400,
	190	.read = exynos4_frc_read,
	191	.mask = CLOCKSOURCE_MASK(64),
	192	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
aa421c13	193	.resume = exynos4_frc_resume,
30d8bead CY	194	};
30d8bead CY	195
93bfb769 VG	196	static u64 notrace exynos4_read_sched_clock(void)
	197	{
	198	return exynos4_frc_read(&mct_frc);
	199	}
	200
30d8bead CY	201	static void __init exynos4_clocksource_init(void)
	202	{
	203	exynos4_mct_frc_start(0, 0);
	204
	205	if (clocksource_register_hz(&mct_frc, clk_rate))
	206	panic("%s: can't register clocksource\n", mct_frc.name);
93bfb769 VG	207
93bfb769 VG	208	sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
30d8bead CY	209	}
	210
	211	static void exynos4_mct_comp0_stop(void)
	212	{
	213	unsigned int tcon;
	214
a1ba7a7a	215	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	216	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	217
	218	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	219	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	220	}
	221
	222	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	223	unsigned long cycles)
	224	{
	225	unsigned int tcon;
	226	cycle_t comp_cycle;
	227
a1ba7a7a	228	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	229
	230	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	231	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	232	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	233	}
	234
	235	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	236	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	237	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	238
	239	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	240
	241	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	242	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	243	}
	244
	245	static int exynos4_comp_set_next_event(unsigned long cycles,
	246	struct clock_event_device *evt)
	247	{
	248	exynos4_mct_comp0_start(evt->mode, cycles);
	249
	250	return 0;
	251	}
	252
	253	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	254	struct clock_event_device *evt)
	255	{
4d2e4d7f	256	unsigned long cycles_per_jiffy;
30d8bead CY	257	exynos4_mct_comp0_stop();
	258
	259	switch (mode) {
	260	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	261	cycles_per_jiffy =
	262	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	263	exynos4_mct_comp0_start(mode, cycles_per_jiffy);
30d8bead CY	264	break;
	265
	266	case CLOCK_EVT_MODE_ONESHOT:
	267	case CLOCK_EVT_MODE_UNUSED:
	268	case CLOCK_EVT_MODE_SHUTDOWN:
	269	case CLOCK_EVT_MODE_RESUME:
	270	break;
	271	}
	272	}
	273
	274	static struct clock_event_device mct_comp_device = {
	275	.name = "mct-comp",
	276	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	277	.rating = 250,
	278	.set_next_event = exynos4_comp_set_next_event,
	279	.set_mode = exynos4_comp_set_mode,
	280	};
	281
	282	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	283	{
	284	struct clock_event_device *evt = dev_id;
	285
	286	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	287
	288	evt->event_handler(evt);
	289
	290	return IRQ_HANDLED;
	291	}
	292
	293	static struct irqaction mct_comp_event_irq = {
	294	.name = "mct_comp_irq",
	295	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	296	.handler = exynos4_mct_comp_isr,
	297	.dev_id = &mct_comp_device,
	298	};
	299
	300	static void exynos4_clockevent_init(void)
	301	{
30d8bead	302	mct_comp_device.cpumask = cpumask_of(0);
838a2ae8 SG	303	clockevents_config_and_register(&mct_comp_device, clk_rate,
838a2ae8 SG	304	0xf, 0xffffffff);
c371dc60	305	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
30d8bead CY	306	}
30d8bead CY	307
991a6c7d KK	308	static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
991a6c7d KK	309
30d8bead CY	310	/* Clock event handling */
	311	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	312	{
	313	unsigned long tmp;
	314	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
a1ba7a7a	315	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
30d8bead	316
a1ba7a7a	317	tmp = __raw_readl(reg_base + offset);
30d8bead CY	318	if (tmp & mask) {
30d8bead CY	319	tmp &= ~mask;
a1ba7a7a	320	exynos4_mct_write(tmp, offset);
30d8bead CY	321	}
	322	}
	323
	324	static void exynos4_mct_tick_start(unsigned long cycles,
	325	struct mct_clock_event_device *mevt)
	326	{
	327	unsigned long tmp;
	328
	329	exynos4_mct_tick_stop(mevt);
	330
	331	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	332
	333	/* update interrupt count buffer */
	334	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	335
25985edc	336	/* enable MCT tick interrupt */
30d8bead CY	337	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
30d8bead CY	338
a1ba7a7a	339	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
30d8bead CY	340	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	341	MCT_L_TCON_INTERVAL_MODE;
	342	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	343	}
	344
	345	static int exynos4_tick_set_next_event(unsigned long cycles,
	346	struct clock_event_device *evt)
	347	{
e700e41d	348	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
30d8bead CY	349
	350	exynos4_mct_tick_start(cycles, mevt);
	351
	352	return 0;
	353	}
	354
	355	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	356	struct clock_event_device *evt)
	357	{
e700e41d	358	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
4d2e4d7f	359	unsigned long cycles_per_jiffy;
30d8bead CY	360
	361	exynos4_mct_tick_stop(mevt);
	362
	363	switch (mode) {
	364	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	365	cycles_per_jiffy =
	366	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	367	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
30d8bead CY	368	break;
	369
	370	case CLOCK_EVT_MODE_ONESHOT:
	371	case CLOCK_EVT_MODE_UNUSED:
	372	case CLOCK_EVT_MODE_SHUTDOWN:
	373	case CLOCK_EVT_MODE_RESUME:
	374	break;
	375	}
	376	}
	377
c8987470	378	static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
30d8bead	379	{
ee98d27d	380	struct clock_event_device *evt = &mevt->evt;
30d8bead CY	381
	382	/*
	383	* This is for supporting oneshot mode.
	384	* Mct would generate interrupt periodically
	385	* without explicit stopping.
	386	*/
	387	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	388	exynos4_mct_tick_stop(mevt);
	389
	390	/* Clear the MCT tick interrupt */
a1ba7a7a	391	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
3a062281 CY	392	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	393	return 1;
	394	} else {
	395	return 0;
	396	}
	397	}
	398
	399	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	400	{
	401	struct mct_clock_event_device *mevt = dev_id;
ee98d27d	402	struct clock_event_device *evt = &mevt->evt;
3a062281 CY	403
3a062281 CY	404	exynos4_mct_tick_clear(mevt);
30d8bead CY	405
	406	evt->event_handler(evt);
	407
	408	return IRQ_HANDLED;
	409	}
	410
8c37bb3a	411	static int exynos4_local_timer_setup(struct clock_event_device *evt)
30d8bead	412	{
e700e41d	413	struct mct_clock_event_device *mevt;
30d8bead CY	414	unsigned int cpu = smp_processor_id();
30d8bead CY	415
ee98d27d	416	mevt = container_of(evt, struct mct_clock_event_device, evt);
30d8bead	417
e700e41d	418	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
09e15176	419	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
30d8bead	420
e700e41d	421	evt->name = mevt->name;
30d8bead CY	422	evt->cpumask = cpumask_of(cpu);
	423	evt->set_next_event = exynos4_tick_set_next_event;
	424	evt->set_mode = exynos4_tick_set_mode;
	425	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	426	evt->rating = 450;
30d8bead	427
4d2e4d7f	428	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
30d8bead	429
3a062281	430	if (mct_int_type == MCT_INT_SPI) {
7114cd74 CK	431	evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
	432	if (request_irq(evt->irq, exynos4_mct_tick_isr,
	433	IRQF_TIMER \| IRQF_NOBALANCING,
	434	evt->name, mevt)) {
	435	pr_err("exynos-mct: cannot register IRQ %d\n",
	436	evt->irq);
	437	return -EIO;
3a062281	438	}
30ccf03b	439	irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
30d8bead	440	} else {
c371dc60	441	enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
30d8bead	442	}
8db6e510 KK	443	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
8db6e510 KK	444	0xf, 0x7fffffff);
4d487d7e KK	445
4d487d7e KK	446	return 0;
30d8bead CY	447	}
30d8bead CY	448
a8cb6041	449	static void exynos4_local_timer_stop(struct clock_event_device *evt)
30d8bead	450	{
28af690a	451	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
e700e41d	452	if (mct_int_type == MCT_INT_SPI)
7114cd74	453	free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
e700e41d	454	else
c371dc60	455	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
30d8bead	456	}
a8cb6041	457
47dcd356	458	static int exynos4_mct_cpu_notify(struct notifier_block *self,
ee98d27d SB	459	unsigned long action, void *hcpu)
	460	{
	461	struct mct_clock_event_device *mevt;
	462
	463	/*
	464	* Grab cpu pointer in each case to avoid spurious
	465	* preemptible warnings
	466	*/
	467	switch (action & ~CPU_TASKS_FROZEN) {
	468	case CPU_STARTING:
	469	mevt = this_cpu_ptr(&percpu_mct_tick);
	470	exynos4_local_timer_setup(&mevt->evt);
	471	break;
	472	case CPU_DYING:
	473	mevt = this_cpu_ptr(&percpu_mct_tick);
	474	exynos4_local_timer_stop(&mevt->evt);
	475	break;
	476	}
	477
	478	return NOTIFY_OK;
	479	}
	480
47dcd356	481	static struct notifier_block exynos4_mct_cpu_nb = {
ee98d27d	482	.notifier_call = exynos4_mct_cpu_notify,
a8cb6041	483	};
30d8bead	484
19ce4f4a	485	static void __init exynos4_timer_resources(struct device_node np, void __iomem base)
30d8bead	486	{
ee98d27d SB	487	int err;
ee98d27d SB	488	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
ca9048ec	489	struct clk mct_clk, tick_clk;
30d8bead	490
415ac2e2 TA	491	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
	492	clk_get(NULL, "fin_pll");
	493	if (IS_ERR(tick_clk))
	494	panic("%s: unable to determine tick clock rate\n", __func__);
	495	clk_rate = clk_get_rate(tick_clk);
e700e41d	496
ca9048ec TA	497	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
	498	if (IS_ERR(mct_clk))
	499	panic("%s: unable to retrieve mct clock instance\n", __func__);
	500	clk_prepare_enable(mct_clk);
e700e41d	501
228e3023	502	reg_base = base;
36ba5d52 TA	503	if (!reg_base)
36ba5d52 TA	504	panic("%s: unable to ioremap mct address space\n", __func__);
a1ba7a7a	505
e700e41d	506	if (mct_int_type == MCT_INT_PPI) {
e700e41d	507
c371dc60	508	err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
e700e41d MZ	509	exynos4_mct_tick_isr, "MCT",
	510	&percpu_mct_tick);
	511	WARN(err, "MCT: can't request IRQ %d (%d)\n",
c371dc60	512	mct_irqs[MCT_L0_IRQ], err);
5df718d8 TF	513	} else {
5df718d8 TF	514	irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
e700e41d	515	}
a8cb6041	516
ee98d27d SB	517	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
	518	if (err)
	519	goto out_irq;
	520
	521	/* Immediately configure the timer on the boot CPU */
	522	exynos4_local_timer_setup(&mevt->evt);
	523	return;
	524
	525	out_irq:
	526	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
30d8bead CY	527	}
30d8bead CY	528
034c097c	529	void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
30d8bead	530	{
034c097c AB	531	mct_irqs[MCT_G0_IRQ] = irq_g0;
	532	mct_irqs[MCT_L0_IRQ] = irq_l0;
	533	mct_irqs[MCT_L1_IRQ] = irq_l1;
	534	mct_int_type = MCT_INT_SPI;
2edb36c4	535
034c097c	536	exynos4_timer_resources(NULL, base);
30d8bead CY	537	exynos4_clocksource_init();
	538	exynos4_clockevent_init();
	539	}
3a062281	540
228e3023 AB	541	static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
	542	{
	543	u32 nr_irqs, i;
	544
	545	mct_int_type = int_type;
	546
	547	/* This driver uses only one global timer interrupt */
	548	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
	549
	550	/*
	551	* Find out the number of local irqs specified. The local
	552	* timer irqs are specified after the four global timer
	553	* irqs are specified.
	554	*/
f4636d0a	555	#ifdef CONFIG_OF
228e3023	556	nr_irqs = of_irq_count(np);
f4636d0a AB	557	#else
	558	nr_irqs = 0;
	559	#endif
228e3023 AB	560	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
	561	mct_irqs[i] = irq_of_parse_and_map(np, i);
	562
19ce4f4a	563	exynos4_timer_resources(np, of_iomap(np, 0));
30d8bead CY	564	exynos4_clocksource_init();
	565	exynos4_clockevent_init();
	566	}
228e3023 AB	567
	568
	569	static void __init mct_init_spi(struct device_node *np)
	570	{
	571	return mct_init_dt(np, MCT_INT_SPI);
	572	}
	573
	574	static void __init mct_init_ppi(struct device_node *np)
	575	{
	576	return mct_init_dt(np, MCT_INT_PPI);
	577	}
	578	CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
	579	CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);