[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / h8300_timer8.c

/*
 *  linux/arch/h8300/kernel/cpu/timer/timer8.c
 *
 *  Yoshinori Sato <ysato@users.sourcefoge.jp>
 *
 *  8bit Timer driver
 *
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define _8TCR	0
#define _8TCSR	2
#define TCORA	4
#define TCORB	6
#define _8TCNT	8

#define FLAG_STARTED (1 << 3)

#define SCALE 64

struct timer8_priv {
	struct clock_event_device ced;
	unsigned long mapbase;
	unsigned long flags;
	unsigned int rate;
	unsigned int tcora;
};

static unsigned long timer8_get_counter(struct timer8_priv *p)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = ctrl_inw(p->mapbase + _8TCNT);
		v2 = ctrl_inw(p->mapbase + _8TCNT);
		v3 = ctrl_inw(p->mapbase + _8TCNT);
		o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	v2 |= o1 << 10;
	return v2;
}

static irqreturn_t timer8_interrupt(int irq, void *dev_id)
{
	struct timer8_priv *p = dev_id;

	ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x40,
		  p->mapbase + _8TCSR);

	ctrl_outw(p->tcora, p->mapbase + TCORA);

	if (clockevent_state_oneshot(&p->ced))
		ctrl_outw(0x0000, p->mapbase + _8TCR);

	p->ced.event_handler(&p->ced);

	return IRQ_HANDLED;
}

static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
{
	unsigned long now;

	if (delta >= 0x10000)
		pr_warn("delta out of range\n");
	now = timer8_get_counter(p);
	p->tcora = delta;
	ctrl_outb(ctrl_inb(p->mapbase + _8TCR) | 0x40, p->mapbase + _8TCR);
	if (delta > now)
		ctrl_outw(delta, p->mapbase + TCORA);
	else
		ctrl_outw(now + 1, p->mapbase + TCORA);
}

static int timer8_enable(struct timer8_priv *p)
{
	ctrl_outw(0xffff, p->mapbase + TCORA);
	ctrl_outw(0x0000, p->mapbase + _8TCNT);
	ctrl_outw(0x0c02, p->mapbase + _8TCR);

	return 0;
}

static int timer8_start(struct timer8_priv *p)
{
	int ret;

	if ((p->flags & FLAG_STARTED))
		return 0;

	ret = timer8_enable(p);
	if (!ret)
		p->flags |= FLAG_STARTED;

	return ret;
}

static void timer8_stop(struct timer8_priv *p)
{
	ctrl_outw(0x0000, p->mapbase + _8TCR);
}

static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
{
	return container_of(ced, struct timer8_priv, ced);
}

static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
{
	struct clock_event_device *ced = &p->ced;

	timer8_start(p);

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);

	timer8_set_next(p, delta);
}

static int timer8_clock_event_shutdown(struct clock_event_device *ced)
{
	timer8_stop(ced_to_priv(ced));
	return 0;
}

static int timer8_clock_event_periodic(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for periodic clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);

	return 0;
}

static int timer8_clock_event_oneshot(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for oneshot clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, 0x10000);

	return 0;
}

static int timer8_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	BUG_ON(!clockevent_state_oneshot(ced));
	timer8_set_next(p, delta - 1);

	return 0;
}

static struct timer8_priv timer8_priv = {
	.ced = {
		.name = "h8300_8timer",
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.rating = 200,
		.set_next_event = timer8_clock_event_next,
		.set_state_shutdown = timer8_clock_event_shutdown,
		.set_state_periodic = timer8_clock_event_periodic,
		.set_state_oneshot = timer8_clock_event_oneshot,
	},
};

static void __init h8300_8timer_init(struct device_node *node)
{
	void __iomem *base;
	int irq;
	int ret = 0;
	int rate;
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clockevent\n");
		return;
	}

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("failed to map registers for clockevent\n");
		goto free_clk;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		pr_err("failed to get irq for clockevent\n");
		goto unmap_reg;
	}

	timer8_priv.mapbase = (unsigned long)base;

	rate = clk_get_rate(clk) / SCALE;
	if (!rate) {
		pr_err("Failed to get rate for the clocksource\n");
		goto unmap_reg;
	}

	ret = request_irq(irq, timer8_interrupt,
			  IRQF_TIMER, timer8_priv.ced.name, &timer8_priv);
	if (ret < 0) {
		pr_err("failed to request irq %d for clockevent\n", irq);
		goto unmap_reg;
	}

	clockevents_config_and_register(&timer8_priv.ced, rate, 1, 0x0000ffff);

	return;
unmap_reg:
	iounmap(base);
free_clk:
	clk_put(clk);
}

CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
Commit	Line	Data
618b902d YS	1	/*
	2	* linux/arch/h8300/kernel/cpu/timer/timer8.c
	3	*
	4	* Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*
	6	* 8bit Timer driver
	7	*
	8	*/
	9
	10	#include <linux/errno.h>
618b902d YS	11	#include <linux/kernel.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/init.h>
618b902d	14	#include <linux/clockchips.h>
618b902d YS	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
4633f4ca YS	18	#include <linux/of_address.h>
4633f4ca YS	19	#include <linux/of_irq.h>
618b902d	20
618b902d YS	21	#define _8TCR 0
	22	#define _8TCSR 2
	23	#define TCORA 4
	24	#define TCORB 6
	25	#define _8TCNT 8
	26
618b902d YS	27	#define FLAG_STARTED (1 << 3)
618b902d YS	28
4633f4ca YS	29	#define SCALE 64
4633f4ca YS	30
618b902d	31	struct timer8_priv {
618b902d	32	struct clock_event_device ced;
618b902d	33	unsigned long mapbase;
618b902d YS	34	unsigned long flags;
	35	unsigned int rate;
	36	unsigned int tcora;
618b902d YS	37	};
	38
	39	static unsigned long timer8_get_counter(struct timer8_priv *p)
	40	{
	41	unsigned long v1, v2, v3;
	42	int o1, o2;
	43
	44	o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
	45
	46	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	47	do {
	48	o2 = o1;
	49	v1 = ctrl_inw(p->mapbase + _8TCNT);
	50	v2 = ctrl_inw(p->mapbase + _8TCNT);
	51	v3 = ctrl_inw(p->mapbase + _8TCNT);
	52	o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
	53	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
	54	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
	55
	56	v2 \|= o1 << 10;
	57	return v2;
	58	}
	59
	60	static irqreturn_t timer8_interrupt(int irq, void *dev_id)
	61	{
	62	struct timer8_priv *p = dev_id;
	63
	64	ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x40,
	65	p->mapbase + _8TCSR);
7053fdac	66
618b902d	67	ctrl_outw(p->tcora, p->mapbase + TCORA);
7053fdac DL	68
	69	if (clockevent_state_oneshot(&p->ced))
	70	ctrl_outw(0x0000, p->mapbase + _8TCR);
	71
	72	p->ced.event_handler(&p->ced);
618b902d YS	73
	74	return IRQ_HANDLED;
	75	}
	76
	77	static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
	78	{
618b902d YS	79	unsigned long now;
618b902d YS	80
618b902d	81	if (delta >= 0x10000)
8c09b7d6	82	pr_warn("delta out of range\n");
618b902d YS	83	now = timer8_get_counter(p);
	84	p->tcora = delta;
	85	ctrl_outb(ctrl_inb(p->mapbase + _8TCR) \| 0x40, p->mapbase + _8TCR);
	86	if (delta > now)
	87	ctrl_outw(delta, p->mapbase + TCORA);
	88	else
	89	ctrl_outw(now + 1, p->mapbase + TCORA);
618b902d YS	90	}
	91
	92	static int timer8_enable(struct timer8_priv *p)
	93	{
618b902d YS	94	ctrl_outw(0xffff, p->mapbase + TCORA);
	95	ctrl_outw(0x0000, p->mapbase + _8TCNT);
	96	ctrl_outw(0x0c02, p->mapbase + _8TCR);
	97
	98	return 0;
	99	}
	100
	101	static int timer8_start(struct timer8_priv *p)
	102	{
cce483e0	103	int ret;
618b902d	104
cce483e0 DL	105	if ((p->flags & FLAG_STARTED))
cce483e0 DL	106	return 0;
618b902d	107
cce483e0 DL	108	ret = timer8_enable(p);
	109	if (!ret)
	110	p->flags \|= FLAG_STARTED;
618b902d	111
618b902d YS	112	return ret;
	113	}
	114
	115	static void timer8_stop(struct timer8_priv *p)
	116	{
618b902d	117	ctrl_outw(0x0000, p->mapbase + _8TCR);
618b902d YS	118	}
	119
	120	static inline struct timer8_priv ced_to_priv(struct clock_event_device ced)
	121	{
	122	return container_of(ced, struct timer8_priv, ced);
	123	}
	124
1f058d52	125	static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
618b902d YS	126	{
	127	struct clock_event_device *ced = &p->ced;
	128
	129	timer8_start(p);
	130
	131	ced->shift = 32;
	132	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	133	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	134	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
	135
1f058d52	136	timer8_set_next(p, delta);
618b902d YS	137	}
618b902d YS	138
fc2b2f5d VK	139	static int timer8_clock_event_shutdown(struct clock_event_device *ced)
	140	{
	141	timer8_stop(ced_to_priv(ced));
	142	return 0;
	143	}
	144
	145	static int timer8_clock_event_periodic(struct clock_event_device *ced)
618b902d YS	146	{
	147	struct timer8_priv *p = ced_to_priv(ced);
	148
4633f4ca	149	pr_info("%s: used for periodic clock events\n", ced->name);
fc2b2f5d	150	timer8_stop(p);
1f058d52	151	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
fc2b2f5d VK	152
	153	return 0;
	154	}
	155
	156	static int timer8_clock_event_oneshot(struct clock_event_device *ced)
	157	{
	158	struct timer8_priv *p = ced_to_priv(ced);
	159
4633f4ca	160	pr_info("%s: used for oneshot clock events\n", ced->name);
fc2b2f5d	161	timer8_stop(p);
1f058d52	162	timer8_clock_event_start(p, 0x10000);
fc2b2f5d VK	163
fc2b2f5d VK	164	return 0;
618b902d YS	165	}
	166
	167	static int timer8_clock_event_next(unsigned long delta,
	168	struct clock_event_device *ced)
	169	{
	170	struct timer8_priv *p = ced_to_priv(ced);
	171
fc2b2f5d	172	BUG_ON(!clockevent_state_oneshot(ced));
618b902d YS	173	timer8_set_next(p, delta - 1);
	174
	175	return 0;
	176	}
	177
4633f4ca YS	178	static struct timer8_priv timer8_priv = {
	179	.ced = {
	180	.name = "h8300_8timer",
	181	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	182	.rating = 200,
	183	.set_next_event = timer8_clock_event_next,
	184	.set_state_shutdown = timer8_clock_event_shutdown,
	185	.set_state_periodic = timer8_clock_event_periodic,
	186	.set_state_oneshot = timer8_clock_event_oneshot,
	187	},
	188	};
	189
	190	static void __init h8300_8timer_init(struct device_node *node)
618b902d	191	{
4633f4ca	192	void __iomem *base;
618b902d	193	int irq;
4633f4ca YS	194	int ret = 0;
	195	int rate;
	196	struct clk *clk;
618b902d	197
4633f4ca YS	198	clk = of_clk_get(node, 0);
	199	if (IS_ERR(clk)) {
	200	pr_err("failed to get clock for clockevent\n");
	201	return;
	202	}
618b902d	203
4633f4ca YS	204	base = of_iomap(node, 0);
	205	if (!base) {
	206	pr_err("failed to map registers for clockevent\n");
	207	goto free_clk;
618b902d YS	208	}
618b902d YS	209
4633f4ca	210	irq = irq_of_parse_and_map(node, 0);
54a0cd5a	211	if (!irq) {
4633f4ca YS	212	pr_err("failed to get irq for clockevent\n");
4633f4ca YS	213	goto unmap_reg;
618b902d YS	214	}
618b902d YS	215
4633f4ca	216	timer8_priv.mapbase = (unsigned long)base;
cce483e0 DL	217
	218	rate = clk_get_rate(clk) / SCALE;
	219	if (!rate) {
	220	pr_err("Failed to get rate for the clocksource\n");
	221	goto unmap_reg;
	222	}
618b902d	223
4633f4ca YS	224	ret = request_irq(irq, timer8_interrupt,
4633f4ca YS	225	IRQF_TIMER, timer8_priv.ced.name, &timer8_priv);
618b902d	226	if (ret < 0) {
4633f4ca YS	227	pr_err("failed to request irq %d for clockevent\n", irq);
4633f4ca YS	228	goto unmap_reg;
618b902d	229	}
cce483e0	230
4633f4ca	231	clockevents_config_and_register(&timer8_priv.ced, rate, 1, 0x0000ffff);
4633f4ca	232
cce483e0	233	return;
4633f4ca YS	234	unmap_reg:
	235	iounmap(base);
	236	free_clk:
	237	clk_put(clk);
618b902d YS	238	}
618b902d YS	239
4633f4ca	240	CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);