[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / h8300_tpu.c

/*
 *  H8S TPU Driver
 *
 *  Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
 *
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TCR	0x0
#define TSR	0x5
#define TCNT	0x6

struct tpu_priv {
	struct clocksource cs;
	void __iomem *mapbase1;
	void __iomem *mapbase2;
	raw_spinlock_t lock;
	unsigned int cs_enabled;
};

static inline unsigned long read_tcnt32(struct tpu_priv *p)
{
	unsigned long tcnt;

	tcnt = readw(p->mapbase1 + TCNT) << 16;
	tcnt |= readw(p->mapbase2 + TCNT);
	return tcnt;
}

static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = readb(p->mapbase1 + TSR) & 0x10;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = read_tcnt32(p);
		v2 = read_tcnt32(p);
		v3 = read_tcnt32(p);
		o1 = readb(p->mapbase1 + TSR) & 0x10;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	*val = v2;
	return o1;
}

static inline struct tpu_priv *cs_to_priv(struct clocksource *cs)
{
	return container_of(cs, struct tpu_priv, cs);
}

static cycle_t tpu_clocksource_read(struct clocksource *cs)
{
	struct tpu_priv *p = cs_to_priv(cs);
	unsigned long flags;
	unsigned long long value;

	raw_spin_lock_irqsave(&p->lock, flags);
	if (tpu_get_counter(p, &value))
		value += 0x100000000;
	raw_spin_unlock_irqrestore(&p->lock, flags);

	return value;
}

static int tpu_clocksource_enable(struct clocksource *cs)
{
	struct tpu_priv *p = cs_to_priv(cs);

	WARN_ON(p->cs_enabled);

	writew(0, p->mapbase1 + TCNT);
	writew(0, p->mapbase2 + TCNT);
	writeb(0x0f, p->mapbase1 + TCR);
	writeb(0x03, p->mapbase2 + TCR);

	p->cs_enabled = true;
	return 0;
}

static void tpu_clocksource_disable(struct clocksource *cs)
{
	struct tpu_priv *p = cs_to_priv(cs);

	WARN_ON(!p->cs_enabled);

	writeb(0, p->mapbase1 + TCR);
	writeb(0, p->mapbase2 + TCR);
	p->cs_enabled = false;
}

static struct tpu_priv tpu_priv = {
	.cs = {
		.name = "H8S_TPU",
		.rating = 200,
		.read = tpu_clocksource_read,
		.enable = tpu_clocksource_enable,
		.disable = tpu_clocksource_disable,
		.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
		.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	},
};

#define CH_L 0
#define CH_H 1

static void __init h8300_tpu_init(struct device_node *node)
{
	void __iomem *base[2];
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clocksource\n");
		return;
	}

	base[CH_L] = of_iomap(node, CH_L);
	if (!base[CH_L]) {
		pr_err("failed to map registers for clocksource\n");
		goto free_clk;
	}
	base[CH_H] = of_iomap(node, CH_H);
	if (!base[CH_H]) {
		pr_err("failed to map registers for clocksource\n");
		goto unmap_L;
	}

	tpu_priv.mapbase1 = base[CH_L];
	tpu_priv.mapbase2 = base[CH_H];

	clocksource_register_hz(&tpu_priv.cs, clk_get_rate(clk) / 64);

	return;

unmap_L:
	iounmap(base[CH_H]);
free_clk:
	clk_put(clk);
}

CLOCKSOURCE_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init);
Commit	Line	Data
618b902d	1	/*
4633f4ca	2	* H8S TPU Driver
618b902d YS	3	*
	4	* Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*
	6	*/
	7
	8	#include <linux/errno.h>
618b902d	9	#include <linux/kernel.h>
618b902d	10	#include <linux/init.h>
618b902d	11	#include <linux/clocksource.h>
618b902d YS	12	#include <linux/clk.h>
	13	#include <linux/io.h>
	14	#include <linux/of.h>
4633f4ca YS	15	#include <linux/of_address.h>
4633f4ca YS	16	#include <linux/of_irq.h>
618b902d	17
9471f1d9 DL	18	#define TCR 0x0
	19	#define TSR 0x5
	20	#define TCNT 0x6
618b902d YS	21
618b902d YS	22	struct tpu_priv {
618b902d	23	struct clocksource cs;
75160515 DL	24	void __iomem *mapbase1;
75160515 DL	25	void __iomem *mapbase2;
618b902d YS	26	raw_spinlock_t lock;
	27	unsigned int cs_enabled;
	28	};
	29
	30	static inline unsigned long read_tcnt32(struct tpu_priv *p)
	31	{
	32	unsigned long tcnt;
	33
75160515 DL	34	tcnt = readw(p->mapbase1 + TCNT) << 16;
75160515 DL	35	tcnt \|= readw(p->mapbase2 + TCNT);
618b902d YS	36	return tcnt;
	37	}
	38
	39	static int tpu_get_counter(struct tpu_priv p, unsigned long long val)
	40	{
	41	unsigned long v1, v2, v3;
	42	int o1, o2;
	43
75160515	44	o1 = readb(p->mapbase1 + TSR) & 0x10;
618b902d YS	45
	46	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	47	do {
	48	o2 = o1;
	49	v1 = read_tcnt32(p);
	50	v2 = read_tcnt32(p);
	51	v3 = read_tcnt32(p);
75160515	52	o1 = readb(p->mapbase1 + TSR) & 0x10;
618b902d YS	53	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
	54	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
	55
	56	*val = v2;
	57	return o1;
	58	}
	59
	60	static inline struct tpu_priv cs_to_priv(struct clocksource cs)
	61	{
	62	return container_of(cs, struct tpu_priv, cs);
	63	}
	64
	65	static cycle_t tpu_clocksource_read(struct clocksource *cs)
	66	{
	67	struct tpu_priv *p = cs_to_priv(cs);
	68	unsigned long flags;
	69	unsigned long long value;
	70
	71	raw_spin_lock_irqsave(&p->lock, flags);
	72	if (tpu_get_counter(p, &value))
	73	value += 0x100000000;
	74	raw_spin_unlock_irqrestore(&p->lock, flags);
	75
	76	return value;
	77	}
	78
	79	static int tpu_clocksource_enable(struct clocksource *cs)
	80	{
	81	struct tpu_priv *p = cs_to_priv(cs);
	82
	83	WARN_ON(p->cs_enabled);
	84
75160515 DL	85	writew(0, p->mapbase1 + TCNT);
	86	writew(0, p->mapbase2 + TCNT);
	87	writeb(0x0f, p->mapbase1 + TCR);
	88	writeb(0x03, p->mapbase2 + TCR);
618b902d YS	89
	90	p->cs_enabled = true;
	91	return 0;
	92	}
	93
	94	static void tpu_clocksource_disable(struct clocksource *cs)
	95	{
	96	struct tpu_priv *p = cs_to_priv(cs);
	97
	98	WARN_ON(!p->cs_enabled);
	99
75160515 DL	100	writeb(0, p->mapbase1 + TCR);
75160515 DL	101	writeb(0, p->mapbase2 + TCR);
618b902d YS	102	p->cs_enabled = false;
	103	}
	104
4633f4ca YS	105	static struct tpu_priv tpu_priv = {
	106	.cs = {
	107	.name = "H8S_TPU",
	108	.rating = 200,
	109	.read = tpu_clocksource_read,
	110	.enable = tpu_clocksource_enable,
	111	.disable = tpu_clocksource_disable,
	112	.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
	113	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	114	},
	115	};
	116
618b902d YS	117	#define CH_L 0
	118	#define CH_H 1
	119
4633f4ca	120	static void __init h8300_tpu_init(struct device_node *node)
618b902d	121	{
4633f4ca YS	122	void __iomem *base[2];
4633f4ca YS	123	struct clk *clk;
618b902d	124
4633f4ca YS	125	clk = of_clk_get(node, 0);
	126	if (IS_ERR(clk)) {
	127	pr_err("failed to get clock for clocksource\n");
	128	return;
618b902d YS	129	}
618b902d YS	130
4633f4ca YS	131	base[CH_L] = of_iomap(node, CH_L);
	132	if (!base[CH_L]) {
	133	pr_err("failed to map registers for clocksource\n");
	134	goto free_clk;
618b902d	135	}
4633f4ca YS	136	base[CH_H] = of_iomap(node, CH_H);
	137	if (!base[CH_H]) {
	138	pr_err("failed to map registers for clocksource\n");
	139	goto unmap_L;
618b902d YS	140	}
618b902d YS	141
75160515 DL	142	tpu_priv.mapbase1 = base[CH_L];
75160515 DL	143	tpu_priv.mapbase2 = base[CH_H];
618b902d	144
4633f4ca	145	clocksource_register_hz(&tpu_priv.cs, clk_get_rate(clk) / 64);
618b902d	146
4633f4ca	147	return;
618b902d	148
4633f4ca YS	149	unmap_L:
	150	iounmap(base[CH_H]);
	151	free_clk:
	152	clk_put(clk);
618b902d YS	153	}
618b902d YS	154
4633f4ca	155	CLOCKSOURCE_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init);