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Commit | Line | Data |
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778eeb1b SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
7 | */ | |
3ca5768d MR |
8 | |
9 | #define pr_fmt(fmt) "mips-gic-timer: " fmt | |
10 | ||
5b4e8453 | 11 | #include <linux/clk.h> |
a331ce63 | 12 | #include <linux/clockchips.h> |
e4752dbb | 13 | #include <linux/cpu.h> |
778eeb1b | 14 | #include <linux/init.h> |
a331ce63 | 15 | #include <linux/interrupt.h> |
e4752dbb | 16 | #include <linux/notifier.h> |
e12aa828 | 17 | #include <linux/of_irq.h> |
a331ce63 | 18 | #include <linux/percpu.h> |
48016e78 | 19 | #include <linux/sched_clock.h> |
a331ce63 | 20 | #include <linux/smp.h> |
dfa762e1 | 21 | #include <linux/time.h> |
e07127a0 | 22 | #include <asm/mips-cps.h> |
778eeb1b | 23 | |
5fee56e0 | 24 | static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); |
e4752dbb | 25 | static int gic_timer_irq; |
b0854514 | 26 | static unsigned int gic_frequency; |
7d7de1a6 SS |
27 | static bool __read_mostly gic_clock_unstable; |
28 | ||
29 | static void gic_clocksource_unstable(char *reason); | |
a331ce63 | 30 | |
48016e78 | 31 | static u64 notrace gic_read_count_2x32(void) |
e07127a0 PB |
32 | { |
33 | unsigned int hi, hi2, lo; | |
34 | ||
e07127a0 PB |
35 | do { |
36 | hi = read_gic_counter_32h(); | |
37 | lo = read_gic_counter_32l(); | |
38 | hi2 = read_gic_counter_32h(); | |
39 | } while (hi2 != hi); | |
40 | ||
41 | return (((u64) hi) << 32) + lo; | |
42 | } | |
43 | ||
48016e78 PB |
44 | static u64 notrace gic_read_count_64(void) |
45 | { | |
46 | return read_gic_counter(); | |
47 | } | |
48 | ||
49 | static u64 notrace gic_read_count(void) | |
50 | { | |
51 | if (mips_cm_is64) | |
52 | return gic_read_count_64(); | |
53 | ||
54 | return gic_read_count_2x32(); | |
55 | } | |
56 | ||
a331ce63 AB |
57 | static int gic_next_event(unsigned long delta, struct clock_event_device *evt) |
58 | { | |
f16ff2bd | 59 | int cpu = cpumask_first(evt->cpumask); |
a331ce63 AB |
60 | u64 cnt; |
61 | int res; | |
62 | ||
63 | cnt = gic_read_count(); | |
64 | cnt += (u64)delta; | |
f16ff2bd MR |
65 | if (cpu == raw_smp_processor_id()) { |
66 | write_gic_vl_compare(cnt); | |
67 | } else { | |
68 | write_gic_vl_other(mips_cm_vp_id(cpu)); | |
69 | write_gic_vo_compare(cnt); | |
70 | } | |
a331ce63 AB |
71 | res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; |
72 | return res; | |
73 | } | |
74 | ||
5fee56e0 | 75 | static irqreturn_t gic_compare_interrupt(int irq, void *dev_id) |
a331ce63 | 76 | { |
f7ea3060 | 77 | struct clock_event_device *cd = dev_id; |
a331ce63 | 78 | |
e07127a0 | 79 | write_gic_vl_compare(read_gic_vl_compare()); |
a331ce63 AB |
80 | cd->event_handler(cd); |
81 | return IRQ_HANDLED; | |
82 | } | |
83 | ||
9039de40 | 84 | static struct irqaction gic_compare_irqaction = { |
a331ce63 | 85 | .handler = gic_compare_interrupt, |
f7ea3060 | 86 | .percpu_dev_id = &gic_clockevent_device, |
a331ce63 AB |
87 | .flags = IRQF_PERCPU | IRQF_TIMER, |
88 | .name = "timer", | |
89 | }; | |
90 | ||
2dab9093 RC |
91 | static void gic_clockevent_cpu_init(unsigned int cpu, |
92 | struct clock_event_device *cd) | |
a331ce63 | 93 | { |
a331ce63 AB |
94 | cd->name = "MIPS GIC"; |
95 | cd->features = CLOCK_EVT_FEAT_ONESHOT | | |
96 | CLOCK_EVT_FEAT_C3STOP; | |
97 | ||
a45da565 | 98 | cd->rating = 350; |
e4752dbb | 99 | cd->irq = gic_timer_irq; |
a331ce63 AB |
100 | cd->cpumask = cpumask_of(cpu); |
101 | cd->set_next_event = gic_next_event; | |
a331ce63 | 102 | |
b695d8e6 | 103 | clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff); |
a331ce63 | 104 | |
e4752dbb AB |
105 | enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE); |
106 | } | |
107 | ||
108 | static void gic_clockevent_cpu_exit(struct clock_event_device *cd) | |
109 | { | |
110 | disable_percpu_irq(gic_timer_irq); | |
111 | } | |
112 | ||
fc6a6772 EG |
113 | static void gic_update_frequency(void *data) |
114 | { | |
115 | unsigned long rate = (unsigned long)data; | |
116 | ||
117 | clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate); | |
118 | } | |
119 | ||
2dab9093 | 120 | static int gic_starting_cpu(unsigned int cpu) |
e4752dbb | 121 | { |
2dab9093 RC |
122 | gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); |
123 | return 0; | |
e4752dbb AB |
124 | } |
125 | ||
fc6a6772 EG |
126 | static int gic_clk_notifier(struct notifier_block *nb, unsigned long action, |
127 | void *data) | |
128 | { | |
129 | struct clk_notifier_data *cnd = data; | |
130 | ||
7d7de1a6 SS |
131 | if (action == POST_RATE_CHANGE) { |
132 | gic_clocksource_unstable("ref clock rate change"); | |
fc6a6772 | 133 | on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1); |
7d7de1a6 | 134 | } |
fc6a6772 EG |
135 | |
136 | return NOTIFY_OK; | |
137 | } | |
138 | ||
2dab9093 RC |
139 | static int gic_dying_cpu(unsigned int cpu) |
140 | { | |
141 | gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device)); | |
142 | return 0; | |
143 | } | |
e4752dbb | 144 | |
fc6a6772 EG |
145 | static struct notifier_block gic_clk_nb = { |
146 | .notifier_call = gic_clk_notifier, | |
147 | }; | |
148 | ||
e4752dbb AB |
149 | static int gic_clockevent_init(void) |
150 | { | |
f95ac855 EG |
151 | int ret; |
152 | ||
6982530e | 153 | if (!gic_frequency) |
e4752dbb AB |
154 | return -ENXIO; |
155 | ||
f95ac855 | 156 | ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); |
2fd0c93c | 157 | if (ret < 0) { |
3ca5768d | 158 | pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret); |
f95ac855 | 159 | return ret; |
2fd0c93c | 160 | } |
e4752dbb | 161 | |
2dab9093 | 162 | cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, |
73c1b41e TG |
163 | "clockevents/mips/gic/timer:starting", |
164 | gic_starting_cpu, gic_dying_cpu); | |
a331ce63 AB |
165 | return 0; |
166 | } | |
167 | ||
a5a1d1c2 | 168 | static u64 gic_hpt_read(struct clocksource *cs) |
778eeb1b | 169 | { |
dfa762e1 | 170 | return gic_read_count(); |
778eeb1b SH |
171 | } |
172 | ||
173 | static struct clocksource gic_clocksource = { | |
e1bdb22e TG |
174 | .name = "GIC", |
175 | .read = gic_hpt_read, | |
176 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
177 | .vdso_clock_mode = VDSO_CLOCKMODE_GIC, | |
778eeb1b SH |
178 | }; |
179 | ||
7d7de1a6 SS |
180 | static void gic_clocksource_unstable(char *reason) |
181 | { | |
182 | if (gic_clock_unstable) | |
183 | return; | |
184 | ||
185 | gic_clock_unstable = true; | |
186 | ||
187 | pr_info("GIC timer is unstable due to %s\n", reason); | |
188 | ||
189 | clocksource_mark_unstable(&gic_clocksource); | |
190 | } | |
191 | ||
d8152bf8 | 192 | static int __init __gic_clocksource_init(void) |
778eeb1b | 193 | { |
e07127a0 | 194 | unsigned int count_width; |
f95ac855 EG |
195 | int ret; |
196 | ||
778eeb1b | 197 | /* Set clocksource mask. */ |
e07127a0 | 198 | count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; |
5753405e | 199 | count_width >>= __ffs(GIC_CONFIG_COUNTBITS); |
e07127a0 PB |
200 | count_width *= 4; |
201 | count_width += 32; | |
202 | gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); | |
778eeb1b SH |
203 | |
204 | /* Calculate a somewhat reasonable rating value. */ | |
e12aa828 | 205 | gic_clocksource.rating = 200 + gic_frequency / 10000000; |
778eeb1b | 206 | |
f95ac855 EG |
207 | ret = clocksource_register_hz(&gic_clocksource, gic_frequency); |
208 | if (ret < 0) | |
3ca5768d | 209 | pr_warn("Unable to register clocksource\n"); |
d8152bf8 DL |
210 | |
211 | return ret; | |
778eeb1b | 212 | } |
e12aa828 | 213 | |
be5769e2 | 214 | static int __init gic_clocksource_of_init(struct device_node *node) |
e12aa828 | 215 | { |
5b4e8453 | 216 | struct clk *clk; |
fc6a6772 | 217 | int ret; |
5b4e8453 | 218 | |
e07127a0 | 219 | if (!mips_gic_present() || !node->parent || |
d8152bf8 | 220 | !of_device_is_compatible(node->parent, "mti,gic")) { |
3ca5768d | 221 | pr_warn("No DT definition\n"); |
d8152bf8 DL |
222 | return -ENXIO; |
223 | } | |
e12aa828 | 224 | |
5b4e8453 AB |
225 | clk = of_clk_get(node, 0); |
226 | if (!IS_ERR(clk)) { | |
8c3ecd60 CJ |
227 | ret = clk_prepare_enable(clk); |
228 | if (ret < 0) { | |
3ca5768d | 229 | pr_err("Failed to enable clock\n"); |
eb811c73 | 230 | clk_put(clk); |
8c3ecd60 | 231 | return ret; |
eb811c73 EG |
232 | } |
233 | ||
5b4e8453 | 234 | gic_frequency = clk_get_rate(clk); |
5b4e8453 AB |
235 | } else if (of_property_read_u32(node, "clock-frequency", |
236 | &gic_frequency)) { | |
3ca5768d | 237 | pr_err("Frequency not specified\n"); |
ed7158ba | 238 | return -EINVAL; |
e12aa828 AB |
239 | } |
240 | gic_timer_irq = irq_of_parse_and_map(node, 0); | |
241 | if (!gic_timer_irq) { | |
3ca5768d | 242 | pr_err("IRQ not specified\n"); |
ed7158ba | 243 | return -EINVAL; |
e12aa828 AB |
244 | } |
245 | ||
d8152bf8 DL |
246 | ret = __gic_clocksource_init(); |
247 | if (ret) | |
248 | return ret; | |
fc6a6772 EG |
249 | |
250 | ret = gic_clockevent_init(); | |
251 | if (!ret && !IS_ERR(clk)) { | |
252 | if (clk_notifier_register(clk, &gic_clk_nb) < 0) | |
3ca5768d | 253 | pr_warn("Unable to register clock notifier\n"); |
fc6a6772 | 254 | } |
67d4e669 EG |
255 | |
256 | /* And finally start the counter */ | |
e07127a0 | 257 | clear_gic_config(GIC_CONFIG_COUNTSTOP); |
d8152bf8 | 258 | |
48016e78 PB |
259 | /* |
260 | * It's safe to use the MIPS GIC timer as a sched clock source only if | |
261 | * its ticks are stable, which is true on either the platforms with | |
262 | * stable CPU frequency or on the platforms with CM3 and CPU frequency | |
263 | * change performed by the CPC core clocks divider. | |
264 | */ | |
265 | if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) { | |
266 | sched_clock_register(mips_cm_is64 ? | |
267 | gic_read_count_64 : gic_read_count_2x32, | |
268 | 64, gic_frequency); | |
269 | } | |
270 | ||
d8152bf8 | 271 | return 0; |
e12aa828 | 272 | } |
17273395 | 273 | TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer", |
e12aa828 | 274 | gic_clocksource_of_init); |