[mirror_ubuntu-zesty-kernel.git] / drivers / clocksource / mxs_timer.c

/*
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/stmp_device.h>
#include <linux/sched_clock.h>

/*
 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
 * extends the counter to 32 bits.
 *
 * The implementation uses two timers, one for clock_event and
 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
 * uses 0 and 2.
 */

#define MX23_TIMROT_VERSION_OFFSET	0x0a0
#define MX28_TIMROT_VERSION_OFFSET	0x120
#define BP_TIMROT_MAJOR_VERSION		24
#define BV_TIMROT_VERSION_1		0x01
#define BV_TIMROT_VERSION_2		0x02
#define timrot_is_v1()	(timrot_major_version == BV_TIMROT_VERSION_1)

/*
 * There are 4 registers for each timrotv2 instance, and 2 registers
 * for each timrotv1. So address step 0x40 in macros below strides
 * one instance of timrotv2 while two instances of timrotv1.
 *
 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
 * on MX28 while timrot2 on MX23.
 */
/* common between v1 and v2 */
#define HW_TIMROT_ROTCTRL		0x00
#define HW_TIMROT_TIMCTRLn(n)		(0x20 + (n) * 0x40)
/* v1 only */
#define HW_TIMROT_TIMCOUNTn(n)		(0x30 + (n) * 0x40)
/* v2 only */
#define HW_TIMROT_RUNNING_COUNTn(n)	(0x30 + (n) * 0x40)
#define HW_TIMROT_FIXED_COUNTn(n)	(0x40 + (n) * 0x40)

#define BM_TIMROT_TIMCTRLn_RELOAD	(1 << 6)
#define BM_TIMROT_TIMCTRLn_UPDATE	(1 << 7)
#define BM_TIMROT_TIMCTRLn_IRQ_EN	(1 << 14)
#define BM_TIMROT_TIMCTRLn_IRQ		(1 << 15)
#define BP_TIMROT_TIMCTRLn_SELECT	0
#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL		0x8
#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL		0xb
#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS	0xf

static struct clock_event_device mxs_clockevent_device;

static void __iomem *mxs_timrot_base;
static u32 timrot_major_version;

static inline void timrot_irq_disable(void)
{
	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
}

static inline void timrot_irq_enable(void)
{
	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
}

static void timrot_irq_acknowledge(void)
{
	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
		     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
}

static u64 timrotv1_get_cycles(struct clocksource *cs)
{
	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
			& 0xffff0000) >> 16);
}

static int timrotv1_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));

	return 0;
}

static int timrotv2_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));

	return 0;
}

static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	timrot_irq_acknowledge();
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mxs_timer_irq = {
	.name		= "MXS Timer Tick",
	.dev_id		= &mxs_clockevent_device,
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= mxs_timer_interrupt,
};

static void mxs_irq_clear(char *state)
{
	/* Disable interrupt in timer module */
	timrot_irq_disable();

	/* Set event time into the furthest future */
	if (timrot_is_v1())
		__raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	else
		__raw_writel(0xffffffff,
			     mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

	/* Clear pending interrupt */
	timrot_irq_acknowledge();

#ifdef DEBUG
	pr_info("%s: changing mode to %s\n", __func__, state)
#endif /* DEBUG */
}

static int mxs_shutdown(struct clock_event_device *evt)
{
	mxs_irq_clear("shutdown");

	return 0;
}

static int mxs_set_oneshot(struct clock_event_device *evt)
{
	if (clockevent_state_oneshot(evt))
		mxs_irq_clear("oneshot");
	timrot_irq_enable();
	return 0;
}

static struct clock_event_device mxs_clockevent_device = {
	.name			= "mxs_timrot",
	.features		= CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= mxs_shutdown,
	.set_state_oneshot	= mxs_set_oneshot,
	.tick_resume		= mxs_shutdown,
	.set_next_event		= timrotv2_set_next_event,
	.rating			= 200,
};

static int __init mxs_clockevent_init(struct clk *timer_clk)
{
	if (timrot_is_v1())
		mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
	mxs_clockevent_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mxs_clockevent_device,
					clk_get_rate(timer_clk),
					timrot_is_v1() ? 0xf : 0x2,
					timrot_is_v1() ? 0xfffe : 0xfffffffe);

	return 0;
}

static struct clocksource clocksource_mxs = {
	.name		= "mxs_timer",
	.rating		= 200,
	.read		= timrotv1_get_cycles,
	.mask		= CLOCKSOURCE_MASK(16),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static u64 notrace mxs_read_sched_clock_v2(void)
{
	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
}

static int __init mxs_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);

	if (timrot_is_v1())
		clocksource_register_hz(&clocksource_mxs, c);
	else {
		clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
			"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
		sched_clock_register(mxs_read_sched_clock_v2, 32, c);
	}

	return 0;
}

static int __init mxs_timer_init(struct device_node *np)
{
	struct clk *timer_clk;
	int irq, ret;

	mxs_timrot_base = of_iomap(np, 0);
	WARN_ON(!mxs_timrot_base);

	timer_clk = of_clk_get(np, 0);
	if (IS_ERR(timer_clk)) {
		pr_err("%s: failed to get clk\n", __func__);
		return PTR_ERR(timer_clk);
	}

	ret = clk_prepare_enable(timer_clk);
	if (ret)
		return ret;

	/*
	 * Initialize timers to a known state
	 */
	stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);

	/* get timrot version */
	timrot_major_version = __raw_readl(mxs_timrot_base +
			(of_device_is_compatible(np, "fsl,imx23-timrot") ?
						MX23_TIMROT_VERSION_OFFSET :
						MX28_TIMROT_VERSION_OFFSET));
	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;

	/* one for clock_event */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_UPDATE |
			BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));

	/* another for clocksource */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_RELOAD,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));

	/* set clocksource timer fixed count to the maximum */
	if (timrot_is_v1())
		__raw_writel(0xffff,
			mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	else
		__raw_writel(0xffffffff,
			mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

	/* init and register the timer to the framework */
	ret = mxs_clocksource_init(timer_clk);
	if (ret)
		return ret;

	ret = mxs_clockevent_init(timer_clk);
	if (ret)
		return ret;

	/* Make irqs happen */
	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0)
		return -EINVAL;

	return setup_irq(irq, &mxs_timer_irq);
}
CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);
Commit	Line	Data
4e472096 SG	1	/*
	2	* Copyright (C) 2000-2001 Deep Blue Solutions
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	5	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	6	* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
39d1367e	23	#include <linux/err.h>
4e472096 SG	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
eeca6e60	28	#include <linux/of.h>
be35bd2b	29	#include <linux/of_address.h>
eeca6e60	30	#include <linux/of_irq.h>
7a9c39f7	31	#include <linux/stmp_device.h>
38ff87f7	32	#include <linux/sched_clock.h>
4e472096	33
4e472096 SG	34	/*
	35	* There are 2 versions of the timrot on Freescale MXS-based SoCs.
	36	* The v1 on MX23 only gets 16 bits counter, while v2 on MX28
	37	* extends the counter to 32 bits.
	38	*
	39	* The implementation uses two timers, one for clock_event and
	40	* another for clocksource. MX28 uses timrot 0 and 1, while MX23
	41	* uses 0 and 2.
	42	*/
	43
	44	#define MX23_TIMROT_VERSION_OFFSET 0x0a0
	45	#define MX28_TIMROT_VERSION_OFFSET 0x120
	46	#define BP_TIMROT_MAJOR_VERSION 24
	47	#define BV_TIMROT_VERSION_1 0x01
	48	#define BV_TIMROT_VERSION_2 0x02
	49	#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
	50
	51	/*
	52	* There are 4 registers for each timrotv2 instance, and 2 registers
	53	* for each timrotv1. So address step 0x40 in macros below strides
	54	* one instance of timrotv2 while two instances of timrotv1.
	55	*
	56	* As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
	57	* on MX28 while timrot2 on MX23.
	58	*/
	59	/* common between v1 and v2 */
	60	#define HW_TIMROT_ROTCTRL 0x00
	61	#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
	62	/* v1 only */
	63	#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
	64	/* v2 only */
	65	#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
	66	#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
	67
	68	#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
	69	#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
	70	#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
	71	#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
	72	#define BP_TIMROT_TIMCTRLn_SELECT 0
2fb318ff TH	73	#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
	74	#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
	75	#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
4e472096 SG	76
4e472096 SG	77	static struct clock_event_device mxs_clockevent_device;
4e472096	78
be35bd2b	79	static void __iomem *mxs_timrot_base;
4e472096 SG	80	static u32 timrot_major_version;
	81
	82	static inline void timrot_irq_disable(void)
	83	{
7a9c39f7 SG	84	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
7a9c39f7 SG	85	HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
4e472096 SG	86	}
	87
	88	static inline void timrot_irq_enable(void)
	89	{
7a9c39f7 SG	90	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
7a9c39f7 SG	91	HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
4e472096 SG	92	}
	93
	94	static void timrot_irq_acknowledge(void)
	95	{
7a9c39f7 SG	96	__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
7a9c39f7 SG	97	HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
4e472096 SG	98	}
4e472096 SG	99
a5a1d1c2	100	static u64 timrotv1_get_cycles(struct clocksource *cs)
4e472096 SG	101	{
	102	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
	103	& 0xffff0000) >> 16);
	104	}
	105
4e472096 SG	106	static int timrotv1_set_next_event(unsigned long evt,
	107	struct clock_event_device *dev)
	108	{
	109	/* timrot decrements the count */
	110	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
	111
	112	return 0;
	113	}
	114
	115	static int timrotv2_set_next_event(unsigned long evt,
	116	struct clock_event_device *dev)
	117	{
	118	/* timrot decrements the count */
	119	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
	120
	121	return 0;
	122	}
	123
	124	static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
	125	{
	126	struct clock_event_device *evt = dev_id;
	127
	128	timrot_irq_acknowledge();
	129	evt->event_handler(evt);
	130
	131	return IRQ_HANDLED;
	132	}
	133
	134	static struct irqaction mxs_timer_irq = {
	135	.name = "MXS Timer Tick",
	136	.dev_id = &mxs_clockevent_device,
	137	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	138	.handler = mxs_timer_interrupt,
	139	};
	140
eb8703e2	141	static void mxs_irq_clear(char *state)
4e472096 SG	142	{
	143	/* Disable interrupt in timer module */
	144	timrot_irq_disable();
	145
eb8703e2 VK	146	/* Set event time into the furthest future */
	147	if (timrot_is_v1())
	148	__raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	149	else
	150	__raw_writel(0xffffffff,
	151	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
4e472096	152
eb8703e2 VK	153	/* Clear pending interrupt */
eb8703e2 VK	154	timrot_irq_acknowledge();
4e472096 SG	155
4e472096 SG	156	#ifdef DEBUG
eb8703e2	157	pr_info("%s: changing mode to %s\n", __func__, state)
4e472096	158	#endif /* DEBUG */
eb8703e2	159	}
4e472096	160
eb8703e2 VK	161	static int mxs_shutdown(struct clock_event_device *evt)
	162	{
	163	mxs_irq_clear("shutdown");
	164
	165	return 0;
	166	}
	167
	168	static int mxs_set_oneshot(struct clock_event_device *evt)
	169	{
	170	if (clockevent_state_oneshot(evt))
	171	mxs_irq_clear("oneshot");
	172	timrot_irq_enable();
	173	return 0;
4e472096 SG	174	}
	175
	176	static struct clock_event_device mxs_clockevent_device = {
eb8703e2 VK	177	.name = "mxs_timrot",
	178	.features = CLOCK_EVT_FEAT_ONESHOT,
	179	.set_state_shutdown = mxs_shutdown,
	180	.set_state_oneshot = mxs_set_oneshot,
	181	.tick_resume = mxs_shutdown,
	182	.set_next_event = timrotv2_set_next_event,
	183	.rating = 200,
4e472096 SG	184	};
	185
	186	static int __init mxs_clockevent_init(struct clk *timer_clk)
	187	{
838a2ae8	188	if (timrot_is_v1())
4e472096	189	mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
838a2ae8 SG	190	mxs_clockevent_device.cpumask = cpumask_of(0);
838a2ae8 SG	191	clockevents_config_and_register(&mxs_clockevent_device,
93044fa1 TH	192	clk_get_rate(timer_clk),
93044fa1 TH	193	timrot_is_v1() ? 0xf : 0x2,
838a2ae8	194	timrot_is_v1() ? 0xfffe : 0xfffffffe);
4e472096 SG	195
	196	return 0;
	197	}
	198
	199	static struct clocksource clocksource_mxs = {
	200	.name = "mxs_timer",
	201	.rating = 200,
5c61ddcf RK	202	.read = timrotv1_get_cycles,
5c61ddcf RK	203	.mask = CLOCKSOURCE_MASK(16),
4e472096 SG	204	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	205	};
	206
fcfca6ef	207	static u64 notrace mxs_read_sched_clock_v2(void)
67948ada SM	208	{
	209	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
	210	}
	211
4e472096 SG	212	static int __init mxs_clocksource_init(struct clk *timer_clk)
	213	{
	214	unsigned int c = clk_get_rate(timer_clk);
	215
5c61ddcf RK	216	if (timrot_is_v1())
5c61ddcf RK	217	clocksource_register_hz(&clocksource_mxs, c);
67948ada	218	else {
5c61ddcf RK	219	clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
5c61ddcf RK	220	"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
fcfca6ef	221	sched_clock_register(mxs_read_sched_clock_v2, 32, c);
67948ada	222	}
4e472096 SG	223
	224	return 0;
	225	}
	226
e1d2b9f0	227	static int __init mxs_timer_init(struct device_node *np)
4e472096	228	{
50260924	229	struct clk *timer_clk;
e1d2b9f0	230	int irq, ret;
eeca6e60	231
be35bd2b SG	232	mxs_timrot_base = of_iomap(np, 0);
	233	WARN_ON(!mxs_timrot_base);
	234
2efb9504	235	timer_clk = of_clk_get(np, 0);
50260924 SG	236	if (IS_ERR(timer_clk)) {
50260924 SG	237	pr_err("%s: failed to get clk\n", __func__);
e1d2b9f0	238	return PTR_ERR(timer_clk);
39d1367e SG	239	}
39d1367e SG	240
e1d2b9f0 DL	241	ret = clk_prepare_enable(timer_clk);
	242	if (ret)
	243	return ret;
4e472096 SG	244
	245	/*
	246	* Initialize timers to a known state
	247	*/
7a9c39f7	248	stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
4e472096 SG	249
	250	/* get timrot version */
	251	timrot_major_version = __raw_readl(mxs_timrot_base +
220d2f26 SG	252	(of_device_is_compatible(np, "fsl,imx23-timrot") ?
220d2f26 SG	253	MX23_TIMROT_VERSION_OFFSET :
4e472096 SG	254	MX28_TIMROT_VERSION_OFFSET));
	255	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
	256
	257	/* one for clock_event */
	258	__raw_writel((timrot_is_v1() ?
	259	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	260	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	261	BM_TIMROT_TIMCTRLn_UPDATE \|
	262	BM_TIMROT_TIMCTRLn_IRQ_EN,
	263	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	264
	265	/* another for clocksource */
	266	__raw_writel((timrot_is_v1() ?
	267	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	268	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	269	BM_TIMROT_TIMCTRLn_RELOAD,
	270	mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
	271
	272	/* set clocksource timer fixed count to the maximum */
	273	if (timrot_is_v1())
	274	__raw_writel(0xffff,
	275	mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	276	else
	277	__raw_writel(0xffffffff,
	278	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
	279
	280	/* init and register the timer to the framework */
e1d2b9f0 DL	281	ret = mxs_clocksource_init(timer_clk);
	282	if (ret)
	283	return ret;
	284
	285	ret = mxs_clockevent_init(timer_clk);
	286	if (ret)
	287	return ret;
4e472096 SG	288
4e472096 SG	289	/* Make irqs happen */
eeca6e60	290	irq = irq_of_parse_and_map(np, 0);
e1d2b9f0 DL	291	if (irq <= 0)
	292	return -EINVAL;
	293
	294	return setup_irq(irq, &mxs_timer_irq);
4e472096	295	}
177cf6e5	296	CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);