[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / nomadik-mtu.c

/*
 * Copyright (C) 2008 STMicroelectronics
 * Copyright (C) 2010 Alessandro Rubini
 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2, as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include <linux/platform_data/clocksource-nomadik-mtu.h>
#include <asm/mach/time.h>
#include <asm/sched_clock.h>

/*
 * The MTU device hosts four different counters, with 4 set of
 * registers. These are register names.
 */

#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
#define MTU_RIS		0x04	/* Raw interrupt status */
#define MTU_MIS		0x08	/* Masked interrupt status */
#define MTU_ICR		0x0C	/* Interrupt clear register */

/* per-timer registers take 0..3 as argument */
#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */

/* bits for the control register */
#define MTU_CRn_ENA		0x80
#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK	0x0c
#define MTU_CRn_PRESCALE_1		0x00
#define MTU_CRn_PRESCALE_16		0x04
#define MTU_CRn_PRESCALE_256		0x08
#define MTU_CRn_32BITS		0x02
#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/

/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR	0xff0
#define MTU_ITOP	0xff4

#define MTU_PERIPH_ID0	0xfe0
#define MTU_PERIPH_ID1	0xfe4
#define MTU_PERIPH_ID2	0xfe8
#define MTU_PERIPH_ID3	0xfeC

#define MTU_PCELL0	0xff0
#define MTU_PCELL1	0xff4
#define MTU_PCELL2	0xff8
#define MTU_PCELL3	0xffC

static void __iomem *mtu_base;
static bool clkevt_periodic;
static u32 clk_prescale;
static u32 nmdk_cycle;		/* write-once */

#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel.
 */
static u32 notrace nomadik_read_sched_clock(void)
{
	if (unlikely(!mtu_base))
		return 0;

	return -readl(mtu_base + MTU_VAL(0));
}
#endif

/* Clockevent device: use one-shot mode */
static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
{
	writel(1 << 1, mtu_base + MTU_IMSC);
	writel(evt, mtu_base + MTU_LR(1));
	/* Load highest value, enable device, enable interrupts */
	writel(MTU_CRn_ONESHOT | clk_prescale |
	       MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(1));

	return 0;
}

void nmdk_clkevt_reset(void)
{
	if (clkevt_periodic) {
		/* Timer: configure load and background-load, and fire it up */
		writel(nmdk_cycle, mtu_base + MTU_LR(1));
		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));

		writel(MTU_CRn_PERIODIC | clk_prescale |
		       MTU_CRn_32BITS | MTU_CRn_ENA,
		       mtu_base + MTU_CR(1));
		writel(1 << 1, mtu_base + MTU_IMSC);
	} else {
		/* Generate an interrupt to start the clockevent again */
		(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	}
}

static void nmdk_clkevt_mode(enum clock_event_mode mode,
			     struct clock_event_device *dev)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		clkevt_periodic = true;
		nmdk_clkevt_reset();
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		clkevt_periodic = false;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		writel(0, mtu_base + MTU_IMSC);
		/* disable timer */
		writel(0, mtu_base + MTU_CR(1));
		/* load some high default value */
		writel(0xffffffff, mtu_base + MTU_LR(1));
		break;
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device nmdk_clkevt = {
	.name		= "mtu_1",
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.rating		= 200,
	.set_mode	= nmdk_clkevt_mode,
	.set_next_event	= nmdk_clkevt_next,
};

/*
 * IRQ Handler for timer 1 of the MTU block.
 */
static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = dev_id;

	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
	evdev->event_handler(evdev);
	return IRQ_HANDLED;
}

static struct irqaction nmdk_timer_irq = {
	.name		= "Nomadik Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER,
	.handler	= nmdk_timer_interrupt,
	.dev_id		= &nmdk_clkevt,
};

void nmdk_clksrc_reset(void)
{
	/* Disable */
	writel(0, mtu_base + MTU_CR(0));

	/* ClockSource: configure load and background-load, and fire it up */
	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));

	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(0));
}

void __init nmdk_timer_init(void __iomem *base, int irq)
{
	unsigned long rate;
	struct clk *clk0, *pclk0;

	mtu_base = base;

	pclk0 = clk_get_sys("mtu0", "apb_pclk");
	BUG_ON(IS_ERR(pclk0));
	BUG_ON(clk_prepare(pclk0) < 0);
	BUG_ON(clk_enable(pclk0) < 0);

	clk0 = clk_get_sys("mtu0", NULL);
	BUG_ON(IS_ERR(clk0));
	BUG_ON(clk_prepare(clk0) < 0);
	BUG_ON(clk_enable(clk0) < 0);

	/*
	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	 * for ux500.
	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	 * with 16 gives too low timer resolution.
	 */
	rate = clk_get_rate(clk0);
	if (rate > 32000000) {
		rate /= 16;
		clk_prescale = MTU_CRn_PRESCALE_16;
	} else {
		clk_prescale = MTU_CRn_PRESCALE_1;
	}

	/* Cycles for periodic mode */
	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);


	/* Timer 0 is the free running clocksource */
	nmdk_clksrc_reset();

	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
			rate, 200, 32, clocksource_mmio_readl_down))
		pr_err("timer: failed to initialize clock source %s\n",
		       "mtu_0");

#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
	setup_sched_clock(nomadik_read_sched_clock, 32, rate);
#endif

	/* Timer 1 is used for events, register irq and clockevents */
	setup_irq(irq, &nmdk_timer_irq);
	nmdk_clkevt.cpumask = cpumask_of(0);
	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
}
Commit	Line	Data
28ad94ec	1	/*
28ad94ec	2	* Copyright (C) 2008 STMicroelectronics
b102c01f	3	* Copyright (C) 2010 Alessandro Rubini
8fbb97a2	4	* Copyright (C) 2010 Linus Walleij for ST-Ericsson
28ad94ec AR	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2, as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/io.h>
	14	#include <linux/clockchips.h>
694e33a7	15	#include <linux/clocksource.h>
ba327b1e	16	#include <linux/clk.h>
28ad94ec	17	#include <linux/jiffies.h>
ba327b1e	18	#include <linux/err.h>
694e33a7	19	#include <linux/platform_data/clocksource-nomadik-mtu.h>
28ad94ec	20	#include <asm/mach/time.h>
ec05aa13	21	#include <asm/sched_clock.h>
28ad94ec	22
05387a9f JA	23	/*
	24	* The MTU device hosts four different counters, with 4 set of
	25	* registers. These are register names.
	26	*/
	27
	28	#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
	29	#define MTU_RIS 0x04 /* Raw interrupt status */
	30	#define MTU_MIS 0x08 /* Masked interrupt status */
	31	#define MTU_ICR 0x0C /* Interrupt clear register */
	32
	33	/* per-timer registers take 0..3 as argument */
	34	#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
	35	#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
	36	#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
	37	#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
	38
	39	/* bits for the control register */
	40	#define MTU_CRn_ENA 0x80
	41	#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
	42	#define MTU_CRn_PRESCALE_MASK 0x0c
	43	#define MTU_CRn_PRESCALE_1 0x00
	44	#define MTU_CRn_PRESCALE_16 0x04
	45	#define MTU_CRn_PRESCALE_256 0x08
	46	#define MTU_CRn_32BITS 0x02
	47	#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
	48
	49	/* Other registers are usual amba/primecell registers, currently not used */
	50	#define MTU_ITCR 0xff0
	51	#define MTU_ITOP 0xff4
	52
	53	#define MTU_PERIPH_ID0 0xfe0
	54	#define MTU_PERIPH_ID1 0xfe4
	55	#define MTU_PERIPH_ID2 0xfe8
	56	#define MTU_PERIPH_ID3 0xfeC
	57
	58	#define MTU_PCELL0 0xff0
	59	#define MTU_PCELL1 0xff4
	60	#define MTU_PCELL2 0xff8
	61	#define MTU_PCELL3 0xffC
28ad94ec	62
b9576623	63	static void __iomem *mtu_base;
2f73a068 JA	64	static bool clkevt_periodic;
	65	static u32 clk_prescale;
	66	static u32 nmdk_cycle; /* write-once */
	67
cba13830	68	#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
2a847513 LW	69	/*
	70	* Override the global weak sched_clock symbol with this
	71	* local implementation which uses the clocksource to get some
8fbb97a2	72	* better resolution when scheduling the kernel.
2a847513	73	*/
2f0778af	74	static u32 notrace nomadik_read_sched_clock(void)
2a847513	75	{
8fbb97a2 LW	76	if (unlikely(!mtu_base))
	77	return 0;
	78
2f0778af	79	return -readl(mtu_base + MTU_VAL(0));
2a847513	80	}
cba13830	81	#endif
2f73a068	82
b102c01f	83	/* Clockevent device: use one-shot mode */
2f73a068 JA	84	static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
	85	{
	86	writel(1 << 1, mtu_base + MTU_IMSC);
	87	writel(evt, mtu_base + MTU_LR(1));
	88	/* Load highest value, enable device, enable interrupts */
	89	writel(MTU_CRn_ONESHOT \| clk_prescale \|
	90	MTU_CRn_32BITS \| MTU_CRn_ENA,
	91	mtu_base + MTU_CR(1));
	92
	93	return 0;
	94	}
	95
05387a9f	96	void nmdk_clkevt_reset(void)
2f73a068 JA	97	{
2f73a068 JA	98	if (clkevt_periodic) {
2f73a068 JA	99	/* Timer: configure load and background-load, and fire it up */
	100	writel(nmdk_cycle, mtu_base + MTU_LR(1));
	101	writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
	102
	103	writel(MTU_CRn_PERIODIC \| clk_prescale \|
	104	MTU_CRn_32BITS \| MTU_CRn_ENA,
	105	mtu_base + MTU_CR(1));
	106	writel(1 << 1, mtu_base + MTU_IMSC);
	107	} else {
	108	/* Generate an interrupt to start the clockevent again */
	109	(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	110	}
	111	}
	112
28ad94ec AR	113	static void nmdk_clkevt_mode(enum clock_event_mode mode,
	114	struct clock_event_device *dev)
	115	{
28ad94ec AR	116	switch (mode) {
28ad94ec AR	117	case CLOCK_EVT_MODE_PERIODIC:
2f73a068 JA	118	clkevt_periodic = true;
2f73a068 JA	119	nmdk_clkevt_reset();
28ad94ec AR	120	break;
28ad94ec AR	121	case CLOCK_EVT_MODE_ONESHOT:
2f73a068	122	clkevt_periodic = false;
b102c01f	123	break;
28ad94ec AR	124	case CLOCK_EVT_MODE_SHUTDOWN:
28ad94ec AR	125	case CLOCK_EVT_MODE_UNUSED:
b102c01f	126	writel(0, mtu_base + MTU_IMSC);
2917947a	127	/* disable timer */
2f73a068	128	writel(0, mtu_base + MTU_CR(1));
2917947a LW	129	/* load some high default value */
2917947a LW	130	writel(0xffffffff, mtu_base + MTU_LR(1));
28ad94ec AR	131	break;
	132	case CLOCK_EVT_MODE_RESUME:
	133	break;
	134	}
	135	}
	136
	137	static struct clock_event_device nmdk_clkevt = {
b102c01f	138	.name = "mtu_1",
2f73a068	139	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
b102c01f	140	.rating = 200,
28ad94ec	141	.set_mode = nmdk_clkevt_mode,
b102c01f	142	.set_next_event = nmdk_clkevt_next,
28ad94ec AR	143	};
	144
	145	/*
b102c01f	146	* IRQ Handler for timer 1 of the MTU block.
28ad94ec AR	147	*/
	148	static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
	149	{
b102c01f	150	struct clock_event_device *evdev = dev_id;
28ad94ec	151
b102c01f AR	152	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
b102c01f AR	153	evdev->event_handler(evdev);
28ad94ec AR	154	return IRQ_HANDLED;
	155	}
	156
28ad94ec AR	157	static struct irqaction nmdk_timer_irq = {
	158	.name = "Nomadik Timer Tick",
	159	.flags = IRQF_DISABLED \| IRQF_TIMER,
	160	.handler = nmdk_timer_interrupt,
b102c01f	161	.dev_id = &nmdk_clkevt,
28ad94ec AR	162	};
28ad94ec AR	163
05387a9f	164	void nmdk_clksrc_reset(void)
2f73a068 JA	165	{
	166	/* Disable */
	167	writel(0, mtu_base + MTU_CR(0));
	168
	169	/* ClockSource: configure load and background-load, and fire it up */
	170	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	171	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
	172
	173	writel(clk_prescale \| MTU_CRn_32BITS \| MTU_CRn_ENA,
	174	mtu_base + MTU_CR(0));
	175	}
	176
0813069d	177	void __init nmdk_timer_init(void __iomem *base, int irq)
28ad94ec	178	{
28ad94ec	179	unsigned long rate;
16defa66	180	struct clk clk0, pclk0;
ba327b1e	181
b9576623	182	mtu_base = base;
16defa66 UH	183
	184	pclk0 = clk_get_sys("mtu0", "apb_pclk");
	185	BUG_ON(IS_ERR(pclk0));
	186	BUG_ON(clk_prepare(pclk0) < 0);
	187	BUG_ON(clk_enable(pclk0) < 0);
	188
ba327b1e LW	189	clk0 = clk_get_sys("mtu0", NULL);
ba327b1e LW	190	BUG_ON(IS_ERR(clk0));
d3e8b756 LW	191	BUG_ON(clk_prepare(clk0) < 0);
d3e8b756 LW	192	BUG_ON(clk_enable(clk0) < 0);
b102c01f AR	193
b102c01f AR	194	/*
a0719f52 LW	195	* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	196	* for ux500.
	197	* Use a divide-by-16 counter if the tick rate is more than 32MHz.
	198	* At 32 MHz, the timer (with 32 bit counter) can be programmed
	199	* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	200	* with 16 gives too low timer resolution.
b102c01f	201	*/
ba327b1e	202	rate = clk_get_rate(clk0);
a0719f52	203	if (rate > 32000000) {
b102c01f	204	rate /= 16;
2f73a068	205	clk_prescale = MTU_CRn_PRESCALE_16;
b102c01f	206	} else {
2f73a068	207	clk_prescale = MTU_CRn_PRESCALE_1;
b102c01f	208	}
28ad94ec	209
21366831 LW	210	/* Cycles for periodic mode */
21366831 LW	211	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
2f73a068 JA	212
2f73a068 JA	213
b102c01f	214	/* Timer 0 is the free running clocksource */
2f73a068	215	nmdk_clksrc_reset();
28ad94ec	216
bfe45e0b RK	217	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
bfe45e0b RK	218	rate, 200, 32, clocksource_mmio_readl_down))
b102c01f	219	pr_err("timer: failed to initialize clock source %s\n",
bfe45e0b	220	"mtu_0");
2f0778af	221
cba13830	222	#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
2f0778af	223	setup_sched_clock(nomadik_read_sched_clock, 32, rate);
cba13830	224	#endif
2f0778af	225
a3b86a6d	226	/* Timer 1 is used for events, register irq and clockevents */
0813069d	227	setup_irq(irq, &nmdk_timer_irq);
a3b86a6d LW	228	nmdk_clkevt.cpumask = cpumask_of(0);
a3b86a6d LW	229	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
28ad94ec	230	}