[mirror_ubuntu-zesty-kernel.git] / drivers / clocksource / nomadik-mtu.c

/*
 * Copyright (C) 2008 STMicroelectronics
 * Copyright (C) 2010 Alessandro Rubini
 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2, as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/platform_data/clocksource-nomadik-mtu.h>
#include <asm/mach/time.h>
#include <asm/sched_clock.h>

/*
 * The MTU device hosts four different counters, with 4 set of
 * registers. These are register names.
 */

#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
#define MTU_RIS		0x04	/* Raw interrupt status */
#define MTU_MIS		0x08	/* Masked interrupt status */
#define MTU_ICR		0x0C	/* Interrupt clear register */

/* per-timer registers take 0..3 as argument */
#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */

/* bits for the control register */
#define MTU_CRn_ENA		0x80
#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK	0x0c
#define MTU_CRn_PRESCALE_1		0x00
#define MTU_CRn_PRESCALE_16		0x04
#define MTU_CRn_PRESCALE_256		0x08
#define MTU_CRn_32BITS		0x02
#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/

/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR	0xff0
#define MTU_ITOP	0xff4

#define MTU_PERIPH_ID0	0xfe0
#define MTU_PERIPH_ID1	0xfe4
#define MTU_PERIPH_ID2	0xfe8
#define MTU_PERIPH_ID3	0xfeC

#define MTU_PCELL0	0xff0
#define MTU_PCELL1	0xff4
#define MTU_PCELL2	0xff8
#define MTU_PCELL3	0xffC

static void __iomem *mtu_base;
static bool clkevt_periodic;
static u32 clk_prescale;
static u32 nmdk_cycle;		/* write-once */
static struct delay_timer mtu_delay_timer;

#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel.
 */
static u32 notrace nomadik_read_sched_clock(void)
{
	if (unlikely(!mtu_base))
		return 0;

	return -readl(mtu_base + MTU_VAL(0));
}
#endif

static unsigned long nmdk_timer_read_current_timer(void)
{
	return ~readl_relaxed(mtu_base + MTU_VAL(0));
}

/* Clockevent device: use one-shot mode */
static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
{
	writel(1 << 1, mtu_base + MTU_IMSC);
	writel(evt, mtu_base + MTU_LR(1));
	/* Load highest value, enable device, enable interrupts */
	writel(MTU_CRn_ONESHOT | clk_prescale |
	       MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(1));

	return 0;
}

void nmdk_clkevt_reset(void)
{
	if (clkevt_periodic) {
		/* Timer: configure load and background-load, and fire it up */
		writel(nmdk_cycle, mtu_base + MTU_LR(1));
		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));

		writel(MTU_CRn_PERIODIC | clk_prescale |
		       MTU_CRn_32BITS | MTU_CRn_ENA,
		       mtu_base + MTU_CR(1));
		writel(1 << 1, mtu_base + MTU_IMSC);
	} else {
		/* Generate an interrupt to start the clockevent again */
		(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	}
}

static void nmdk_clkevt_mode(enum clock_event_mode mode,
			     struct clock_event_device *dev)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		clkevt_periodic = true;
		nmdk_clkevt_reset();
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		clkevt_periodic = false;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		writel(0, mtu_base + MTU_IMSC);
		/* disable timer */
		writel(0, mtu_base + MTU_CR(1));
		/* load some high default value */
		writel(0xffffffff, mtu_base + MTU_LR(1));
		break;
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

void nmdk_clksrc_reset(void)
{
	/* Disable */
	writel(0, mtu_base + MTU_CR(0));

	/* ClockSource: configure load and background-load, and fire it up */
	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));

	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(0));
}

static void nmdk_clkevt_resume(struct clock_event_device *cedev)
{
	nmdk_clkevt_reset();
	nmdk_clksrc_reset();
}

static struct clock_event_device nmdk_clkevt = {
	.name		= "mtu_1",
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.rating		= 200,
	.set_mode	= nmdk_clkevt_mode,
	.set_next_event	= nmdk_clkevt_next,
	.resume		= nmdk_clkevt_resume,
};

/*
 * IRQ Handler for timer 1 of the MTU block.
 */
static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = dev_id;

	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
	evdev->event_handler(evdev);
	return IRQ_HANDLED;
}

static struct irqaction nmdk_timer_irq = {
	.name		= "Nomadik Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER,
	.handler	= nmdk_timer_interrupt,
	.dev_id		= &nmdk_clkevt,
};

void __init nmdk_timer_init(void __iomem *base, int irq)
{
	unsigned long rate;
	struct clk *clk0, *pclk0;

	mtu_base = base;

	pclk0 = clk_get_sys("mtu0", "apb_pclk");
	BUG_ON(IS_ERR(pclk0));
	BUG_ON(clk_prepare(pclk0) < 0);
	BUG_ON(clk_enable(pclk0) < 0);

	clk0 = clk_get_sys("mtu0", NULL);
	BUG_ON(IS_ERR(clk0));
	BUG_ON(clk_prepare(clk0) < 0);
	BUG_ON(clk_enable(clk0) < 0);

	/*
	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	 * for ux500.
	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	 * with 16 gives too low timer resolution.
	 */
	rate = clk_get_rate(clk0);
	if (rate > 32000000) {
		rate /= 16;
		clk_prescale = MTU_CRn_PRESCALE_16;
	} else {
		clk_prescale = MTU_CRn_PRESCALE_1;
	}

	/* Cycles for periodic mode */
	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);


	/* Timer 0 is the free running clocksource */
	nmdk_clksrc_reset();

	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
			rate, 200, 32, clocksource_mmio_readl_down))
		pr_err("timer: failed to initialize clock source %s\n",
		       "mtu_0");

#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
	setup_sched_clock(nomadik_read_sched_clock, 32, rate);
#endif

	/* Timer 1 is used for events, register irq and clockevents */
	setup_irq(irq, &nmdk_timer_irq);
	nmdk_clkevt.cpumask = cpumask_of(0);
	nmdk_clkevt.irq = irq;
	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);

	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	mtu_delay_timer.freq = rate;
	register_current_timer_delay(&mtu_delay_timer);
}
Commit	Line	Data
28ad94ec	1	/*
28ad94ec	2	* Copyright (C) 2008 STMicroelectronics
b102c01f	3	* Copyright (C) 2010 Alessandro Rubini
8fbb97a2	4	* Copyright (C) 2010 Linus Walleij for ST-Ericsson
28ad94ec AR	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2, as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/io.h>
	14	#include <linux/clockchips.h>
694e33a7	15	#include <linux/clocksource.h>
ba327b1e	16	#include <linux/clk.h>
28ad94ec	17	#include <linux/jiffies.h>
6f179b72	18	#include <linux/delay.h>
ba327b1e	19	#include <linux/err.h>
694e33a7	20	#include <linux/platform_data/clocksource-nomadik-mtu.h>
28ad94ec	21	#include <asm/mach/time.h>
ec05aa13	22	#include <asm/sched_clock.h>
28ad94ec	23
05387a9f JA	24	/*
	25	* The MTU device hosts four different counters, with 4 set of
	26	* registers. These are register names.
	27	*/
	28
	29	#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
	30	#define MTU_RIS 0x04 /* Raw interrupt status */
	31	#define MTU_MIS 0x08 /* Masked interrupt status */
	32	#define MTU_ICR 0x0C /* Interrupt clear register */
	33
	34	/* per-timer registers take 0..3 as argument */
	35	#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
	36	#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
	37	#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
	38	#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
	39
	40	/* bits for the control register */
	41	#define MTU_CRn_ENA 0x80
	42	#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
	43	#define MTU_CRn_PRESCALE_MASK 0x0c
	44	#define MTU_CRn_PRESCALE_1 0x00
	45	#define MTU_CRn_PRESCALE_16 0x04
	46	#define MTU_CRn_PRESCALE_256 0x08
	47	#define MTU_CRn_32BITS 0x02
	48	#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
	49
	50	/* Other registers are usual amba/primecell registers, currently not used */
	51	#define MTU_ITCR 0xff0
	52	#define MTU_ITOP 0xff4
	53
	54	#define MTU_PERIPH_ID0 0xfe0
	55	#define MTU_PERIPH_ID1 0xfe4
	56	#define MTU_PERIPH_ID2 0xfe8
	57	#define MTU_PERIPH_ID3 0xfeC
	58
	59	#define MTU_PCELL0 0xff0
	60	#define MTU_PCELL1 0xff4
	61	#define MTU_PCELL2 0xff8
	62	#define MTU_PCELL3 0xffC
28ad94ec	63
b9576623	64	static void __iomem *mtu_base;
2f73a068 JA	65	static bool clkevt_periodic;
	66	static u32 clk_prescale;
	67	static u32 nmdk_cycle; /* write-once */
6f179b72	68	static struct delay_timer mtu_delay_timer;
2f73a068	69
cba13830	70	#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
2a847513 LW	71	/*
	72	* Override the global weak sched_clock symbol with this
	73	* local implementation which uses the clocksource to get some
8fbb97a2	74	* better resolution when scheduling the kernel.
2a847513	75	*/
2f0778af	76	static u32 notrace nomadik_read_sched_clock(void)
2a847513	77	{
8fbb97a2 LW	78	if (unlikely(!mtu_base))
	79	return 0;
	80
2f0778af	81	return -readl(mtu_base + MTU_VAL(0));
2a847513	82	}
cba13830	83	#endif
2f73a068	84
6f179b72 FB	85	static unsigned long nmdk_timer_read_current_timer(void)
	86	{
	87	return ~readl_relaxed(mtu_base + MTU_VAL(0));
	88	}
	89
b102c01f	90	/* Clockevent device: use one-shot mode */
2f73a068 JA	91	static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
	92	{
	93	writel(1 << 1, mtu_base + MTU_IMSC);
	94	writel(evt, mtu_base + MTU_LR(1));
	95	/* Load highest value, enable device, enable interrupts */
	96	writel(MTU_CRn_ONESHOT \| clk_prescale \|
	97	MTU_CRn_32BITS \| MTU_CRn_ENA,
	98	mtu_base + MTU_CR(1));
	99
	100	return 0;
	101	}
	102
05387a9f	103	void nmdk_clkevt_reset(void)
2f73a068 JA	104	{
2f73a068 JA	105	if (clkevt_periodic) {
2f73a068 JA	106	/* Timer: configure load and background-load, and fire it up */
	107	writel(nmdk_cycle, mtu_base + MTU_LR(1));
	108	writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
	109
	110	writel(MTU_CRn_PERIODIC \| clk_prescale \|
	111	MTU_CRn_32BITS \| MTU_CRn_ENA,
	112	mtu_base + MTU_CR(1));
	113	writel(1 << 1, mtu_base + MTU_IMSC);
	114	} else {
	115	/* Generate an interrupt to start the clockevent again */
	116	(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	117	}
	118	}
	119
28ad94ec AR	120	static void nmdk_clkevt_mode(enum clock_event_mode mode,
	121	struct clock_event_device *dev)
	122	{
28ad94ec AR	123	switch (mode) {
28ad94ec AR	124	case CLOCK_EVT_MODE_PERIODIC:
2f73a068 JA	125	clkevt_periodic = true;
2f73a068 JA	126	nmdk_clkevt_reset();
28ad94ec AR	127	break;
28ad94ec AR	128	case CLOCK_EVT_MODE_ONESHOT:
2f73a068	129	clkevt_periodic = false;
b102c01f	130	break;
28ad94ec AR	131	case CLOCK_EVT_MODE_SHUTDOWN:
28ad94ec AR	132	case CLOCK_EVT_MODE_UNUSED:
b102c01f	133	writel(0, mtu_base + MTU_IMSC);
2917947a	134	/* disable timer */
2f73a068	135	writel(0, mtu_base + MTU_CR(1));
2917947a LW	136	/* load some high default value */
2917947a LW	137	writel(0xffffffff, mtu_base + MTU_LR(1));
28ad94ec AR	138	break;
	139	case CLOCK_EVT_MODE_RESUME:
	140	break;
	141	}
	142	}
	143
8726e96f SW	144	void nmdk_clksrc_reset(void)
	145	{
	146	/* Disable */
	147	writel(0, mtu_base + MTU_CR(0));
	148
	149	/* ClockSource: configure load and background-load, and fire it up */
	150	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	151	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
	152
	153	writel(clk_prescale \| MTU_CRn_32BITS \| MTU_CRn_ENA,
	154	mtu_base + MTU_CR(0));
	155	}
	156
	157	static void nmdk_clkevt_resume(struct clock_event_device *cedev)
	158	{
	159	nmdk_clkevt_reset();
	160	nmdk_clksrc_reset();
	161	}
	162
28ad94ec	163	static struct clock_event_device nmdk_clkevt = {
b102c01f	164	.name = "mtu_1",
2f73a068	165	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
b102c01f	166	.rating = 200,
28ad94ec	167	.set_mode = nmdk_clkevt_mode,
b102c01f	168	.set_next_event = nmdk_clkevt_next,
8726e96f	169	.resume = nmdk_clkevt_resume,
28ad94ec AR	170	};
	171
	172	/*
b102c01f	173	* IRQ Handler for timer 1 of the MTU block.
28ad94ec AR	174	*/
	175	static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
	176	{
b102c01f	177	struct clock_event_device *evdev = dev_id;
28ad94ec	178
b102c01f AR	179	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
b102c01f AR	180	evdev->event_handler(evdev);
28ad94ec AR	181	return IRQ_HANDLED;
	182	}
	183
28ad94ec AR	184	static struct irqaction nmdk_timer_irq = {
	185	.name = "Nomadik Timer Tick",
	186	.flags = IRQF_DISABLED \| IRQF_TIMER,
	187	.handler = nmdk_timer_interrupt,
b102c01f	188	.dev_id = &nmdk_clkevt,
28ad94ec AR	189	};
28ad94ec AR	190
0813069d	191	void __init nmdk_timer_init(void __iomem *base, int irq)
28ad94ec	192	{
28ad94ec	193	unsigned long rate;
16defa66	194	struct clk clk0, pclk0;
ba327b1e	195
b9576623	196	mtu_base = base;
16defa66 UH	197
	198	pclk0 = clk_get_sys("mtu0", "apb_pclk");
	199	BUG_ON(IS_ERR(pclk0));
	200	BUG_ON(clk_prepare(pclk0) < 0);
	201	BUG_ON(clk_enable(pclk0) < 0);
	202
ba327b1e LW	203	clk0 = clk_get_sys("mtu0", NULL);
ba327b1e LW	204	BUG_ON(IS_ERR(clk0));
d3e8b756 LW	205	BUG_ON(clk_prepare(clk0) < 0);
d3e8b756 LW	206	BUG_ON(clk_enable(clk0) < 0);
b102c01f AR	207
b102c01f AR	208	/*
a0719f52 LW	209	* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	210	* for ux500.
	211	* Use a divide-by-16 counter if the tick rate is more than 32MHz.
	212	* At 32 MHz, the timer (with 32 bit counter) can be programmed
	213	* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	214	* with 16 gives too low timer resolution.
b102c01f	215	*/
ba327b1e	216	rate = clk_get_rate(clk0);
a0719f52	217	if (rate > 32000000) {
b102c01f	218	rate /= 16;
2f73a068	219	clk_prescale = MTU_CRn_PRESCALE_16;
b102c01f	220	} else {
2f73a068	221	clk_prescale = MTU_CRn_PRESCALE_1;
b102c01f	222	}
28ad94ec	223
21366831 LW	224	/* Cycles for periodic mode */
21366831 LW	225	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
2f73a068 JA	226
2f73a068 JA	227
b102c01f	228	/* Timer 0 is the free running clocksource */
2f73a068	229	nmdk_clksrc_reset();
28ad94ec	230
bfe45e0b RK	231	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
bfe45e0b RK	232	rate, 200, 32, clocksource_mmio_readl_down))
b102c01f	233	pr_err("timer: failed to initialize clock source %s\n",
bfe45e0b	234	"mtu_0");
2f0778af	235
cba13830	236	#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
2f0778af	237	setup_sched_clock(nomadik_read_sched_clock, 32, rate);
cba13830	238	#endif
2f0778af	239
a3b86a6d	240	/* Timer 1 is used for events, register irq and clockevents */
0813069d	241	setup_irq(irq, &nmdk_timer_irq);
a3b86a6d	242	nmdk_clkevt.cpumask = cpumask_of(0);
00f4e13c	243	nmdk_clkevt.irq = irq;
a3b86a6d	244	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
6f179b72 FB	245
	246	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	247	mtu_delay_timer.freq = rate;
	248	register_current_timer_delay(&mtu_delay_timer);
28ad94ec	249	}