[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / nomadik-mtu.c

/*
 * Copyright (C) 2008 STMicroelectronics
 * Copyright (C) 2010 Alessandro Rubini
 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2, as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/platform_data/clocksource-nomadik-mtu.h>
#include <linux/sched_clock.h>
#include <asm/mach/time.h>

/*
 * The MTU device hosts four different counters, with 4 set of
 * registers. These are register names.
 */

#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
#define MTU_RIS		0x04	/* Raw interrupt status */
#define MTU_MIS		0x08	/* Masked interrupt status */
#define MTU_ICR		0x0C	/* Interrupt clear register */

/* per-timer registers take 0..3 as argument */
#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */

/* bits for the control register */
#define MTU_CRn_ENA		0x80
#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK	0x0c
#define MTU_CRn_PRESCALE_1		0x00
#define MTU_CRn_PRESCALE_16		0x04
#define MTU_CRn_PRESCALE_256		0x08
#define MTU_CRn_32BITS		0x02
#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/

/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR	0xff0
#define MTU_ITOP	0xff4

#define MTU_PERIPH_ID0	0xfe0
#define MTU_PERIPH_ID1	0xfe4
#define MTU_PERIPH_ID2	0xfe8
#define MTU_PERIPH_ID3	0xfeC

#define MTU_PCELL0	0xff0
#define MTU_PCELL1	0xff4
#define MTU_PCELL2	0xff8
#define MTU_PCELL3	0xffC

static void __iomem *mtu_base;
static bool clkevt_periodic;
static u32 clk_prescale;
static u32 nmdk_cycle;		/* write-once */
static struct delay_timer mtu_delay_timer;

#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel.
 */
static u64 notrace nomadik_read_sched_clock(void)
{
	if (unlikely(!mtu_base))
		return 0;

	return -readl(mtu_base + MTU_VAL(0));
}
#endif

static unsigned long nmdk_timer_read_current_timer(void)
{
	return ~readl_relaxed(mtu_base + MTU_VAL(0));
}

/* Clockevent device: use one-shot mode */
static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
{
	writel(1 << 1, mtu_base + MTU_IMSC);
	writel(evt, mtu_base + MTU_LR(1));
	/* Load highest value, enable device, enable interrupts */
	writel(MTU_CRn_ONESHOT | clk_prescale |
	       MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(1));

	return 0;
}

void nmdk_clkevt_reset(void)
{
	if (clkevt_periodic) {
		/* Timer: configure load and background-load, and fire it up */
		writel(nmdk_cycle, mtu_base + MTU_LR(1));
		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));

		writel(MTU_CRn_PERIODIC | clk_prescale |
		       MTU_CRn_32BITS | MTU_CRn_ENA,
		       mtu_base + MTU_CR(1));
		writel(1 << 1, mtu_base + MTU_IMSC);
	} else {
		/* Generate an interrupt to start the clockevent again */
		(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	}
}

static void nmdk_clkevt_mode(enum clock_event_mode mode,
			     struct clock_event_device *dev)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		clkevt_periodic = true;
		nmdk_clkevt_reset();
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		clkevt_periodic = false;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		writel(0, mtu_base + MTU_IMSC);
		/* disable timer */
		writel(0, mtu_base + MTU_CR(1));
		/* load some high default value */
		writel(0xffffffff, mtu_base + MTU_LR(1));
		break;
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

void nmdk_clksrc_reset(void)
{
	/* Disable */
	writel(0, mtu_base + MTU_CR(0));

	/* ClockSource: configure load and background-load, and fire it up */
	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));

	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(0));
}

static void nmdk_clkevt_resume(struct clock_event_device *cedev)
{
	nmdk_clkevt_reset();
	nmdk_clksrc_reset();
}

static struct clock_event_device nmdk_clkevt = {
	.name		= "mtu_1",
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC |
	                  CLOCK_EVT_FEAT_DYNIRQ,
	.rating		= 200,
	.set_mode	= nmdk_clkevt_mode,
	.set_next_event	= nmdk_clkevt_next,
	.resume		= nmdk_clkevt_resume,
};

/*
 * IRQ Handler for timer 1 of the MTU block.
 */
static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = dev_id;

	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
	evdev->event_handler(evdev);
	return IRQ_HANDLED;
}

static struct irqaction nmdk_timer_irq = {
	.name		= "Nomadik Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER,
	.handler	= nmdk_timer_interrupt,
	.dev_id		= &nmdk_clkevt,
};

static void __init __nmdk_timer_init(void __iomem *base, int irq,
				     struct clk *pclk, struct clk *clk)
{
	unsigned long rate;

	mtu_base = base;

	BUG_ON(clk_prepare_enable(pclk));
	BUG_ON(clk_prepare_enable(clk));

	/*
	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	 * for ux500.
	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	 * with 16 gives too low timer resolution.
	 */
	rate = clk_get_rate(clk);
	if (rate > 32000000) {
		rate /= 16;
		clk_prescale = MTU_CRn_PRESCALE_16;
	} else {
		clk_prescale = MTU_CRn_PRESCALE_1;
	}

	/* Cycles for periodic mode */
	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);


	/* Timer 0 is the free running clocksource */
	nmdk_clksrc_reset();

	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
			rate, 200, 32, clocksource_mmio_readl_down))
		pr_err("timer: failed to initialize clock source %s\n",
		       "mtu_0");

#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
	sched_clock_register(nomadik_read_sched_clock, 32, rate);
#endif

	/* Timer 1 is used for events, register irq and clockevents */
	setup_irq(irq, &nmdk_timer_irq);
	nmdk_clkevt.cpumask = cpumask_of(0);
	nmdk_clkevt.irq = irq;
	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);

	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	mtu_delay_timer.freq = rate;
	register_current_timer_delay(&mtu_delay_timer);
}

void __init nmdk_timer_init(void __iomem *base, int irq)
{
	struct clk *clk0, *pclk0;

	pclk0 = clk_get_sys("mtu0", "apb_pclk");
	BUG_ON(IS_ERR(pclk0));
	clk0 = clk_get_sys("mtu0", NULL);
	BUG_ON(IS_ERR(clk0));

	__nmdk_timer_init(base, irq, pclk0, clk0);
}

static void __init nmdk_timer_of_init(struct device_node *node)
{
	struct clk *pclk;
	struct clk *clk;
	void __iomem *base;
	int irq;

	base = of_iomap(node, 0);
	if (!base)
		panic("Can't remap registers");

	pclk = of_clk_get_by_name(node, "apb_pclk");
	if (IS_ERR(pclk))
		panic("could not get apb_pclk");

	clk = of_clk_get_by_name(node, "timclk");
	if (IS_ERR(clk))
		panic("could not get timclk");

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0)
		panic("Can't parse IRQ");

	__nmdk_timer_init(base, irq, pclk, clk);
}
CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
		       nmdk_timer_of_init);
Commit	Line	Data
28ad94ec	1	/*
28ad94ec	2	* Copyright (C) 2008 STMicroelectronics
b102c01f	3	* Copyright (C) 2010 Alessandro Rubini
8fbb97a2	4	* Copyright (C) 2010 Linus Walleij for ST-Ericsson
28ad94ec AR	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2, as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/io.h>
	14	#include <linux/clockchips.h>
694e33a7	15	#include <linux/clocksource.h>
c7785ea0 RV	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/of_platform.h>
ba327b1e	19	#include <linux/clk.h>
28ad94ec	20	#include <linux/jiffies.h>
6f179b72	21	#include <linux/delay.h>
ba327b1e	22	#include <linux/err.h>
694e33a7	23	#include <linux/platform_data/clocksource-nomadik-mtu.h>
38ff87f7	24	#include <linux/sched_clock.h>
28ad94ec	25	#include <asm/mach/time.h>
28ad94ec	26
05387a9f JA	27	/*
	28	* The MTU device hosts four different counters, with 4 set of
	29	* registers. These are register names.
	30	*/
	31
	32	#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
	33	#define MTU_RIS 0x04 /* Raw interrupt status */
	34	#define MTU_MIS 0x08 /* Masked interrupt status */
	35	#define MTU_ICR 0x0C /* Interrupt clear register */
	36
	37	/* per-timer registers take 0..3 as argument */
	38	#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
	39	#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
	40	#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
	41	#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
	42
	43	/* bits for the control register */
	44	#define MTU_CRn_ENA 0x80
	45	#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
	46	#define MTU_CRn_PRESCALE_MASK 0x0c
	47	#define MTU_CRn_PRESCALE_1 0x00
	48	#define MTU_CRn_PRESCALE_16 0x04
	49	#define MTU_CRn_PRESCALE_256 0x08
	50	#define MTU_CRn_32BITS 0x02
	51	#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
	52
	53	/* Other registers are usual amba/primecell registers, currently not used */
	54	#define MTU_ITCR 0xff0
	55	#define MTU_ITOP 0xff4
	56
	57	#define MTU_PERIPH_ID0 0xfe0
	58	#define MTU_PERIPH_ID1 0xfe4
	59	#define MTU_PERIPH_ID2 0xfe8
	60	#define MTU_PERIPH_ID3 0xfeC
	61
	62	#define MTU_PCELL0 0xff0
	63	#define MTU_PCELL1 0xff4
	64	#define MTU_PCELL2 0xff8
	65	#define MTU_PCELL3 0xffC
28ad94ec	66
b9576623	67	static void __iomem *mtu_base;
2f73a068 JA	68	static bool clkevt_periodic;
	69	static u32 clk_prescale;
	70	static u32 nmdk_cycle; /* write-once */
6f179b72	71	static struct delay_timer mtu_delay_timer;
2f73a068	72
ea7113f7	73	#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
2a847513 LW	74	/*
	75	* Override the global weak sched_clock symbol with this
	76	* local implementation which uses the clocksource to get some
8fbb97a2	77	* better resolution when scheduling the kernel.
2a847513	78	*/
e25bc5f5	79	static u64 notrace nomadik_read_sched_clock(void)
2a847513	80	{
8fbb97a2 LW	81	if (unlikely(!mtu_base))
	82	return 0;
	83
2f0778af	84	return -readl(mtu_base + MTU_VAL(0));
2a847513	85	}
cba13830	86	#endif
2f73a068	87
6f179b72 FB	88	static unsigned long nmdk_timer_read_current_timer(void)
	89	{
	90	return ~readl_relaxed(mtu_base + MTU_VAL(0));
	91	}
	92
b102c01f	93	/* Clockevent device: use one-shot mode */
2f73a068 JA	94	static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
	95	{
	96	writel(1 << 1, mtu_base + MTU_IMSC);
	97	writel(evt, mtu_base + MTU_LR(1));
	98	/* Load highest value, enable device, enable interrupts */
	99	writel(MTU_CRn_ONESHOT \| clk_prescale \|
	100	MTU_CRn_32BITS \| MTU_CRn_ENA,
	101	mtu_base + MTU_CR(1));
	102
	103	return 0;
	104	}
	105
05387a9f	106	void nmdk_clkevt_reset(void)
2f73a068 JA	107	{
2f73a068 JA	108	if (clkevt_periodic) {
2f73a068 JA	109	/* Timer: configure load and background-load, and fire it up */
	110	writel(nmdk_cycle, mtu_base + MTU_LR(1));
	111	writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
	112
	113	writel(MTU_CRn_PERIODIC \| clk_prescale \|
	114	MTU_CRn_32BITS \| MTU_CRn_ENA,
	115	mtu_base + MTU_CR(1));
	116	writel(1 << 1, mtu_base + MTU_IMSC);
	117	} else {
	118	/* Generate an interrupt to start the clockevent again */
	119	(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	120	}
	121	}
	122
28ad94ec AR	123	static void nmdk_clkevt_mode(enum clock_event_mode mode,
	124	struct clock_event_device *dev)
	125	{
28ad94ec AR	126	switch (mode) {
28ad94ec AR	127	case CLOCK_EVT_MODE_PERIODIC:
2f73a068 JA	128	clkevt_periodic = true;
2f73a068 JA	129	nmdk_clkevt_reset();
28ad94ec AR	130	break;
28ad94ec AR	131	case CLOCK_EVT_MODE_ONESHOT:
2f73a068	132	clkevt_periodic = false;
b102c01f	133	break;
28ad94ec AR	134	case CLOCK_EVT_MODE_SHUTDOWN:
28ad94ec AR	135	case CLOCK_EVT_MODE_UNUSED:
b102c01f	136	writel(0, mtu_base + MTU_IMSC);
2917947a	137	/* disable timer */
2f73a068	138	writel(0, mtu_base + MTU_CR(1));
2917947a LW	139	/* load some high default value */
2917947a LW	140	writel(0xffffffff, mtu_base + MTU_LR(1));
28ad94ec AR	141	break;
	142	case CLOCK_EVT_MODE_RESUME:
	143	break;
	144	}
	145	}
	146
8726e96f SW	147	void nmdk_clksrc_reset(void)
	148	{
	149	/* Disable */
	150	writel(0, mtu_base + MTU_CR(0));
	151
	152	/* ClockSource: configure load and background-load, and fire it up */
	153	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	154	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
	155
	156	writel(clk_prescale \| MTU_CRn_32BITS \| MTU_CRn_ENA,
	157	mtu_base + MTU_CR(0));
	158	}
	159
	160	static void nmdk_clkevt_resume(struct clock_event_device *cedev)
	161	{
	162	nmdk_clkevt_reset();
	163	nmdk_clksrc_reset();
	164	}
	165
28ad94ec	166	static struct clock_event_device nmdk_clkevt = {
b102c01f	167	.name = "mtu_1",
74adcbff DL	168	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC \|
74adcbff DL	169	CLOCK_EVT_FEAT_DYNIRQ,
b102c01f	170	.rating = 200,
28ad94ec	171	.set_mode = nmdk_clkevt_mode,
b102c01f	172	.set_next_event = nmdk_clkevt_next,
8726e96f	173	.resume = nmdk_clkevt_resume,
28ad94ec AR	174	};
	175
	176	/*
b102c01f	177	* IRQ Handler for timer 1 of the MTU block.
28ad94ec AR	178	*/
	179	static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
	180	{
b102c01f	181	struct clock_event_device *evdev = dev_id;
28ad94ec	182
b102c01f AR	183	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
b102c01f AR	184	evdev->event_handler(evdev);
28ad94ec AR	185	return IRQ_HANDLED;
	186	}
	187
28ad94ec AR	188	static struct irqaction nmdk_timer_irq = {
	189	.name = "Nomadik Timer Tick",
	190	.flags = IRQF_DISABLED \| IRQF_TIMER,
	191	.handler = nmdk_timer_interrupt,
b102c01f	192	.dev_id = &nmdk_clkevt,
28ad94ec AR	193	};
28ad94ec AR	194
c7785ea0 RV	195	static void __init __nmdk_timer_init(void __iomem *base, int irq,
c7785ea0 RV	196	struct clk pclk, struct clk clk)
28ad94ec	197	{
28ad94ec	198	unsigned long rate;
ba327b1e	199
b9576623	200	mtu_base = base;
16defa66	201
c7785ea0 RV	202	BUG_ON(clk_prepare_enable(pclk));
c7785ea0 RV	203	BUG_ON(clk_prepare_enable(clk));
b102c01f AR	204
b102c01f AR	205	/*
a0719f52 LW	206	* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	207	* for ux500.
	208	* Use a divide-by-16 counter if the tick rate is more than 32MHz.
	209	* At 32 MHz, the timer (with 32 bit counter) can be programmed
	210	* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	211	* with 16 gives too low timer resolution.
b102c01f	212	*/
c7785ea0	213	rate = clk_get_rate(clk);
a0719f52	214	if (rate > 32000000) {
b102c01f	215	rate /= 16;
2f73a068	216	clk_prescale = MTU_CRn_PRESCALE_16;
b102c01f	217	} else {
2f73a068	218	clk_prescale = MTU_CRn_PRESCALE_1;
b102c01f	219	}
28ad94ec	220
21366831 LW	221	/* Cycles for periodic mode */
21366831 LW	222	nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
2f73a068 JA	223
2f73a068 JA	224
b102c01f	225	/* Timer 0 is the free running clocksource */
2f73a068	226	nmdk_clksrc_reset();
28ad94ec	227
bfe45e0b RK	228	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
bfe45e0b RK	229	rate, 200, 32, clocksource_mmio_readl_down))
b102c01f	230	pr_err("timer: failed to initialize clock source %s\n",
bfe45e0b	231	"mtu_0");
2f0778af	232
ea7113f7	233	#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
e25bc5f5	234	sched_clock_register(nomadik_read_sched_clock, 32, rate);
cba13830	235	#endif
2f0778af	236
a3b86a6d	237	/* Timer 1 is used for events, register irq and clockevents */
0813069d	238	setup_irq(irq, &nmdk_timer_irq);
a3b86a6d	239	nmdk_clkevt.cpumask = cpumask_of(0);
00f4e13c	240	nmdk_clkevt.irq = irq;
a3b86a6d	241	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
6f179b72 FB	242
	243	mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
	244	mtu_delay_timer.freq = rate;
	245	register_current_timer_delay(&mtu_delay_timer);
28ad94ec	246	}
c7785ea0 RV	247
	248	void __init nmdk_timer_init(void __iomem *base, int irq)
	249	{
	250	struct clk clk0, pclk0;
	251
	252	pclk0 = clk_get_sys("mtu0", "apb_pclk");
	253	BUG_ON(IS_ERR(pclk0));
	254	clk0 = clk_get_sys("mtu0", NULL);
	255	BUG_ON(IS_ERR(clk0));
	256
	257	__nmdk_timer_init(base, irq, pclk0, clk0);
	258	}
	259
3c09f4da	260	static void __init nmdk_timer_of_init(struct device_node *node)
c7785ea0	261	{
c7785ea0 RV	262	struct clk *pclk;
	263	struct clk *clk;
	264	void __iomem *base;
	265	int irq;
	266
c7785ea0 RV	267	base = of_iomap(node, 0);
	268	if (!base)
	269	panic("Can't remap registers");
	270
	271	pclk = of_clk_get_by_name(node, "apb_pclk");
	272	if (IS_ERR(pclk))
	273	panic("could not get apb_pclk");
	274
	275	clk = of_clk_get_by_name(node, "timclk");
	276	if (IS_ERR(clk))
	277	panic("could not get timclk");
	278
	279	irq = irq_of_parse_and_map(node, 0);
	280	if (irq <= 0)
	281	panic("Can't parse IRQ");
	282
	283	__nmdk_timer_init(base, irq, pclk, clk);
	284	}
	285	CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
	286	nmdk_timer_of_init);