[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / rockchip_timer.c

/*
 * Rockchip timer support
 *
 * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_NAME "rk_timer"

#define TIMER_LOAD_COUNT0	0x00
#define TIMER_LOAD_COUNT1	0x04
#define TIMER_CONTROL_REG3288	0x10
#define TIMER_CONTROL_REG3399	0x1c
#define TIMER_INT_STATUS	0x18

#define TIMER_DISABLE		0x0
#define TIMER_ENABLE		0x1
#define TIMER_MODE_FREE_RUNNING			(0 << 1)
#define TIMER_MODE_USER_DEFINED_COUNT		(1 << 1)
#define TIMER_INT_UNMASK			(1 << 2)

struct bc_timer {
	struct clock_event_device ce;
	void __iomem *base;
	void __iomem *ctrl;
	u32 freq;
};

static struct bc_timer bc_timer;

static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
{
	return container_of(ce, struct bc_timer, ce);
}

static inline void __iomem *rk_base(struct clock_event_device *ce)
{
	return rk_timer(ce)->base;
}

static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
{
	return rk_timer(ce)->ctrl;
}

static inline void rk_timer_disable(struct clock_event_device *ce)
{
	writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
}

static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
{
	writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
		       rk_ctrl(ce));
}

static void rk_timer_update_counter(unsigned long cycles,
				    struct clock_event_device *ce)
{
	writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
	writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
}

static void rk_timer_interrupt_clear(struct clock_event_device *ce)
{
	writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
}

static inline int rk_timer_set_next_event(unsigned long cycles,
					  struct clock_event_device *ce)
{
	rk_timer_disable(ce);
	rk_timer_update_counter(cycles, ce);
	rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
	return 0;
}

static int rk_timer_shutdown(struct clock_event_device *ce)
{
	rk_timer_disable(ce);
	return 0;
}

static int rk_timer_set_periodic(struct clock_event_device *ce)
{
	rk_timer_disable(ce);
	rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
	rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
	return 0;
}

static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;

	rk_timer_interrupt_clear(ce);

	if (clockevent_state_oneshot(ce))
		rk_timer_disable(ce);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
{
	struct clock_event_device *ce = &bc_timer.ce;
	struct clk *timer_clk;
	struct clk *pclk;
	int ret = -EINVAL, irq;

	bc_timer.base = of_iomap(np, 0);
	if (!bc_timer.base) {
		pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
		return -ENXIO;
	}
	bc_timer.ctrl = bc_timer.base + ctrl_reg;

	pclk = of_clk_get_by_name(np, "pclk");
	if (IS_ERR(pclk)) {
		ret = PTR_ERR(pclk);
		pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
		goto out_unmap;
	}

	ret = clk_prepare_enable(pclk);
	if (ret) {
		pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
		goto out_unmap;
	}

	timer_clk = of_clk_get_by_name(np, "timer");
	if (IS_ERR(timer_clk)) {
		ret = PTR_ERR(timer_clk);
		pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
		goto out_timer_clk;
	}

	ret = clk_prepare_enable(timer_clk);
	if (ret) {
		pr_err("Failed to enable timer clock\n");
		goto out_timer_clk;
	}

	bc_timer.freq = clk_get_rate(timer_clk);

	irq = irq_of_parse_and_map(np, 0);
	if (!irq) {
		ret = -EINVAL;
		pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
		goto out_irq;
	}

	ce->name = TIMER_NAME;
	ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
		       CLOCK_EVT_FEAT_DYNIRQ;
	ce->set_next_event = rk_timer_set_next_event;
	ce->set_state_shutdown = rk_timer_shutdown;
	ce->set_state_periodic = rk_timer_set_periodic;
	ce->irq = irq;
	ce->cpumask = cpu_possible_mask;
	ce->rating = 250;

	rk_timer_interrupt_clear(ce);
	rk_timer_disable(ce);

	ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
	if (ret) {
		pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
		goto out_irq;
	}

	clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);

	return 0;

out_irq:
	clk_disable_unprepare(timer_clk);
out_timer_clk:
	clk_disable_unprepare(pclk);
out_unmap:
	iounmap(bc_timer.base);

	return ret;
}

static int __init rk3288_timer_init(struct device_node *np)
{
	return rk_timer_init(np, TIMER_CONTROL_REG3288);
}

static int __init rk3399_timer_init(struct device_node *np)
{
	return rk_timer_init(np, TIMER_CONTROL_REG3399);
}

CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
		       rk3288_timer_init);
CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
		       rk3399_timer_init);
Commit	Line	Data
468b8c4c DL	1	/*
	2	* Rockchip timer support
	3	*
	4	* Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/clk.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_irq.h>
	17
	18	#define TIMER_NAME "rk_timer"
	19
a0d2216e CW	20	#define TIMER_LOAD_COUNT0 0x00
a0d2216e CW	21	#define TIMER_LOAD_COUNT1 0x04
be6af450 HT	22	#define TIMER_CONTROL_REG3288 0x10
be6af450 HT	23	#define TIMER_CONTROL_REG3399 0x1c
a0d2216e	24	#define TIMER_INT_STATUS 0x18
468b8c4c	25
a0d2216e CW	26	#define TIMER_DISABLE 0x0
	27	#define TIMER_ENABLE 0x1
	28	#define TIMER_MODE_FREE_RUNNING (0 << 1)
	29	#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
	30	#define TIMER_INT_UNMASK (1 << 2)
468b8c4c DL	31
	32	struct bc_timer {
	33	struct clock_event_device ce;
	34	void __iomem *base;
be6af450	35	void __iomem *ctrl;
468b8c4c DL	36	u32 freq;
	37	};
	38
	39	static struct bc_timer bc_timer;
	40
	41	static inline struct bc_timer rk_timer(struct clock_event_device ce)
	42	{
	43	return container_of(ce, struct bc_timer, ce);
	44	}
	45
	46	static inline void __iomem rk_base(struct clock_event_device ce)
	47	{
	48	return rk_timer(ce)->base;
	49	}
	50
be6af450 HT	51	static inline void __iomem rk_ctrl(struct clock_event_device ce)
	52	{
	53	return rk_timer(ce)->ctrl;
	54	}
	55
468b8c4c DL	56	static inline void rk_timer_disable(struct clock_event_device *ce)
468b8c4c DL	57	{
be6af450	58	writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
468b8c4c DL	59	}
	60
	61	static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
	62	{
	63	writel_relaxed(TIMER_ENABLE \| TIMER_INT_UNMASK \| flags,
be6af450	64	rk_ctrl(ce));
468b8c4c DL	65	}
	66
	67	static void rk_timer_update_counter(unsigned long cycles,
	68	struct clock_event_device *ce)
	69	{
	70	writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
	71	writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
468b8c4c DL	72	}
	73
	74	static void rk_timer_interrupt_clear(struct clock_event_device *ce)
	75	{
	76	writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
468b8c4c DL	77	}
	78
	79	static inline int rk_timer_set_next_event(unsigned long cycles,
	80	struct clock_event_device *ce)
	81	{
	82	rk_timer_disable(ce);
	83	rk_timer_update_counter(cycles, ce);
	84	rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
	85	return 0;
	86	}
	87
99b3fa72	88	static int rk_timer_shutdown(struct clock_event_device *ce)
468b8c4c	89	{
99b3fa72 VK	90	rk_timer_disable(ce);
	91	return 0;
	92	}
	93
	94	static int rk_timer_set_periodic(struct clock_event_device *ce)
	95	{
	96	rk_timer_disable(ce);
	97	rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
	98	rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
	99	return 0;
468b8c4c DL	100	}
	101
	102	static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
	103	{
	104	struct clock_event_device *ce = dev_id;
	105
	106	rk_timer_interrupt_clear(ce);
	107
99b3fa72	108	if (clockevent_state_oneshot(ce))
468b8c4c DL	109	rk_timer_disable(ce);
	110
	111	ce->event_handler(ce);
	112
	113	return IRQ_HANDLED;
	114	}
	115
8bdd5a2e	116	static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
468b8c4c DL	117	{
	118	struct clock_event_device *ce = &bc_timer.ce;
	119	struct clk *timer_clk;
	120	struct clk *pclk;
8bdd5a2e	121	int ret = -EINVAL, irq;
468b8c4c DL	122
	123	bc_timer.base = of_iomap(np, 0);
	124	if (!bc_timer.base) {
	125	pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
8bdd5a2e	126	return -ENXIO;
468b8c4c	127	}
be6af450	128	bc_timer.ctrl = bc_timer.base + ctrl_reg;
468b8c4c DL	129
	130	pclk = of_clk_get_by_name(np, "pclk");
	131	if (IS_ERR(pclk)) {
8bdd5a2e	132	ret = PTR_ERR(pclk);
468b8c4c	133	pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
522ed95c	134	goto out_unmap;
468b8c4c DL	135	}
468b8c4c DL	136
8bdd5a2e DL	137	ret = clk_prepare_enable(pclk);
8bdd5a2e DL	138	if (ret) {
468b8c4c	139	pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
522ed95c	140	goto out_unmap;
468b8c4c DL	141	}
	142
	143	timer_clk = of_clk_get_by_name(np, "timer");
	144	if (IS_ERR(timer_clk)) {
8bdd5a2e	145	ret = PTR_ERR(timer_clk);
468b8c4c	146	pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
522ed95c	147	goto out_timer_clk;
468b8c4c DL	148	}
468b8c4c DL	149
8bdd5a2e DL	150	ret = clk_prepare_enable(timer_clk);
8bdd5a2e DL	151	if (ret) {
468b8c4c	152	pr_err("Failed to enable timer clock\n");
522ed95c	153	goto out_timer_clk;
468b8c4c DL	154	}
	155
	156	bc_timer.freq = clk_get_rate(timer_clk);
	157
	158	irq = irq_of_parse_and_map(np, 0);
ccc42592	159	if (!irq) {
8bdd5a2e	160	ret = -EINVAL;
468b8c4c	161	pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
522ed95c	162	goto out_irq;
468b8c4c DL	163	}
	164
	165	ce->name = TIMER_NAME;
716897d9 HT	166	ce->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT \|
716897d9 HT	167	CLOCK_EVT_FEAT_DYNIRQ;
468b8c4c	168	ce->set_next_event = rk_timer_set_next_event;
99b3fa72 VK	169	ce->set_state_shutdown = rk_timer_shutdown;
99b3fa72 VK	170	ce->set_state_periodic = rk_timer_set_periodic;
468b8c4c	171	ce->irq = irq;
716897d9	172	ce->cpumask = cpu_possible_mask;
468b8c4c DL	173	ce->rating = 250;
	174
	175	rk_timer_interrupt_clear(ce);
	176	rk_timer_disable(ce);
	177
	178	ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
	179	if (ret) {
	180	pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
522ed95c	181	goto out_irq;
468b8c4c DL	182	}
	183
	184	clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
522ed95c	185
8bdd5a2e	186	return 0;
522ed95c SL	187
	188	out_irq:
	189	clk_disable_unprepare(timer_clk);
	190	out_timer_clk:
	191	clk_disable_unprepare(pclk);
	192	out_unmap:
	193	iounmap(bc_timer.base);
8bdd5a2e DL	194
8bdd5a2e DL	195	return ret;
468b8c4c	196	}
a0d2216e	197
8bdd5a2e	198	static int __init rk3288_timer_init(struct device_node *np)
be6af450	199	{
8bdd5a2e	200	return rk_timer_init(np, TIMER_CONTROL_REG3288);
be6af450 HT	201	}
be6af450 HT	202
8bdd5a2e	203	static int __init rk3399_timer_init(struct device_node *np)
be6af450	204	{
8bdd5a2e	205	return rk_timer_init(np, TIMER_CONTROL_REG3399);
be6af450 HT	206	}
be6af450 HT	207
177cf6e5 DL	208	CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
	209	rk3288_timer_init);
	210	CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
	211	rk3399_timer_init);