[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / samsung_pwm_timer.c

/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * samsung - Common hr-timer support (s3c and s5p)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sched_clock.h>

#include <clocksource/samsung_pwm.h>


/*
 * Clocksource driver
 */

#define REG_TCFG0			0x00
#define REG_TCFG1			0x04
#define REG_TCON			0x08
#define REG_TINT_CSTAT			0x44

#define REG_TCNTB(chan)			(0x0c + 12 * (chan))
#define REG_TCMPB(chan)			(0x10 + 12 * (chan))

#define TCFG0_PRESCALER_MASK		0xff
#define TCFG0_PRESCALER1_SHIFT		8

#define TCFG1_SHIFT(x)	  		((x) * 4)
#define TCFG1_MUX_MASK	  		0xf

/*
 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
 * bits (one channel) after channel 0, so channels have different numbering
 * when accessing TCON register.
 *
 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
 * in its set of bits is 2 as opposed to 3 for other channels.
 */
#define TCON_START(chan)		(1 << (4 * (chan) + 0))
#define TCON_MANUALUPDATE(chan)		(1 << (4 * (chan) + 1))
#define TCON_INVERT(chan)		(1 << (4 * (chan) + 2))
#define _TCON_AUTORELOAD(chan)		(1 << (4 * (chan) + 3))
#define _TCON_AUTORELOAD4(chan)		(1 << (4 * (chan) + 2))
#define TCON_AUTORELOAD(chan)		\
	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))

DEFINE_SPINLOCK(samsung_pwm_lock);
EXPORT_SYMBOL(samsung_pwm_lock);

struct samsung_pwm_clocksource {
	void __iomem *base;
	unsigned int irq[SAMSUNG_PWM_NUM];
	struct samsung_pwm_variant variant;

	struct clk *timerclk;

	unsigned int event_id;
	unsigned int source_id;
	unsigned int tcnt_max;
	unsigned int tscaler_div;
	unsigned int tdiv;

	unsigned long clock_count_per_tick;
};

static struct samsung_pwm_clocksource pwm;

static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
{
	unsigned long flags;
	u8 shift = 0;
	u32 reg;

	if (channel >= 2)
		shift = TCFG0_PRESCALER1_SHIFT;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG0);
	reg &= ~(TCFG0_PRESCALER_MASK << shift);
	reg |= (prescale - 1) << shift;
	writel(reg, pwm.base + REG_TCFG0);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
{
	u8 shift = TCFG1_SHIFT(channel);
	unsigned long flags;
	u32 reg;
	u8 bits;

	bits = (fls(divisor) - 1) - pwm.variant.div_base;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG1);
	reg &= ~(TCFG1_MUX_MASK << shift);
	reg |= bits << shift;
	writel(reg, pwm.base + REG_TCFG1);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_stop(unsigned int channel)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);
	tcon &= ~TCON_START(channel);
	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
{
	unsigned long tcon;
	unsigned long flags;
	unsigned int tcon_chan = channel;

	if (tcon_chan > 0)
		++tcon_chan;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);

	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
	tcon |= TCON_MANUALUPDATE(tcon_chan);

	__raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
	__raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_start(unsigned int channel, bool periodic)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);

	tcon &= ~TCON_MANUALUPDATE(channel);
	tcon |= TCON_START(channel);

	if (periodic)
		tcon |= TCON_AUTORELOAD(channel);
	else
		tcon &= ~TCON_AUTORELOAD(channel);

	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static int samsung_set_next_event(unsigned long cycles,
				struct clock_event_device *evt)
{
	/*
	 * This check is needed to account for internal rounding
	 * errors inside clockevents core, which might result in
	 * passing cycles = 0, which in turn would not generate any
	 * timer interrupt and hang the system.
	 *
	 * Another solution would be to set up the clockevent device
	 * with min_delta = 2, but this would unnecessarily increase
	 * the minimum sleep period.
	 */
	if (!cycles)
		cycles = 1;

	samsung_time_setup(pwm.event_id, cycles);
	samsung_time_start(pwm.event_id, false);

	return 0;
}

static void samsung_timer_resume(void)
{
	/* event timer restart */
	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	samsung_time_start(pwm.event_id, true);

	/* source timer restart */
	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);
}

static void samsung_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
		samsung_time_start(pwm.event_id, true);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;

	case CLOCK_EVT_MODE_RESUME:
		samsung_timer_resume();
		break;
	}
}

static struct clock_event_device time_event_device = {
	.name		= "samsung_event_timer",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= samsung_set_next_event,
	.set_mode	= samsung_set_mode,
};

static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction samsung_clock_event_irq = {
	.name		= "samsung_time_irq",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= samsung_clock_event_isr,
	.dev_id		= &time_event_device,
};

static void __init samsung_clockevent_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;
	unsigned int irq_number;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
	pwm.clock_count_per_tick = clock_rate / HZ;

	time_event_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&time_event_device,
						clock_rate, 1, pwm.tcnt_max);

	irq_number = pwm.irq[pwm.event_id];
	setup_irq(irq_number, &samsung_clock_event_irq);

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static void __iomem *samsung_timer_reg(void)
{
	switch (pwm.source_id) {
	case 0:
	case 1:
	case 2:
	case 3:
		return pwm.base + pwm.source_id * 0x0c + 0x14;

	case 4:
		return pwm.base + 0x40;

	default:
		BUG();
	}
}

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by U300 implementation.)
 */
static u32 notrace samsung_read_sched_clock(void)
{
	void __iomem *reg = samsung_timer_reg();

	if (!reg)
		return 0;

	return ~__raw_readl(reg);
}

static void __init samsung_clocksource_init(void)
{
	void __iomem *reg = samsung_timer_reg();
	unsigned long pclk;
	unsigned long clock_rate;
	int ret;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);

	setup_sched_clock(samsung_read_sched_clock,
						pwm.variant.bits, clock_rate);

	ret = clocksource_mmio_init(reg, "samsung_clocksource_timer",
					clock_rate, 250, pwm.variant.bits,
					clocksource_mmio_readl_down);
	if (ret)
		panic("samsung_clocksource_timer: can't register clocksource\n");
}

static void __init samsung_timer_resources(void)
{
	pwm.timerclk = clk_get(NULL, "timers");
	if (IS_ERR(pwm.timerclk))
		panic("failed to get timers clock for timer");

	clk_prepare_enable(pwm.timerclk);

	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	if (pwm.variant.bits == 16) {
		pwm.tscaler_div = 25;
		pwm.tdiv = 2;
	} else {
		pwm.tscaler_div = 2;
		pwm.tdiv = 1;
	}
}

/*
 * PWM master driver
 */
static void __init _samsung_pwm_clocksource_init(void)
{
	u8 mask;
	int channel;

	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
	channel = fls(mask) - 1;
	if (channel < 0)
		panic("failed to find PWM channel for clocksource");
	pwm.source_id = channel;

	mask &= ~(1 << channel);
	channel = fls(mask) - 1;
	if (channel < 0)
		panic("failed to find PWM channel for clock event");
	pwm.event_id = channel;

	samsung_timer_resources();
	samsung_clockevent_init();
	samsung_clocksource_init();
}

void __init samsung_pwm_clocksource_init(void __iomem *base,
			unsigned int *irqs, struct samsung_pwm_variant *variant)
{
	pwm.base = base;
	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));

	_samsung_pwm_clocksource_init();
}

#ifdef CONFIG_CLKSRC_OF
static void __init samsung_pwm_alloc(struct device_node *np,
				     const struct samsung_pwm_variant *variant)
{
	struct property *prop;
	const __be32 *cur;
	u32 val;
	int i;

	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
		pwm.irq[i] = irq_of_parse_and_map(np, i);

	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
		if (val >= SAMSUNG_PWM_NUM) {
			pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
								__func__);
			continue;
		}
		pwm.variant.output_mask |= 1 << val;
	}

	pwm.base = of_iomap(np, 0);
	if (!pwm.base) {
		pr_err("%s: failed to map PWM registers\n", __func__);
		return;
	}

	_samsung_pwm_clocksource_init();
}

static const struct samsung_pwm_variant s3c24xx_variant = {
	.bits		= 16,
	.div_base	= 1,
	.has_tint_cstat	= false,
	.tclk_mask	= (1 << 4),
};

static void __init s3c2410_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s3c24xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);

static const struct samsung_pwm_variant s3c64xx_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

static void __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s3c64xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p64x0_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= 0,
};

static void __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s5p64x0_variant);
}
CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 5),
};

static void __init s5p_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s5p_variant);
}
CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
#endif
Commit	Line	Data
f1189989 TF	1	/*
	2	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com/
	4	*
	5	* samsung - Common hr-timer support (s3c and s5p)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/clockchips.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/slab.h>
38ff87f7	24	#include <linux/sched_clock.h>
f1189989 TF	25
	26	#include <clocksource/samsung_pwm.h>
	27
f1189989 TF	28
	29	/*
	30	* Clocksource driver
	31	*/
	32
	33	#define REG_TCFG0 0x00
	34	#define REG_TCFG1 0x04
	35	#define REG_TCON 0x08
	36	#define REG_TINT_CSTAT 0x44
	37
	38	#define REG_TCNTB(chan) (0x0c + 12 * (chan))
	39	#define REG_TCMPB(chan) (0x10 + 12 * (chan))
	40
	41	#define TCFG0_PRESCALER_MASK 0xff
	42	#define TCFG0_PRESCALER1_SHIFT 8
	43
	44	#define TCFG1_SHIFT(x) ((x) * 4)
	45	#define TCFG1_MUX_MASK 0xf
	46
ceea1241 TF	47	/*
	48	* Each channel occupies 4 bits in TCON register, but there is a gap of 4
	49	* bits (one channel) after channel 0, so channels have different numbering
	50	* when accessing TCON register.
	51	*
	52	* In addition, the location of autoreload bit for channel 4 (TCON channel 5)
	53	* in its set of bits is 2 as opposed to 3 for other channels.
	54	*/
f1189989 TF	55	#define TCON_START(chan) (1 << (4 * (chan) + 0))
	56	#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
	57	#define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
ceea1241 TF	58	#define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
	59	#define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2))
	60	#define TCON_AUTORELOAD(chan) \
	61	((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
f1189989	62
7aac482e TF	63	DEFINE_SPINLOCK(samsung_pwm_lock);
	64	EXPORT_SYMBOL(samsung_pwm_lock);
	65
030c2a1e TF	66	struct samsung_pwm_clocksource {
	67	void __iomem *base;
	68	unsigned int irq[SAMSUNG_PWM_NUM];
	69	struct samsung_pwm_variant variant;
	70
	71	struct clk *timerclk;
	72
f1189989 TF	73	unsigned int event_id;
	74	unsigned int source_id;
	75	unsigned int tcnt_max;
	76	unsigned int tscaler_div;
	77	unsigned int tdiv;
030c2a1e TF	78
030c2a1e TF	79	unsigned long clock_count_per_tick;
f1189989 TF	80	};
f1189989 TF	81
030c2a1e	82	static struct samsung_pwm_clocksource pwm;
f1189989	83
030c2a1e	84	static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
f1189989 TF	85	{
	86	unsigned long flags;
	87	u8 shift = 0;
	88	u32 reg;
	89
	90	if (channel >= 2)
	91	shift = TCFG0_PRESCALER1_SHIFT;
	92
7aac482e	93	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	94
030c2a1e	95	reg = readl(pwm.base + REG_TCFG0);
f1189989 TF	96	reg &= ~(TCFG0_PRESCALER_MASK << shift);
f1189989 TF	97	reg \|= (prescale - 1) << shift;
030c2a1e	98	writel(reg, pwm.base + REG_TCFG0);
f1189989	99
7aac482e	100	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	101	}
f1189989 TF	102
030c2a1e	103	static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
f1189989 TF	104	{
	105	u8 shift = TCFG1_SHIFT(channel);
	106	unsigned long flags;
	107	u32 reg;
	108	u8 bits;
	109
030c2a1e	110	bits = (fls(divisor) - 1) - pwm.variant.div_base;
f1189989	111
7aac482e	112	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	113
030c2a1e	114	reg = readl(pwm.base + REG_TCFG1);
f1189989 TF	115	reg &= ~(TCFG1_MUX_MASK << shift);
f1189989 TF	116	reg \|= bits << shift;
030c2a1e	117	writel(reg, pwm.base + REG_TCFG1);
f1189989	118
7aac482e	119	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	120	}
	121
	122	static void samsung_time_stop(unsigned int channel)
	123	{
	124	unsigned long tcon;
	125	unsigned long flags;
	126
	127	if (channel > 0)
	128	++channel;
	129
7aac482e	130	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	131
030c2a1e	132	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989	133	tcon &= ~TCON_START(channel);
030c2a1e	134	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	135
7aac482e	136	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	137	}
	138
	139	static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
	140	{
	141	unsigned long tcon;
	142	unsigned long flags;
	143	unsigned int tcon_chan = channel;
	144
	145	if (tcon_chan > 0)
	146	++tcon_chan;
	147
7aac482e	148	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	149
030c2a1e	150	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989	151
f1189989 TF	152	tcon &= ~(TCON_START(tcon_chan) \| TCON_AUTORELOAD(tcon_chan));
	153	tcon \|= TCON_MANUALUPDATE(tcon_chan);
	154
030c2a1e TF	155	__raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
	156	__raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
	157	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	158
7aac482e	159	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	160	}
	161
	162	static void samsung_time_start(unsigned int channel, bool periodic)
	163	{
	164	unsigned long tcon;
	165	unsigned long flags;
	166
	167	if (channel > 0)
	168	++channel;
	169
7aac482e	170	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	171
030c2a1e	172	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989 TF	173
	174	tcon &= ~TCON_MANUALUPDATE(channel);
	175	tcon \|= TCON_START(channel);
	176
	177	if (periodic)
	178	tcon \|= TCON_AUTORELOAD(channel);
	179	else
	180	tcon &= ~TCON_AUTORELOAD(channel);
	181
030c2a1e	182	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	183
7aac482e	184	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	185	}
	186
	187	static int samsung_set_next_event(unsigned long cycles,
	188	struct clock_event_device *evt)
	189	{
81d4f7bf TF	190	/*
	191	* This check is needed to account for internal rounding
	192	* errors inside clockevents core, which might result in
	193	* passing cycles = 0, which in turn would not generate any
	194	* timer interrupt and hang the system.
	195	*
	196	* Another solution would be to set up the clockevent device
	197	* with min_delta = 2, but this would unnecessarily increase
	198	* the minimum sleep period.
	199	*/
	200	if (!cycles)
	201	cycles = 1;
	202
030c2a1e TF	203	samsung_time_setup(pwm.event_id, cycles);
030c2a1e TF	204	samsung_time_start(pwm.event_id, false);
f1189989 TF	205
	206	return 0;
	207	}
	208
	209	static void samsung_timer_resume(void)
	210	{
	211	/* event timer restart */
6fe4dfd0	212	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
030c2a1e	213	samsung_time_start(pwm.event_id, true);
f1189989 TF	214
f1189989 TF	215	/* source timer restart */
030c2a1e TF	216	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	217	samsung_time_start(pwm.source_id, true);
f1189989 TF	218	}
	219
	220	static void samsung_set_mode(enum clock_event_mode mode,
	221	struct clock_event_device *evt)
	222	{
030c2a1e	223	samsung_time_stop(pwm.event_id);
f1189989 TF	224
	225	switch (mode) {
	226	case CLOCK_EVT_MODE_PERIODIC:
6fe4dfd0	227	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
030c2a1e	228	samsung_time_start(pwm.event_id, true);
f1189989 TF	229	break;
	230
	231	case CLOCK_EVT_MODE_ONESHOT:
	232	break;
	233
	234	case CLOCK_EVT_MODE_UNUSED:
	235	case CLOCK_EVT_MODE_SHUTDOWN:
	236	break;
	237
	238	case CLOCK_EVT_MODE_RESUME:
	239	samsung_timer_resume();
	240	break;
	241	}
	242	}
	243
	244	static struct clock_event_device time_event_device = {
	245	.name = "samsung_event_timer",
	246	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	247	.rating = 200,
	248	.set_next_event = samsung_set_next_event,
	249	.set_mode = samsung_set_mode,
	250	};
	251
	252	static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
	253	{
	254	struct clock_event_device *evt = dev_id;
	255
030c2a1e TF	256	if (pwm.variant.has_tint_cstat) {
	257	u32 mask = (1 << pwm.event_id);
	258	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	259	}
	260
	261	evt->event_handler(evt);
	262
	263	return IRQ_HANDLED;
	264	}
	265
	266	static struct irqaction samsung_clock_event_irq = {
	267	.name = "samsung_time_irq",
	268	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	269	.handler = samsung_clock_event_isr,
	270	.dev_id = &time_event_device,
	271	};
	272
	273	static void __init samsung_clockevent_init(void)
	274	{
	275	unsigned long pclk;
	276	unsigned long clock_rate;
	277	unsigned int irq_number;
	278
030c2a1e	279	pclk = clk_get_rate(pwm.timerclk);
f1189989	280
030c2a1e TF	281	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
030c2a1e TF	282	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
f1189989	283
030c2a1e TF	284	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
030c2a1e TF	285	pwm.clock_count_per_tick = clock_rate / HZ;
f1189989 TF	286
f1189989 TF	287	time_event_device.cpumask = cpumask_of(0);
e9b852b8 TF	288	clockevents_config_and_register(&time_event_device,
e9b852b8 TF	289	clock_rate, 1, pwm.tcnt_max);
f1189989	290
030c2a1e	291	irq_number = pwm.irq[pwm.event_id];
f1189989 TF	292	setup_irq(irq_number, &samsung_clock_event_irq);
f1189989 TF	293
030c2a1e TF	294	if (pwm.variant.has_tint_cstat) {
	295	u32 mask = (1 << pwm.event_id);
	296	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	297	}
	298	}
	299
	300	static void __iomem *samsung_timer_reg(void)
	301	{
030c2a1e	302	switch (pwm.source_id) {
f1189989 TF	303	case 0:
	304	case 1:
	305	case 2:
	306	case 3:
030c2a1e	307	return pwm.base + pwm.source_id * 0x0c + 0x14;
f1189989 TF	308
f1189989 TF	309	case 4:
030c2a1e	310	return pwm.base + 0x40;
f1189989 TF	311
	312	default:
	313	BUG();
	314	}
	315	}
	316
	317	/*
	318	* Override the global weak sched_clock symbol with this
	319	* local implementation which uses the clocksource to get some
	320	* better resolution when scheduling the kernel. We accept that
	321	* this wraps around for now, since it is just a relative time
	322	* stamp. (Inspired by U300 implementation.)
	323	*/
	324	static u32 notrace samsung_read_sched_clock(void)
	325	{
	326	void __iomem *reg = samsung_timer_reg();
	327
	328	if (!reg)
	329	return 0;
	330
	331	return ~__raw_readl(reg);
	332	}
	333
	334	static void __init samsung_clocksource_init(void)
	335	{
	336	void __iomem *reg = samsung_timer_reg();
	337	unsigned long pclk;
	338	unsigned long clock_rate;
	339	int ret;
	340
030c2a1e	341	pclk = clk_get_rate(pwm.timerclk);
f1189989	342
030c2a1e TF	343	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
030c2a1e TF	344	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
f1189989	345
030c2a1e	346	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
f1189989	347
030c2a1e TF	348	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	349	samsung_time_start(pwm.source_id, true);
f1189989 TF	350
f1189989 TF	351	setup_sched_clock(samsung_read_sched_clock,
030c2a1e	352	pwm.variant.bits, clock_rate);
f1189989 TF	353
f1189989 TF	354	ret = clocksource_mmio_init(reg, "samsung_clocksource_timer",
030c2a1e	355	clock_rate, 250, pwm.variant.bits,
f1189989 TF	356	clocksource_mmio_readl_down);
	357	if (ret)
	358	panic("samsung_clocksource_timer: can't register clocksource\n");
	359	}
	360
	361	static void __init samsung_timer_resources(void)
	362	{
030c2a1e TF	363	pwm.timerclk = clk_get(NULL, "timers");
030c2a1e TF	364	if (IS_ERR(pwm.timerclk))
f1189989 TF	365	panic("failed to get timers clock for timer");
f1189989 TF	366
030c2a1e	367	clk_prepare_enable(pwm.timerclk);
f1189989	368
030c2a1e TF	369	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	370	if (pwm.variant.bits == 16) {
	371	pwm.tscaler_div = 25;
	372	pwm.tdiv = 2;
f1189989	373	} else {
030c2a1e TF	374	pwm.tscaler_div = 2;
030c2a1e TF	375	pwm.tdiv = 1;
f1189989 TF	376	}
	377	}
	378
	379	/*
	380	* PWM master driver
	381	*/
f9bb48a2	382	static void __init _samsung_pwm_clocksource_init(void)
f1189989 TF	383	{
	384	u8 mask;
	385	int channel;
	386
030c2a1e	387	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
f1189989 TF	388	channel = fls(mask) - 1;
	389	if (channel < 0)
	390	panic("failed to find PWM channel for clocksource");
030c2a1e	391	pwm.source_id = channel;
f1189989 TF	392
	393	mask &= ~(1 << channel);
	394	channel = fls(mask) - 1;
	395	if (channel < 0)
	396	panic("failed to find PWM channel for clock event");
030c2a1e	397	pwm.event_id = channel;
f1189989 TF	398
	399	samsung_timer_resources();
	400	samsung_clockevent_init();
	401	samsung_clocksource_init();
	402	}
	403
f9bb48a2 TF	404	void __init samsung_pwm_clocksource_init(void __iomem *base,
	405	unsigned int irqs, struct samsung_pwm_variant variant)
	406	{
	407	pwm.base = base;
	408	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	409	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
	410
	411	_samsung_pwm_clocksource_init();
	412	}
	413
	414	#ifdef CONFIG_CLKSRC_OF
f1189989 TF	415	static void __init samsung_pwm_alloc(struct device_node *np,
	416	const struct samsung_pwm_variant *variant)
	417	{
f1189989 TF	418	struct property *prop;
	419	const __be32 *cur;
	420	u32 val;
	421	int i;
	422
030c2a1e	423	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
f1189989	424	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
030c2a1e	425	pwm.irq[i] = irq_of_parse_and_map(np, i);
f1189989 TF	426
	427	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
	428	if (val >= SAMSUNG_PWM_NUM) {
	429	pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
	430	__func__);
	431	continue;
	432	}
030c2a1e	433	pwm.variant.output_mask \|= 1 << val;
f1189989 TF	434	}
f1189989 TF	435
e2415489	436	pwm.base = of_iomap(np, 0);
030c2a1e	437	if (!pwm.base) {
f1189989	438	pr_err("%s: failed to map PWM registers\n", __func__);
f1189989 TF	439	return;
	440	}
	441
f9bb48a2	442	_samsung_pwm_clocksource_init();
f1189989 TF	443	}
	444
	445	static const struct samsung_pwm_variant s3c24xx_variant = {
	446	.bits = 16,
	447	.div_base = 1,
	448	.has_tint_cstat = false,
	449	.tclk_mask = (1 << 4),
	450	};
	451
	452	static void __init s3c2410_pwm_clocksource_init(struct device_node *np)
	453	{
	454	samsung_pwm_alloc(np, &s3c24xx_variant);
	455	}
	456	CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
	457
	458	static const struct samsung_pwm_variant s3c64xx_variant = {
	459	.bits = 32,
	460	.div_base = 0,
	461	.has_tint_cstat = true,
	462	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	463	};
	464
	465	static void __init s3c64xx_pwm_clocksource_init(struct device_node *np)
	466	{
	467	samsung_pwm_alloc(np, &s3c64xx_variant);
	468	}
	469	CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
	470
	471	static const struct samsung_pwm_variant s5p64x0_variant = {
	472	.bits = 32,
	473	.div_base = 0,
	474	.has_tint_cstat = true,
	475	.tclk_mask = 0,
	476	};
	477
	478	static void __init s5p64x0_pwm_clocksource_init(struct device_node *np)
	479	{
	480	samsung_pwm_alloc(np, &s5p64x0_variant);
	481	}
	482	CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
	483
	484	static const struct samsung_pwm_variant s5p_variant = {
	485	.bits = 32,
	486	.div_base = 0,
	487	.has_tint_cstat = true,
	488	.tclk_mask = (1 << 5),
	489	};
	490
	491	static void __init s5p_pwm_clocksource_init(struct device_node *np)
	492	{
	493	samsung_pwm_alloc(np, &s5p_variant);
	494	}
	495	CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
f9bb48a2	496	#endif