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Commit | Line | Data |
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3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
3fb1b6ad MD |
14 | */ |
15 | ||
e7a9bcc2 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/clocksource.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
3fb1b6ad | 21 | #include <linux/init.h> |
3fb1b6ad | 22 | #include <linux/interrupt.h> |
3fb1b6ad | 23 | #include <linux/io.h> |
e7a9bcc2 | 24 | #include <linux/ioport.h> |
3fb1b6ad | 25 | #include <linux/irq.h> |
7deeab5d | 26 | #include <linux/module.h> |
1768aa2f | 27 | #include <linux/of.h> |
2d1d5172 | 28 | #include <linux/of_device.h> |
e7a9bcc2 | 29 | #include <linux/platform_device.h> |
615a445f | 30 | #include <linux/pm_domain.h> |
bad81383 | 31 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
32 | #include <linux/sh_timer.h> |
33 | #include <linux/slab.h> | |
34 | #include <linux/spinlock.h> | |
3fb1b6ad | 35 | |
2653caf4 | 36 | struct sh_cmt_device; |
7269f933 | 37 | |
2cda3ac4 LP |
38 | /* |
39 | * The CMT comes in 5 different identified flavours, depending not only on the | |
40 | * SoC but also on the particular instance. The following table lists the main | |
41 | * characteristics of those flavours. | |
42 | * | |
83c79a6d | 43 | * 16B 32B 32B-F 48B R-Car Gen2 |
2cda3ac4 LP |
44 | * ----------------------------------------------------------------------------- |
45 | * Channels 2 1/4 1 6 2/8 | |
46 | * Control Width 16 16 16 16 32 | |
47 | * Counter Width 16 32 32 32/48 32/48 | |
48 | * Shared Start/Stop Y Y Y Y N | |
49 | * | |
83c79a6d MD |
50 | * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register |
51 | * located in the channel registers block. All other versions have a shared | |
52 | * start/stop register located in the global space. | |
2cda3ac4 | 53 | * |
81b3b271 LP |
54 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
55 | * infers the start/stop bit position in the control register and the channel | |
56 | * registers block address. Some CMT instances have a subset of channels | |
57 | * available, in which case the index in the documentation doesn't match the | |
58 | * "real" index as implemented in hardware. This is for instance the case with | |
59 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
60 | * in the documentation but using start/stop bit 5 and having its registers | |
61 | * block at 0x60. | |
62 | * | |
63 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
64 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
65 | */ | |
66 | ||
67 | enum sh_cmt_model { | |
68 | SH_CMT_16BIT, | |
69 | SH_CMT_32BIT, | |
2cda3ac4 | 70 | SH_CMT_48BIT, |
83c79a6d MD |
71 | SH_CMT0_RCAR_GEN2, |
72 | SH_CMT1_RCAR_GEN2, | |
2cda3ac4 LP |
73 | }; |
74 | ||
75 | struct sh_cmt_info { | |
76 | enum sh_cmt_model model; | |
77 | ||
464eed84 MD |
78 | unsigned int channels_mask; |
79 | ||
2cda3ac4 LP |
80 | unsigned long width; /* 16 or 32 bit version of hardware block */ |
81 | unsigned long overflow_bit; | |
82 | unsigned long clear_bits; | |
83 | ||
84 | /* callbacks for CMSTR and CMCSR access */ | |
85 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
86 | void (*write_control)(void __iomem *base, unsigned long offs, | |
87 | unsigned long value); | |
88 | ||
89 | /* callbacks for CMCNT and CMCOR access */ | |
90 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
91 | void (*write_count)(void __iomem *base, unsigned long offs, | |
92 | unsigned long value); | |
93 | }; | |
94 | ||
7269f933 | 95 | struct sh_cmt_channel { |
2653caf4 | 96 | struct sh_cmt_device *cmt; |
3fb1b6ad | 97 | |
81b3b271 LP |
98 | unsigned int index; /* Index in the documentation */ |
99 | unsigned int hwidx; /* Real hardware index */ | |
100 | ||
101 | void __iomem *iostart; | |
102 | void __iomem *ioctrl; | |
c924d2d2 | 103 | |
81b3b271 | 104 | unsigned int timer_bit; |
3fb1b6ad MD |
105 | unsigned long flags; |
106 | unsigned long match_value; | |
107 | unsigned long next_match_value; | |
108 | unsigned long max_match_value; | |
7d0c399f | 109 | raw_spinlock_t lock; |
3fb1b6ad | 110 | struct clock_event_device ced; |
19bdc9d0 | 111 | struct clocksource cs; |
3fb1b6ad | 112 | unsigned long total_cycles; |
bad81383 | 113 | bool cs_enabled; |
7269f933 LP |
114 | }; |
115 | ||
2653caf4 | 116 | struct sh_cmt_device { |
7269f933 LP |
117 | struct platform_device *pdev; |
118 | ||
2cda3ac4 LP |
119 | const struct sh_cmt_info *info; |
120 | ||
7269f933 | 121 | void __iomem *mapbase; |
7269f933 | 122 | struct clk *clk; |
890f423b | 123 | unsigned long rate; |
7269f933 | 124 | |
de599c88 LP |
125 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
126 | ||
f5ec9b19 LP |
127 | struct sh_cmt_channel *channels; |
128 | unsigned int num_channels; | |
1768aa2f | 129 | unsigned int hw_channels; |
81b3b271 LP |
130 | |
131 | bool has_clockevent; | |
132 | bool has_clocksource; | |
3fb1b6ad MD |
133 | }; |
134 | ||
d14be99b LP |
135 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
136 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
137 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
138 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
139 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
140 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
141 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
142 | ||
143 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
144 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
145 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
146 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
147 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
148 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
149 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
150 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
151 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
152 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
153 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
154 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
155 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
156 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
157 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
158 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
159 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
160 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
161 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
162 | ||
a6a912ca | 163 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
164 | { |
165 | return ioread16(base + (offs << 1)); | |
166 | } | |
167 | ||
a6a912ca MD |
168 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
169 | { | |
170 | return ioread32(base + (offs << 2)); | |
171 | } | |
172 | ||
173 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
174 | unsigned long value) | |
587acb3d MD |
175 | { |
176 | iowrite16(value, base + (offs << 1)); | |
177 | } | |
3fb1b6ad | 178 | |
a6a912ca MD |
179 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
180 | unsigned long value) | |
181 | { | |
182 | iowrite32(value, base + (offs << 2)); | |
183 | } | |
184 | ||
2cda3ac4 LP |
185 | static const struct sh_cmt_info sh_cmt_info[] = { |
186 | [SH_CMT_16BIT] = { | |
187 | .model = SH_CMT_16BIT, | |
188 | .width = 16, | |
d14be99b LP |
189 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
190 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
191 | .read_control = sh_cmt_read16, |
192 | .write_control = sh_cmt_write16, | |
193 | .read_count = sh_cmt_read16, | |
194 | .write_count = sh_cmt_write16, | |
195 | }, | |
196 | [SH_CMT_32BIT] = { | |
197 | .model = SH_CMT_32BIT, | |
198 | .width = 32, | |
d14be99b LP |
199 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
200 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
201 | .read_control = sh_cmt_read16, |
202 | .write_control = sh_cmt_write16, | |
203 | .read_count = sh_cmt_read32, | |
204 | .write_count = sh_cmt_write32, | |
205 | }, | |
2cda3ac4 LP |
206 | [SH_CMT_48BIT] = { |
207 | .model = SH_CMT_48BIT, | |
464eed84 | 208 | .channels_mask = 0x3f, |
2cda3ac4 | 209 | .width = 32, |
d14be99b LP |
210 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
211 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
212 | .read_control = sh_cmt_read32, |
213 | .write_control = sh_cmt_write32, | |
214 | .read_count = sh_cmt_read32, | |
215 | .write_count = sh_cmt_write32, | |
216 | }, | |
83c79a6d MD |
217 | [SH_CMT0_RCAR_GEN2] = { |
218 | .model = SH_CMT0_RCAR_GEN2, | |
219 | .channels_mask = 0x60, | |
220 | .width = 32, | |
221 | .overflow_bit = SH_CMT32_CMCSR_CMF, | |
222 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
223 | .read_control = sh_cmt_read32, | |
224 | .write_control = sh_cmt_write32, | |
225 | .read_count = sh_cmt_read32, | |
226 | .write_count = sh_cmt_write32, | |
227 | }, | |
228 | [SH_CMT1_RCAR_GEN2] = { | |
229 | .model = SH_CMT1_RCAR_GEN2, | |
230 | .channels_mask = 0xff, | |
2cda3ac4 | 231 | .width = 32, |
d14be99b LP |
232 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
233 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
234 | .read_control = sh_cmt_read32, |
235 | .write_control = sh_cmt_write32, | |
236 | .read_count = sh_cmt_read32, | |
237 | .write_count = sh_cmt_write32, | |
238 | }, | |
239 | }; | |
240 | ||
3fb1b6ad MD |
241 | #define CMCSR 0 /* channel register */ |
242 | #define CMCNT 1 /* channel register */ | |
243 | #define CMCOR 2 /* channel register */ | |
244 | ||
7269f933 | 245 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 246 | { |
81b3b271 LP |
247 | if (ch->iostart) |
248 | return ch->cmt->info->read_control(ch->iostart, 0); | |
249 | else | |
250 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
251 | } |
252 | ||
81b3b271 LP |
253 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
254 | unsigned long value) | |
1b56b96b | 255 | { |
81b3b271 LP |
256 | if (ch->iostart) |
257 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
258 | else | |
259 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
260 | } |
261 | ||
81b3b271 | 262 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 263 | { |
81b3b271 | 264 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
265 | } |
266 | ||
81b3b271 | 267 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
268 | unsigned long value) |
269 | { | |
81b3b271 | 270 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
271 | } |
272 | ||
81b3b271 | 273 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 274 | { |
81b3b271 | 275 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
276 | } |
277 | ||
7269f933 | 278 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
279 | unsigned long value) |
280 | { | |
81b3b271 | 281 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
282 | } |
283 | ||
7269f933 | 284 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
285 | unsigned long value) |
286 | { | |
81b3b271 | 287 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
288 | } |
289 | ||
7269f933 | 290 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
291 | int *has_wrapped) |
292 | { | |
293 | unsigned long v1, v2, v3; | |
5b644c7a MD |
294 | int o1, o2; |
295 | ||
2cda3ac4 | 296 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
297 | |
298 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
299 | do { | |
5b644c7a | 300 | o2 = o1; |
7269f933 LP |
301 | v1 = sh_cmt_read_cmcnt(ch); |
302 | v2 = sh_cmt_read_cmcnt(ch); | |
303 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 304 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
305 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
306 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 307 | |
5b644c7a | 308 | *has_wrapped = o1; |
3fb1b6ad MD |
309 | return v2; |
310 | } | |
311 | ||
7269f933 | 312 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 313 | { |
3fb1b6ad MD |
314 | unsigned long flags, value; |
315 | ||
316 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 317 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 318 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
319 | |
320 | if (start) | |
81b3b271 | 321 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 322 | else |
81b3b271 | 323 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 324 | |
7269f933 | 325 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 326 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
327 | } |
328 | ||
890f423b | 329 | static int sh_cmt_enable(struct sh_cmt_channel *ch) |
3fb1b6ad | 330 | { |
3f7e5e24 | 331 | int k, ret; |
3fb1b6ad | 332 | |
7269f933 LP |
333 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
334 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 335 | |
9436b4ab | 336 | /* enable clock */ |
7269f933 | 337 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 338 | if (ret) { |
740a9518 LP |
339 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
340 | ch->index); | |
3f7e5e24 | 341 | goto err0; |
3fb1b6ad | 342 | } |
3fb1b6ad MD |
343 | |
344 | /* make sure channel is disabled */ | |
7269f933 | 345 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
346 | |
347 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 348 | if (ch->cmt->info->width == 16) { |
d14be99b LP |
349 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
350 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 351 | } else { |
d14be99b LP |
352 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
353 | SH_CMT32_CMCSR_CMTOUT_IE | | |
354 | SH_CMT32_CMCSR_CMR_IRQ | | |
355 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 356 | } |
3fb1b6ad | 357 | |
7269f933 LP |
358 | sh_cmt_write_cmcor(ch, 0xffffffff); |
359 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 360 | |
3f7e5e24 MD |
361 | /* |
362 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
363 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
364 | * modifying CMCNT register; two RCLK cycles are necessary before | |
365 | * this register is either read or any modification of the value | |
366 | * it holds is reflected in the LSI's actual operation. | |
367 | * | |
368 | * While at it, we're supposed to clear out the CMCNT as of this | |
369 | * moment, so make sure it's processed properly here. This will | |
370 | * take RCLKx2 at maximum. | |
371 | */ | |
372 | for (k = 0; k < 100; k++) { | |
7269f933 | 373 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
374 | break; |
375 | udelay(1); | |
376 | } | |
377 | ||
7269f933 | 378 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
379 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
380 | ch->index); | |
3f7e5e24 MD |
381 | ret = -ETIMEDOUT; |
382 | goto err1; | |
383 | } | |
384 | ||
3fb1b6ad | 385 | /* enable channel */ |
7269f933 | 386 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 387 | return 0; |
3f7e5e24 MD |
388 | err1: |
389 | /* stop clock */ | |
7269f933 | 390 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
391 | |
392 | err0: | |
393 | return ret; | |
3fb1b6ad MD |
394 | } |
395 | ||
7269f933 | 396 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
397 | { |
398 | /* disable channel */ | |
7269f933 | 399 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 400 | |
be890a1a | 401 | /* disable interrupts in CMT block */ |
7269f933 | 402 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 403 | |
9436b4ab | 404 | /* stop clock */ |
7269f933 | 405 | clk_disable(ch->cmt->clk); |
bad81383 | 406 | |
7269f933 LP |
407 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
408 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
409 | } |
410 | ||
411 | /* private flags */ | |
412 | #define FLAG_CLOCKEVENT (1 << 0) | |
413 | #define FLAG_CLOCKSOURCE (1 << 1) | |
414 | #define FLAG_REPROGRAM (1 << 2) | |
415 | #define FLAG_SKIPEVENT (1 << 3) | |
416 | #define FLAG_IRQCONTEXT (1 << 4) | |
417 | ||
7269f933 | 418 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
419 | int absolute) |
420 | { | |
421 | unsigned long new_match; | |
7269f933 | 422 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
423 | unsigned long delay = 0; |
424 | unsigned long now = 0; | |
425 | int has_wrapped; | |
426 | ||
7269f933 LP |
427 | now = sh_cmt_get_counter(ch, &has_wrapped); |
428 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
429 | |
430 | if (has_wrapped) { | |
431 | /* we're competing with the interrupt handler. | |
432 | * -> let the interrupt handler reprogram the timer. | |
433 | * -> interrupt number two handles the event. | |
434 | */ | |
7269f933 | 435 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
436 | return; |
437 | } | |
438 | ||
439 | if (absolute) | |
440 | now = 0; | |
441 | ||
442 | do { | |
443 | /* reprogram the timer hardware, | |
444 | * but don't save the new match value yet. | |
445 | */ | |
446 | new_match = now + value + delay; | |
7269f933 LP |
447 | if (new_match > ch->max_match_value) |
448 | new_match = ch->max_match_value; | |
3fb1b6ad | 449 | |
7269f933 | 450 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 451 | |
7269f933 LP |
452 | now = sh_cmt_get_counter(ch, &has_wrapped); |
453 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
454 | /* we are changing to a greater match value, |
455 | * so this wrap must be caused by the counter | |
456 | * matching the old value. | |
457 | * -> first interrupt reprograms the timer. | |
458 | * -> interrupt number two handles the event. | |
459 | */ | |
7269f933 | 460 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
461 | break; |
462 | } | |
463 | ||
464 | if (has_wrapped) { | |
465 | /* we are changing to a smaller match value, | |
466 | * so the wrap must be caused by the counter | |
467 | * matching the new value. | |
468 | * -> save programmed match value. | |
469 | * -> let isr handle the event. | |
470 | */ | |
7269f933 | 471 | ch->match_value = new_match; |
3fb1b6ad MD |
472 | break; |
473 | } | |
474 | ||
475 | /* be safe: verify hardware settings */ | |
476 | if (now < new_match) { | |
477 | /* timer value is below match value, all good. | |
478 | * this makes sure we won't miss any match events. | |
479 | * -> save programmed match value. | |
480 | * -> let isr handle the event. | |
481 | */ | |
7269f933 | 482 | ch->match_value = new_match; |
3fb1b6ad MD |
483 | break; |
484 | } | |
485 | ||
486 | /* the counter has reached a value greater | |
487 | * than our new match value. and since the | |
488 | * has_wrapped flag isn't set we must have | |
489 | * programmed a too close event. | |
490 | * -> increase delay and retry. | |
491 | */ | |
492 | if (delay) | |
493 | delay <<= 1; | |
494 | else | |
495 | delay = 1; | |
496 | ||
497 | if (!delay) | |
740a9518 LP |
498 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
499 | ch->index); | |
3fb1b6ad MD |
500 | |
501 | } while (delay); | |
502 | } | |
503 | ||
7269f933 | 504 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 505 | { |
7269f933 | 506 | if (delta > ch->max_match_value) |
740a9518 LP |
507 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
508 | ch->index); | |
3fb1b6ad | 509 | |
7269f933 LP |
510 | ch->next_match_value = delta; |
511 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
512 | } |
513 | ||
7269f933 | 514 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
515 | { |
516 | unsigned long flags; | |
517 | ||
7269f933 LP |
518 | raw_spin_lock_irqsave(&ch->lock, flags); |
519 | __sh_cmt_set_next(ch, delta); | |
520 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
521 | } |
522 | ||
523 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
524 | { | |
7269f933 | 525 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
526 | |
527 | /* clear flags */ | |
2cda3ac4 LP |
528 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
529 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
530 | |
531 | /* update clock source counter to begin with if enabled | |
532 | * the wrap flag should be cleared by the timer specific | |
533 | * isr before we end up here. | |
534 | */ | |
7269f933 LP |
535 | if (ch->flags & FLAG_CLOCKSOURCE) |
536 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 537 | |
7269f933 LP |
538 | if (!(ch->flags & FLAG_REPROGRAM)) |
539 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 540 | |
7269f933 | 541 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 542 | |
7269f933 LP |
543 | if (ch->flags & FLAG_CLOCKEVENT) { |
544 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
051b782e | 545 | if (clockevent_state_oneshot(&ch->ced)) { |
7269f933 LP |
546 | ch->next_match_value = ch->max_match_value; |
547 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
548 | } |
549 | ||
7269f933 | 550 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
551 | } |
552 | } | |
553 | ||
7269f933 | 554 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 555 | |
7269f933 LP |
556 | if (ch->flags & FLAG_REPROGRAM) { |
557 | ch->flags &= ~FLAG_REPROGRAM; | |
558 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 559 | |
7269f933 | 560 | if (ch->flags & FLAG_CLOCKEVENT) |
051b782e | 561 | if ((clockevent_state_shutdown(&ch->ced)) |
7269f933 LP |
562 | || (ch->match_value == ch->next_match_value)) |
563 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
564 | } |
565 | ||
7269f933 | 566 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
567 | |
568 | return IRQ_HANDLED; | |
569 | } | |
570 | ||
7269f933 | 571 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
572 | { |
573 | int ret = 0; | |
574 | unsigned long flags; | |
575 | ||
7269f933 | 576 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 577 | |
7269f933 | 578 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
890f423b | 579 | ret = sh_cmt_enable(ch); |
3fb1b6ad MD |
580 | |
581 | if (ret) | |
582 | goto out; | |
7269f933 | 583 | ch->flags |= flag; |
3fb1b6ad MD |
584 | |
585 | /* setup timeout if no clockevent */ | |
7269f933 LP |
586 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
587 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 588 | out: |
7269f933 | 589 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
590 | |
591 | return ret; | |
592 | } | |
593 | ||
7269f933 | 594 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
595 | { |
596 | unsigned long flags; | |
597 | unsigned long f; | |
598 | ||
7269f933 | 599 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 600 | |
7269f933 LP |
601 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
602 | ch->flags &= ~flag; | |
3fb1b6ad | 603 | |
7269f933 LP |
604 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
605 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
606 | |
607 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
608 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
609 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 610 | |
7269f933 | 611 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
612 | } |
613 | ||
7269f933 | 614 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 615 | { |
7269f933 | 616 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
617 | } |
618 | ||
a5a1d1c2 | 619 | static u64 sh_cmt_clocksource_read(struct clocksource *cs) |
19bdc9d0 | 620 | { |
7269f933 | 621 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
622 | unsigned long flags, raw; |
623 | unsigned long value; | |
624 | int has_wrapped; | |
625 | ||
7269f933 LP |
626 | raw_spin_lock_irqsave(&ch->lock, flags); |
627 | value = ch->total_cycles; | |
628 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
629 | |
630 | if (unlikely(has_wrapped)) | |
7269f933 LP |
631 | raw += ch->match_value + 1; |
632 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
633 | |
634 | return value + raw; | |
635 | } | |
636 | ||
637 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
638 | { | |
3593f5fe | 639 | int ret; |
7269f933 | 640 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 641 | |
7269f933 | 642 | WARN_ON(ch->cs_enabled); |
bad81383 | 643 | |
7269f933 | 644 | ch->total_cycles = 0; |
19bdc9d0 | 645 | |
7269f933 | 646 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
890f423b | 647 | if (!ret) |
7269f933 | 648 | ch->cs_enabled = true; |
890f423b | 649 | |
3593f5fe | 650 | return ret; |
19bdc9d0 MD |
651 | } |
652 | ||
653 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
654 | { | |
7269f933 | 655 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 656 | |
7269f933 | 657 | WARN_ON(!ch->cs_enabled); |
bad81383 | 658 | |
7269f933 LP |
659 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
660 | ch->cs_enabled = false; | |
19bdc9d0 MD |
661 | } |
662 | ||
9bb5ec88 RW |
663 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
664 | { | |
7269f933 | 665 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 666 | |
54d46b7f GU |
667 | if (!ch->cs_enabled) |
668 | return; | |
669 | ||
7269f933 LP |
670 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
671 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
672 | } |
673 | ||
c8162884 MD |
674 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
675 | { | |
7269f933 | 676 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 677 | |
54d46b7f GU |
678 | if (!ch->cs_enabled) |
679 | return; | |
680 | ||
7269f933 LP |
681 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
682 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
683 | } |
684 | ||
7269f933 | 685 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 686 | const char *name) |
19bdc9d0 | 687 | { |
7269f933 | 688 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
689 | |
690 | cs->name = name; | |
fb28a659 | 691 | cs->rating = 125; |
19bdc9d0 MD |
692 | cs->read = sh_cmt_clocksource_read; |
693 | cs->enable = sh_cmt_clocksource_enable; | |
694 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 695 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 696 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
697 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
698 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 699 | |
740a9518 LP |
700 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
701 | ch->index); | |
f4d7c356 | 702 | |
890f423b | 703 | clocksource_register_hz(cs, ch->cmt->rate); |
19bdc9d0 MD |
704 | return 0; |
705 | } | |
706 | ||
7269f933 | 707 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 708 | { |
7269f933 | 709 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
710 | } |
711 | ||
7269f933 | 712 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 713 | { |
7269f933 | 714 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 715 | |
3fb1b6ad | 716 | if (periodic) |
890f423b | 717 | sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 718 | else |
7269f933 | 719 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
720 | } |
721 | ||
051b782e VK |
722 | static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) |
723 | { | |
724 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); | |
725 | ||
726 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); | |
727 | return 0; | |
728 | } | |
729 | ||
730 | static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, | |
731 | int periodic) | |
3fb1b6ad | 732 | { |
7269f933 | 733 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
734 | |
735 | /* deal with old setting first */ | |
051b782e | 736 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
7269f933 | 737 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 738 | |
051b782e VK |
739 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", |
740 | ch->index, periodic ? "periodic" : "oneshot"); | |
741 | sh_cmt_clock_event_start(ch, periodic); | |
742 | return 0; | |
743 | } | |
744 | ||
745 | static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) | |
746 | { | |
747 | return sh_cmt_clock_event_set_state(ced, 0); | |
748 | } | |
749 | ||
750 | static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) | |
751 | { | |
752 | return sh_cmt_clock_event_set_state(ced, 1); | |
3fb1b6ad MD |
753 | } |
754 | ||
755 | static int sh_cmt_clock_event_next(unsigned long delta, | |
756 | struct clock_event_device *ced) | |
757 | { | |
7269f933 | 758 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad | 759 | |
051b782e | 760 | BUG_ON(!clockevent_state_oneshot(ced)); |
7269f933 LP |
761 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
762 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 763 | else |
7269f933 | 764 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
765 | |
766 | return 0; | |
767 | } | |
768 | ||
9bb5ec88 RW |
769 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
770 | { | |
7269f933 | 771 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 772 | |
7269f933 LP |
773 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
774 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
775 | } |
776 | ||
777 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
778 | { | |
7269f933 | 779 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 780 | |
7269f933 LP |
781 | clk_prepare(ch->cmt->clk); |
782 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
783 | } |
784 | ||
bfa76bb1 LP |
785 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
786 | const char *name) | |
3fb1b6ad | 787 | { |
7269f933 | 788 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
789 | int irq; |
790 | int ret; | |
791 | ||
31e912f5 | 792 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
bfa76bb1 LP |
793 | if (irq < 0) { |
794 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", | |
795 | ch->index); | |
796 | return irq; | |
797 | } | |
798 | ||
799 | ret = request_irq(irq, sh_cmt_interrupt, | |
800 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
801 | dev_name(&ch->cmt->pdev->dev), ch); | |
802 | if (ret) { | |
803 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
804 | ch->index, irq); | |
805 | return ret; | |
806 | } | |
3fb1b6ad | 807 | |
3fb1b6ad MD |
808 | ced->name = name; |
809 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
810 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 811 | ced->rating = 125; |
f1ebe1e4 | 812 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad | 813 | ced->set_next_event = sh_cmt_clock_event_next; |
051b782e VK |
814 | ced->set_state_shutdown = sh_cmt_clock_event_shutdown; |
815 | ced->set_state_periodic = sh_cmt_clock_event_set_periodic; | |
816 | ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; | |
9bb5ec88 RW |
817 | ced->suspend = sh_cmt_clock_event_suspend; |
818 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 819 | |
890f423b NS |
820 | /* TODO: calculate good shift from rate and counter bit width */ |
821 | ced->shift = 32; | |
822 | ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); | |
823 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
bb2e94ac | 824 | ced->max_delta_ticks = ch->max_match_value; |
890f423b | 825 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
bb2e94ac | 826 | ced->min_delta_ticks = 0x1f; |
890f423b | 827 | |
740a9518 LP |
828 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
829 | ch->index); | |
3fb1b6ad | 830 | clockevents_register_device(ced); |
bfa76bb1 LP |
831 | |
832 | return 0; | |
3fb1b6ad MD |
833 | } |
834 | ||
1d053e1d | 835 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 836 | bool clockevent, bool clocksource) |
3fb1b6ad | 837 | { |
bfa76bb1 LP |
838 | int ret; |
839 | ||
81b3b271 LP |
840 | if (clockevent) { |
841 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
842 | ret = sh_cmt_register_clockevent(ch, name); |
843 | if (ret < 0) | |
844 | return ret; | |
81b3b271 | 845 | } |
3fb1b6ad | 846 | |
81b3b271 LP |
847 | if (clocksource) { |
848 | ch->cmt->has_clocksource = true; | |
fb28a659 | 849 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 850 | } |
19bdc9d0 | 851 | |
3fb1b6ad MD |
852 | return 0; |
853 | } | |
854 | ||
740a9518 | 855 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
856 | unsigned int hwidx, bool clockevent, |
857 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 858 | { |
b882e7b1 LP |
859 | int ret; |
860 | ||
81b3b271 LP |
861 | /* Skip unused channels. */ |
862 | if (!clockevent && !clocksource) | |
863 | return 0; | |
864 | ||
b882e7b1 | 865 | ch->cmt = cmt; |
740a9518 | 866 | ch->index = index; |
81b3b271 | 867 | ch->hwidx = hwidx; |
83c79a6d | 868 | ch->timer_bit = hwidx; |
81b3b271 LP |
869 | |
870 | /* | |
871 | * Compute the address of the channel control register block. For the | |
872 | * timers with a per-channel start/stop register, compute its address | |
873 | * as well. | |
81b3b271 | 874 | */ |
31e912f5 LP |
875 | switch (cmt->info->model) { |
876 | case SH_CMT_16BIT: | |
877 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
878 | break; | |
879 | case SH_CMT_32BIT: | |
880 | case SH_CMT_48BIT: | |
881 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
882 | break; | |
83c79a6d MD |
883 | case SH_CMT0_RCAR_GEN2: |
884 | case SH_CMT1_RCAR_GEN2: | |
31e912f5 LP |
885 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; |
886 | ch->ioctrl = ch->iostart + 0x10; | |
83c79a6d | 887 | ch->timer_bit = 0; |
31e912f5 | 888 | break; |
81b3b271 LP |
889 | } |
890 | ||
2cda3ac4 | 891 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
892 | ch->max_match_value = ~0; |
893 | else | |
2cda3ac4 | 894 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
895 | |
896 | ch->match_value = ch->max_match_value; | |
897 | raw_spin_lock_init(&ch->lock); | |
898 | ||
1d053e1d | 899 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 900 | clockevent, clocksource); |
b882e7b1 | 901 | if (ret) { |
740a9518 LP |
902 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
903 | ch->index); | |
b882e7b1 LP |
904 | return ret; |
905 | } | |
906 | ch->cs_enabled = false; | |
907 | ||
b882e7b1 LP |
908 | return 0; |
909 | } | |
910 | ||
81b3b271 | 911 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 912 | { |
81b3b271 | 913 | struct resource *mem; |
3fb1b6ad | 914 | |
81b3b271 LP |
915 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
916 | if (!mem) { | |
917 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
918 | return -ENXIO; | |
919 | } | |
3fb1b6ad | 920 | |
81b3b271 LP |
921 | cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); |
922 | if (cmt->mapbase == NULL) { | |
923 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
924 | return -ENXIO; | |
3fb1b6ad MD |
925 | } |
926 | ||
81b3b271 LP |
927 | return 0; |
928 | } | |
929 | ||
1768aa2f LP |
930 | static const struct platform_device_id sh_cmt_id_table[] = { |
931 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
932 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1768aa2f LP |
933 | { } |
934 | }; | |
935 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
936 | ||
937 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
1768aa2f | 938 | { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, |
8d50e947 GU |
939 | { |
940 | /* deprecated, preserved for backward compatibility */ | |
941 | .compatible = "renesas,cmt-48-gen2", | |
942 | .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] | |
943 | }, | |
83c79a6d MD |
944 | { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, |
945 | { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] }, | |
1768aa2f LP |
946 | { } |
947 | }; | |
948 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
949 | ||
81b3b271 LP |
950 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
951 | { | |
31e912f5 LP |
952 | unsigned int mask; |
953 | unsigned int i; | |
81b3b271 LP |
954 | int ret; |
955 | ||
81b3b271 | 956 | cmt->pdev = pdev; |
de599c88 | 957 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 958 | |
1768aa2f | 959 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
2d1d5172 | 960 | cmt->info = of_device_get_match_data(&pdev->dev); |
d1d28597 | 961 | cmt->hw_channels = cmt->info->channels_mask; |
1768aa2f LP |
962 | } else if (pdev->dev.platform_data) { |
963 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
964 | const struct platform_device_id *id = pdev->id_entry; | |
965 | ||
966 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
967 | cmt->hw_channels = cfg->channels_mask; | |
968 | } else { | |
81b3b271 LP |
969 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
970 | return -ENXIO; | |
971 | } | |
972 | ||
81b3b271 | 973 | /* Get hold of clock. */ |
31e912f5 | 974 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
975 | if (IS_ERR(cmt->clk)) { |
976 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 977 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
978 | } |
979 | ||
2653caf4 | 980 | ret = clk_prepare(cmt->clk); |
57dee992 | 981 | if (ret < 0) |
81b3b271 | 982 | goto err_clk_put; |
57dee992 | 983 | |
890f423b NS |
984 | /* Determine clock rate. */ |
985 | ret = clk_enable(cmt->clk); | |
986 | if (ret < 0) | |
987 | goto err_clk_unprepare; | |
988 | ||
989 | if (cmt->info->width == 16) | |
990 | cmt->rate = clk_get_rate(cmt->clk) / 512; | |
991 | else | |
992 | cmt->rate = clk_get_rate(cmt->clk) / 8; | |
993 | ||
994 | clk_disable(cmt->clk); | |
995 | ||
31e912f5 LP |
996 | /* Map the memory resource(s). */ |
997 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 LP |
998 | if (ret < 0) |
999 | goto err_clk_unprepare; | |
1000 | ||
1001 | /* Allocate and setup the channels. */ | |
1768aa2f | 1002 | cmt->num_channels = hweight8(cmt->hw_channels); |
81b3b271 LP |
1003 | cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), |
1004 | GFP_KERNEL); | |
f5ec9b19 LP |
1005 | if (cmt->channels == NULL) { |
1006 | ret = -ENOMEM; | |
81b3b271 | 1007 | goto err_unmap; |
f5ec9b19 LP |
1008 | } |
1009 | ||
31e912f5 LP |
1010 | /* |
1011 | * Use the first channel as a clock event device and the second channel | |
1012 | * as a clock source. If only one channel is available use it for both. | |
1013 | */ | |
1768aa2f | 1014 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1015 | unsigned int hwidx = ffs(mask) - 1; |
1016 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1017 | bool clockevent = i == 0; | |
1018 | ||
1019 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1020 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1021 | if (ret < 0) |
1022 | goto err_unmap; | |
f5ec9b19 | 1023 | |
31e912f5 | 1024 | mask &= ~(1 << hwidx); |
81b3b271 | 1025 | } |
da64c2a8 | 1026 | |
2653caf4 | 1027 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1028 | |
da64c2a8 | 1029 | return 0; |
81b3b271 LP |
1030 | |
1031 | err_unmap: | |
f5ec9b19 | 1032 | kfree(cmt->channels); |
31e912f5 | 1033 | iounmap(cmt->mapbase); |
81b3b271 | 1034 | err_clk_unprepare: |
2653caf4 | 1035 | clk_unprepare(cmt->clk); |
81b3b271 | 1036 | err_clk_put: |
2653caf4 | 1037 | clk_put(cmt->clk); |
3fb1b6ad MD |
1038 | return ret; |
1039 | } | |
1040 | ||
1850514b | 1041 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1042 | { |
2653caf4 | 1043 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1044 | int ret; |
1045 | ||
9bb5ec88 | 1046 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
1047 | pm_runtime_set_active(&pdev->dev); |
1048 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1049 | } |
615a445f | 1050 | |
2653caf4 | 1051 | if (cmt) { |
214a607a | 1052 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1053 | goto out; |
e475eedb MD |
1054 | } |
1055 | ||
b262bc74 | 1056 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1057 | if (cmt == NULL) |
3fb1b6ad | 1058 | return -ENOMEM; |
3fb1b6ad | 1059 | |
2653caf4 | 1060 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1061 | if (ret) { |
2653caf4 | 1062 | kfree(cmt); |
bad81383 RW |
1063 | pm_runtime_idle(&pdev->dev); |
1064 | return ret; | |
3fb1b6ad | 1065 | } |
bad81383 RW |
1066 | if (is_early_platform_device(pdev)) |
1067 | return 0; | |
1068 | ||
1069 | out: | |
81b3b271 | 1070 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1071 | pm_runtime_irq_safe(&pdev->dev); |
1072 | else | |
1073 | pm_runtime_idle(&pdev->dev); | |
1074 | ||
1075 | return 0; | |
3fb1b6ad MD |
1076 | } |
1077 | ||
1850514b | 1078 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1079 | { |
1080 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1081 | } | |
1082 | ||
1083 | static struct platform_driver sh_cmt_device_driver = { | |
1084 | .probe = sh_cmt_probe, | |
1850514b | 1085 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1086 | .driver = { |
1087 | .name = "sh_cmt", | |
1768aa2f | 1088 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
81b3b271 LP |
1089 | }, |
1090 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1091 | }; |
1092 | ||
1093 | static int __init sh_cmt_init(void) | |
1094 | { | |
1095 | return platform_driver_register(&sh_cmt_device_driver); | |
1096 | } | |
1097 | ||
1098 | static void __exit sh_cmt_exit(void) | |
1099 | { | |
1100 | platform_driver_unregister(&sh_cmt_device_driver); | |
1101 | } | |
1102 | ||
e475eedb | 1103 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1104 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1105 | module_exit(sh_cmt_exit); |
1106 | ||
1107 | MODULE_AUTHOR("Magnus Damm"); | |
1108 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1109 | MODULE_LICENSE("GPL v2"); |