]>
Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
3fb1b6ad MD |
14 | */ |
15 | ||
e7a9bcc2 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/clocksource.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
3fb1b6ad | 21 | #include <linux/init.h> |
3fb1b6ad | 22 | #include <linux/interrupt.h> |
3fb1b6ad | 23 | #include <linux/io.h> |
e7a9bcc2 | 24 | #include <linux/ioport.h> |
3fb1b6ad | 25 | #include <linux/irq.h> |
7deeab5d | 26 | #include <linux/module.h> |
1768aa2f | 27 | #include <linux/of.h> |
e7a9bcc2 | 28 | #include <linux/platform_device.h> |
615a445f | 29 | #include <linux/pm_domain.h> |
bad81383 | 30 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
31 | #include <linux/sh_timer.h> |
32 | #include <linux/slab.h> | |
33 | #include <linux/spinlock.h> | |
3fb1b6ad | 34 | |
2653caf4 | 35 | struct sh_cmt_device; |
7269f933 | 36 | |
2cda3ac4 LP |
37 | /* |
38 | * The CMT comes in 5 different identified flavours, depending not only on the | |
39 | * SoC but also on the particular instance. The following table lists the main | |
40 | * characteristics of those flavours. | |
41 | * | |
42 | * 16B 32B 32B-F 48B 48B-2 | |
43 | * ----------------------------------------------------------------------------- | |
44 | * Channels 2 1/4 1 6 2/8 | |
45 | * Control Width 16 16 16 16 32 | |
46 | * Counter Width 16 32 32 32/48 32/48 | |
47 | * Shared Start/Stop Y Y Y Y N | |
48 | * | |
49 | * The 48-bit gen2 version has a per-channel start/stop register located in the | |
50 | * channel registers block. All other versions have a shared start/stop register | |
51 | * located in the global space. | |
52 | * | |
81b3b271 LP |
53 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
54 | * infers the start/stop bit position in the control register and the channel | |
55 | * registers block address. Some CMT instances have a subset of channels | |
56 | * available, in which case the index in the documentation doesn't match the | |
57 | * "real" index as implemented in hardware. This is for instance the case with | |
58 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
59 | * in the documentation but using start/stop bit 5 and having its registers | |
60 | * block at 0x60. | |
61 | * | |
62 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
63 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
64 | */ | |
65 | ||
66 | enum sh_cmt_model { | |
67 | SH_CMT_16BIT, | |
68 | SH_CMT_32BIT, | |
69 | SH_CMT_32BIT_FAST, | |
70 | SH_CMT_48BIT, | |
71 | SH_CMT_48BIT_GEN2, | |
72 | }; | |
73 | ||
74 | struct sh_cmt_info { | |
75 | enum sh_cmt_model model; | |
76 | ||
77 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
78 | unsigned long overflow_bit; | |
79 | unsigned long clear_bits; | |
80 | ||
81 | /* callbacks for CMSTR and CMCSR access */ | |
82 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
83 | void (*write_control)(void __iomem *base, unsigned long offs, | |
84 | unsigned long value); | |
85 | ||
86 | /* callbacks for CMCNT and CMCOR access */ | |
87 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
88 | void (*write_count)(void __iomem *base, unsigned long offs, | |
89 | unsigned long value); | |
90 | }; | |
91 | ||
7269f933 | 92 | struct sh_cmt_channel { |
2653caf4 | 93 | struct sh_cmt_device *cmt; |
3fb1b6ad | 94 | |
81b3b271 LP |
95 | unsigned int index; /* Index in the documentation */ |
96 | unsigned int hwidx; /* Real hardware index */ | |
97 | ||
98 | void __iomem *iostart; | |
99 | void __iomem *ioctrl; | |
c924d2d2 | 100 | |
81b3b271 | 101 | unsigned int timer_bit; |
3fb1b6ad MD |
102 | unsigned long flags; |
103 | unsigned long match_value; | |
104 | unsigned long next_match_value; | |
105 | unsigned long max_match_value; | |
7d0c399f | 106 | raw_spinlock_t lock; |
3fb1b6ad | 107 | struct clock_event_device ced; |
19bdc9d0 | 108 | struct clocksource cs; |
3fb1b6ad | 109 | unsigned long total_cycles; |
bad81383 | 110 | bool cs_enabled; |
7269f933 LP |
111 | }; |
112 | ||
2653caf4 | 113 | struct sh_cmt_device { |
7269f933 LP |
114 | struct platform_device *pdev; |
115 | ||
2cda3ac4 LP |
116 | const struct sh_cmt_info *info; |
117 | ||
7269f933 | 118 | void __iomem *mapbase; |
7269f933 | 119 | struct clk *clk; |
890f423b | 120 | unsigned long rate; |
7269f933 | 121 | |
de599c88 LP |
122 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
123 | ||
f5ec9b19 LP |
124 | struct sh_cmt_channel *channels; |
125 | unsigned int num_channels; | |
1768aa2f | 126 | unsigned int hw_channels; |
81b3b271 LP |
127 | |
128 | bool has_clockevent; | |
129 | bool has_clocksource; | |
3fb1b6ad MD |
130 | }; |
131 | ||
d14be99b LP |
132 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
133 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
134 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
135 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
136 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
137 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
138 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
139 | ||
140 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
141 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
142 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
143 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
144 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
145 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
146 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
147 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
148 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
149 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
150 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
151 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
152 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
153 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
154 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
155 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
156 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
157 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
158 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
159 | ||
a6a912ca | 160 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
161 | { |
162 | return ioread16(base + (offs << 1)); | |
163 | } | |
164 | ||
a6a912ca MD |
165 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
166 | { | |
167 | return ioread32(base + (offs << 2)); | |
168 | } | |
169 | ||
170 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
171 | unsigned long value) | |
587acb3d MD |
172 | { |
173 | iowrite16(value, base + (offs << 1)); | |
174 | } | |
3fb1b6ad | 175 | |
a6a912ca MD |
176 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
177 | unsigned long value) | |
178 | { | |
179 | iowrite32(value, base + (offs << 2)); | |
180 | } | |
181 | ||
2cda3ac4 LP |
182 | static const struct sh_cmt_info sh_cmt_info[] = { |
183 | [SH_CMT_16BIT] = { | |
184 | .model = SH_CMT_16BIT, | |
185 | .width = 16, | |
d14be99b LP |
186 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
187 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
188 | .read_control = sh_cmt_read16, |
189 | .write_control = sh_cmt_write16, | |
190 | .read_count = sh_cmt_read16, | |
191 | .write_count = sh_cmt_write16, | |
192 | }, | |
193 | [SH_CMT_32BIT] = { | |
194 | .model = SH_CMT_32BIT, | |
195 | .width = 32, | |
d14be99b LP |
196 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
197 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
198 | .read_control = sh_cmt_read16, |
199 | .write_control = sh_cmt_write16, | |
200 | .read_count = sh_cmt_read32, | |
201 | .write_count = sh_cmt_write32, | |
202 | }, | |
203 | [SH_CMT_32BIT_FAST] = { | |
204 | .model = SH_CMT_32BIT_FAST, | |
205 | .width = 32, | |
d14be99b LP |
206 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
207 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
208 | .read_control = sh_cmt_read16, |
209 | .write_control = sh_cmt_write16, | |
210 | .read_count = sh_cmt_read32, | |
211 | .write_count = sh_cmt_write32, | |
212 | }, | |
213 | [SH_CMT_48BIT] = { | |
214 | .model = SH_CMT_48BIT, | |
215 | .width = 32, | |
d14be99b LP |
216 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
217 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
218 | .read_control = sh_cmt_read32, |
219 | .write_control = sh_cmt_write32, | |
220 | .read_count = sh_cmt_read32, | |
221 | .write_count = sh_cmt_write32, | |
222 | }, | |
223 | [SH_CMT_48BIT_GEN2] = { | |
224 | .model = SH_CMT_48BIT_GEN2, | |
225 | .width = 32, | |
d14be99b LP |
226 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
227 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
228 | .read_control = sh_cmt_read32, |
229 | .write_control = sh_cmt_write32, | |
230 | .read_count = sh_cmt_read32, | |
231 | .write_count = sh_cmt_write32, | |
232 | }, | |
233 | }; | |
234 | ||
3fb1b6ad MD |
235 | #define CMCSR 0 /* channel register */ |
236 | #define CMCNT 1 /* channel register */ | |
237 | #define CMCOR 2 /* channel register */ | |
238 | ||
7269f933 | 239 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 240 | { |
81b3b271 LP |
241 | if (ch->iostart) |
242 | return ch->cmt->info->read_control(ch->iostart, 0); | |
243 | else | |
244 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
245 | } |
246 | ||
81b3b271 LP |
247 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
248 | unsigned long value) | |
1b56b96b | 249 | { |
81b3b271 LP |
250 | if (ch->iostart) |
251 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
252 | else | |
253 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
254 | } |
255 | ||
81b3b271 | 256 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 257 | { |
81b3b271 | 258 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
259 | } |
260 | ||
81b3b271 | 261 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
262 | unsigned long value) |
263 | { | |
81b3b271 | 264 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
265 | } |
266 | ||
81b3b271 | 267 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 268 | { |
81b3b271 | 269 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
270 | } |
271 | ||
7269f933 | 272 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
273 | unsigned long value) |
274 | { | |
81b3b271 | 275 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
276 | } |
277 | ||
7269f933 | 278 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
279 | unsigned long value) |
280 | { | |
81b3b271 | 281 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
282 | } |
283 | ||
7269f933 | 284 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
285 | int *has_wrapped) |
286 | { | |
287 | unsigned long v1, v2, v3; | |
5b644c7a MD |
288 | int o1, o2; |
289 | ||
2cda3ac4 | 290 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
291 | |
292 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
293 | do { | |
5b644c7a | 294 | o2 = o1; |
7269f933 LP |
295 | v1 = sh_cmt_read_cmcnt(ch); |
296 | v2 = sh_cmt_read_cmcnt(ch); | |
297 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 298 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
299 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
300 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 301 | |
5b644c7a | 302 | *has_wrapped = o1; |
3fb1b6ad MD |
303 | return v2; |
304 | } | |
305 | ||
7269f933 | 306 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 307 | { |
3fb1b6ad MD |
308 | unsigned long flags, value; |
309 | ||
310 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 311 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 312 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
313 | |
314 | if (start) | |
81b3b271 | 315 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 316 | else |
81b3b271 | 317 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 318 | |
7269f933 | 319 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 320 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
321 | } |
322 | ||
890f423b | 323 | static int sh_cmt_enable(struct sh_cmt_channel *ch) |
3fb1b6ad | 324 | { |
3f7e5e24 | 325 | int k, ret; |
3fb1b6ad | 326 | |
7269f933 LP |
327 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
328 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 329 | |
9436b4ab | 330 | /* enable clock */ |
7269f933 | 331 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 332 | if (ret) { |
740a9518 LP |
333 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
334 | ch->index); | |
3f7e5e24 | 335 | goto err0; |
3fb1b6ad | 336 | } |
3fb1b6ad MD |
337 | |
338 | /* make sure channel is disabled */ | |
7269f933 | 339 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
340 | |
341 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 342 | if (ch->cmt->info->width == 16) { |
d14be99b LP |
343 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
344 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 345 | } else { |
d14be99b LP |
346 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
347 | SH_CMT32_CMCSR_CMTOUT_IE | | |
348 | SH_CMT32_CMCSR_CMR_IRQ | | |
349 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 350 | } |
3fb1b6ad | 351 | |
7269f933 LP |
352 | sh_cmt_write_cmcor(ch, 0xffffffff); |
353 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 354 | |
3f7e5e24 MD |
355 | /* |
356 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
357 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
358 | * modifying CMCNT register; two RCLK cycles are necessary before | |
359 | * this register is either read or any modification of the value | |
360 | * it holds is reflected in the LSI's actual operation. | |
361 | * | |
362 | * While at it, we're supposed to clear out the CMCNT as of this | |
363 | * moment, so make sure it's processed properly here. This will | |
364 | * take RCLKx2 at maximum. | |
365 | */ | |
366 | for (k = 0; k < 100; k++) { | |
7269f933 | 367 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
368 | break; |
369 | udelay(1); | |
370 | } | |
371 | ||
7269f933 | 372 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
373 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
374 | ch->index); | |
3f7e5e24 MD |
375 | ret = -ETIMEDOUT; |
376 | goto err1; | |
377 | } | |
378 | ||
3fb1b6ad | 379 | /* enable channel */ |
7269f933 | 380 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 381 | return 0; |
3f7e5e24 MD |
382 | err1: |
383 | /* stop clock */ | |
7269f933 | 384 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
385 | |
386 | err0: | |
387 | return ret; | |
3fb1b6ad MD |
388 | } |
389 | ||
7269f933 | 390 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
391 | { |
392 | /* disable channel */ | |
7269f933 | 393 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 394 | |
be890a1a | 395 | /* disable interrupts in CMT block */ |
7269f933 | 396 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 397 | |
9436b4ab | 398 | /* stop clock */ |
7269f933 | 399 | clk_disable(ch->cmt->clk); |
bad81383 | 400 | |
7269f933 LP |
401 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
402 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
403 | } |
404 | ||
405 | /* private flags */ | |
406 | #define FLAG_CLOCKEVENT (1 << 0) | |
407 | #define FLAG_CLOCKSOURCE (1 << 1) | |
408 | #define FLAG_REPROGRAM (1 << 2) | |
409 | #define FLAG_SKIPEVENT (1 << 3) | |
410 | #define FLAG_IRQCONTEXT (1 << 4) | |
411 | ||
7269f933 | 412 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
413 | int absolute) |
414 | { | |
415 | unsigned long new_match; | |
7269f933 | 416 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
417 | unsigned long delay = 0; |
418 | unsigned long now = 0; | |
419 | int has_wrapped; | |
420 | ||
7269f933 LP |
421 | now = sh_cmt_get_counter(ch, &has_wrapped); |
422 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
423 | |
424 | if (has_wrapped) { | |
425 | /* we're competing with the interrupt handler. | |
426 | * -> let the interrupt handler reprogram the timer. | |
427 | * -> interrupt number two handles the event. | |
428 | */ | |
7269f933 | 429 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
430 | return; |
431 | } | |
432 | ||
433 | if (absolute) | |
434 | now = 0; | |
435 | ||
436 | do { | |
437 | /* reprogram the timer hardware, | |
438 | * but don't save the new match value yet. | |
439 | */ | |
440 | new_match = now + value + delay; | |
7269f933 LP |
441 | if (new_match > ch->max_match_value) |
442 | new_match = ch->max_match_value; | |
3fb1b6ad | 443 | |
7269f933 | 444 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 445 | |
7269f933 LP |
446 | now = sh_cmt_get_counter(ch, &has_wrapped); |
447 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
448 | /* we are changing to a greater match value, |
449 | * so this wrap must be caused by the counter | |
450 | * matching the old value. | |
451 | * -> first interrupt reprograms the timer. | |
452 | * -> interrupt number two handles the event. | |
453 | */ | |
7269f933 | 454 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
455 | break; |
456 | } | |
457 | ||
458 | if (has_wrapped) { | |
459 | /* we are changing to a smaller match value, | |
460 | * so the wrap must be caused by the counter | |
461 | * matching the new value. | |
462 | * -> save programmed match value. | |
463 | * -> let isr handle the event. | |
464 | */ | |
7269f933 | 465 | ch->match_value = new_match; |
3fb1b6ad MD |
466 | break; |
467 | } | |
468 | ||
469 | /* be safe: verify hardware settings */ | |
470 | if (now < new_match) { | |
471 | /* timer value is below match value, all good. | |
472 | * this makes sure we won't miss any match events. | |
473 | * -> save programmed match value. | |
474 | * -> let isr handle the event. | |
475 | */ | |
7269f933 | 476 | ch->match_value = new_match; |
3fb1b6ad MD |
477 | break; |
478 | } | |
479 | ||
480 | /* the counter has reached a value greater | |
481 | * than our new match value. and since the | |
482 | * has_wrapped flag isn't set we must have | |
483 | * programmed a too close event. | |
484 | * -> increase delay and retry. | |
485 | */ | |
486 | if (delay) | |
487 | delay <<= 1; | |
488 | else | |
489 | delay = 1; | |
490 | ||
491 | if (!delay) | |
740a9518 LP |
492 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
493 | ch->index); | |
3fb1b6ad MD |
494 | |
495 | } while (delay); | |
496 | } | |
497 | ||
7269f933 | 498 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 499 | { |
7269f933 | 500 | if (delta > ch->max_match_value) |
740a9518 LP |
501 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
502 | ch->index); | |
3fb1b6ad | 503 | |
7269f933 LP |
504 | ch->next_match_value = delta; |
505 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
506 | } |
507 | ||
7269f933 | 508 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
509 | { |
510 | unsigned long flags; | |
511 | ||
7269f933 LP |
512 | raw_spin_lock_irqsave(&ch->lock, flags); |
513 | __sh_cmt_set_next(ch, delta); | |
514 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
515 | } |
516 | ||
517 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
518 | { | |
7269f933 | 519 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
520 | |
521 | /* clear flags */ | |
2cda3ac4 LP |
522 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
523 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
524 | |
525 | /* update clock source counter to begin with if enabled | |
526 | * the wrap flag should be cleared by the timer specific | |
527 | * isr before we end up here. | |
528 | */ | |
7269f933 LP |
529 | if (ch->flags & FLAG_CLOCKSOURCE) |
530 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 531 | |
7269f933 LP |
532 | if (!(ch->flags & FLAG_REPROGRAM)) |
533 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 534 | |
7269f933 | 535 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 536 | |
7269f933 LP |
537 | if (ch->flags & FLAG_CLOCKEVENT) { |
538 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
051b782e | 539 | if (clockevent_state_oneshot(&ch->ced)) { |
7269f933 LP |
540 | ch->next_match_value = ch->max_match_value; |
541 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
542 | } |
543 | ||
7269f933 | 544 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
545 | } |
546 | } | |
547 | ||
7269f933 | 548 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 549 | |
7269f933 LP |
550 | if (ch->flags & FLAG_REPROGRAM) { |
551 | ch->flags &= ~FLAG_REPROGRAM; | |
552 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 553 | |
7269f933 | 554 | if (ch->flags & FLAG_CLOCKEVENT) |
051b782e | 555 | if ((clockevent_state_shutdown(&ch->ced)) |
7269f933 LP |
556 | || (ch->match_value == ch->next_match_value)) |
557 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
558 | } |
559 | ||
7269f933 | 560 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
561 | |
562 | return IRQ_HANDLED; | |
563 | } | |
564 | ||
7269f933 | 565 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
566 | { |
567 | int ret = 0; | |
568 | unsigned long flags; | |
569 | ||
7269f933 | 570 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 571 | |
7269f933 | 572 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
890f423b | 573 | ret = sh_cmt_enable(ch); |
3fb1b6ad MD |
574 | |
575 | if (ret) | |
576 | goto out; | |
7269f933 | 577 | ch->flags |= flag; |
3fb1b6ad MD |
578 | |
579 | /* setup timeout if no clockevent */ | |
7269f933 LP |
580 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
581 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 582 | out: |
7269f933 | 583 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
584 | |
585 | return ret; | |
586 | } | |
587 | ||
7269f933 | 588 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
589 | { |
590 | unsigned long flags; | |
591 | unsigned long f; | |
592 | ||
7269f933 | 593 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 594 | |
7269f933 LP |
595 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
596 | ch->flags &= ~flag; | |
3fb1b6ad | 597 | |
7269f933 LP |
598 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
599 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
600 | |
601 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
602 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
603 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 604 | |
7269f933 | 605 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
606 | } |
607 | ||
7269f933 | 608 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 609 | { |
7269f933 | 610 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
611 | } |
612 | ||
a5a1d1c2 | 613 | static u64 sh_cmt_clocksource_read(struct clocksource *cs) |
19bdc9d0 | 614 | { |
7269f933 | 615 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
616 | unsigned long flags, raw; |
617 | unsigned long value; | |
618 | int has_wrapped; | |
619 | ||
7269f933 LP |
620 | raw_spin_lock_irqsave(&ch->lock, flags); |
621 | value = ch->total_cycles; | |
622 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
623 | |
624 | if (unlikely(has_wrapped)) | |
7269f933 LP |
625 | raw += ch->match_value + 1; |
626 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
627 | |
628 | return value + raw; | |
629 | } | |
630 | ||
631 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
632 | { | |
3593f5fe | 633 | int ret; |
7269f933 | 634 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 635 | |
7269f933 | 636 | WARN_ON(ch->cs_enabled); |
bad81383 | 637 | |
7269f933 | 638 | ch->total_cycles = 0; |
19bdc9d0 | 639 | |
7269f933 | 640 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
890f423b | 641 | if (!ret) |
7269f933 | 642 | ch->cs_enabled = true; |
890f423b | 643 | |
3593f5fe | 644 | return ret; |
19bdc9d0 MD |
645 | } |
646 | ||
647 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
648 | { | |
7269f933 | 649 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 650 | |
7269f933 | 651 | WARN_ON(!ch->cs_enabled); |
bad81383 | 652 | |
7269f933 LP |
653 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
654 | ch->cs_enabled = false; | |
19bdc9d0 MD |
655 | } |
656 | ||
9bb5ec88 RW |
657 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
658 | { | |
7269f933 | 659 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 660 | |
54d46b7f GU |
661 | if (!ch->cs_enabled) |
662 | return; | |
663 | ||
7269f933 LP |
664 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
665 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
666 | } |
667 | ||
c8162884 MD |
668 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
669 | { | |
7269f933 | 670 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 671 | |
54d46b7f GU |
672 | if (!ch->cs_enabled) |
673 | return; | |
674 | ||
7269f933 LP |
675 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
676 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
677 | } |
678 | ||
7269f933 | 679 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 680 | const char *name) |
19bdc9d0 | 681 | { |
7269f933 | 682 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
683 | |
684 | cs->name = name; | |
fb28a659 | 685 | cs->rating = 125; |
19bdc9d0 MD |
686 | cs->read = sh_cmt_clocksource_read; |
687 | cs->enable = sh_cmt_clocksource_enable; | |
688 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 689 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 690 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
691 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
692 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 693 | |
740a9518 LP |
694 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
695 | ch->index); | |
f4d7c356 | 696 | |
890f423b | 697 | clocksource_register_hz(cs, ch->cmt->rate); |
19bdc9d0 MD |
698 | return 0; |
699 | } | |
700 | ||
7269f933 | 701 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 702 | { |
7269f933 | 703 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
704 | } |
705 | ||
7269f933 | 706 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 707 | { |
7269f933 | 708 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 709 | |
3fb1b6ad | 710 | if (periodic) |
890f423b | 711 | sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 712 | else |
7269f933 | 713 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
714 | } |
715 | ||
051b782e VK |
716 | static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced) |
717 | { | |
718 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); | |
719 | ||
720 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); | |
721 | return 0; | |
722 | } | |
723 | ||
724 | static int sh_cmt_clock_event_set_state(struct clock_event_device *ced, | |
725 | int periodic) | |
3fb1b6ad | 726 | { |
7269f933 | 727 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
728 | |
729 | /* deal with old setting first */ | |
051b782e | 730 | if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
7269f933 | 731 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad | 732 | |
051b782e VK |
733 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", |
734 | ch->index, periodic ? "periodic" : "oneshot"); | |
735 | sh_cmt_clock_event_start(ch, periodic); | |
736 | return 0; | |
737 | } | |
738 | ||
739 | static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced) | |
740 | { | |
741 | return sh_cmt_clock_event_set_state(ced, 0); | |
742 | } | |
743 | ||
744 | static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced) | |
745 | { | |
746 | return sh_cmt_clock_event_set_state(ced, 1); | |
3fb1b6ad MD |
747 | } |
748 | ||
749 | static int sh_cmt_clock_event_next(unsigned long delta, | |
750 | struct clock_event_device *ced) | |
751 | { | |
7269f933 | 752 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad | 753 | |
051b782e | 754 | BUG_ON(!clockevent_state_oneshot(ced)); |
7269f933 LP |
755 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
756 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 757 | else |
7269f933 | 758 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
759 | |
760 | return 0; | |
761 | } | |
762 | ||
9bb5ec88 RW |
763 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
764 | { | |
7269f933 | 765 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 766 | |
7269f933 LP |
767 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
768 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
769 | } |
770 | ||
771 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
772 | { | |
7269f933 | 773 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 774 | |
7269f933 LP |
775 | clk_prepare(ch->cmt->clk); |
776 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
777 | } |
778 | ||
bfa76bb1 LP |
779 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
780 | const char *name) | |
3fb1b6ad | 781 | { |
7269f933 | 782 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
783 | int irq; |
784 | int ret; | |
785 | ||
31e912f5 | 786 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
bfa76bb1 LP |
787 | if (irq < 0) { |
788 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", | |
789 | ch->index); | |
790 | return irq; | |
791 | } | |
792 | ||
793 | ret = request_irq(irq, sh_cmt_interrupt, | |
794 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
795 | dev_name(&ch->cmt->pdev->dev), ch); | |
796 | if (ret) { | |
797 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
798 | ch->index, irq); | |
799 | return ret; | |
800 | } | |
3fb1b6ad | 801 | |
3fb1b6ad MD |
802 | ced->name = name; |
803 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
804 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 805 | ced->rating = 125; |
f1ebe1e4 | 806 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad | 807 | ced->set_next_event = sh_cmt_clock_event_next; |
051b782e VK |
808 | ced->set_state_shutdown = sh_cmt_clock_event_shutdown; |
809 | ced->set_state_periodic = sh_cmt_clock_event_set_periodic; | |
810 | ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; | |
9bb5ec88 RW |
811 | ced->suspend = sh_cmt_clock_event_suspend; |
812 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 813 | |
890f423b NS |
814 | /* TODO: calculate good shift from rate and counter bit width */ |
815 | ced->shift = 32; | |
816 | ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); | |
817 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
818 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); | |
819 | ||
740a9518 LP |
820 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
821 | ch->index); | |
3fb1b6ad | 822 | clockevents_register_device(ced); |
bfa76bb1 LP |
823 | |
824 | return 0; | |
3fb1b6ad MD |
825 | } |
826 | ||
1d053e1d | 827 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 828 | bool clockevent, bool clocksource) |
3fb1b6ad | 829 | { |
bfa76bb1 LP |
830 | int ret; |
831 | ||
81b3b271 LP |
832 | if (clockevent) { |
833 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
834 | ret = sh_cmt_register_clockevent(ch, name); |
835 | if (ret < 0) | |
836 | return ret; | |
81b3b271 | 837 | } |
3fb1b6ad | 838 | |
81b3b271 LP |
839 | if (clocksource) { |
840 | ch->cmt->has_clocksource = true; | |
fb28a659 | 841 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 842 | } |
19bdc9d0 | 843 | |
3fb1b6ad MD |
844 | return 0; |
845 | } | |
846 | ||
740a9518 | 847 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
848 | unsigned int hwidx, bool clockevent, |
849 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 850 | { |
b882e7b1 LP |
851 | int ret; |
852 | ||
81b3b271 LP |
853 | /* Skip unused channels. */ |
854 | if (!clockevent && !clocksource) | |
855 | return 0; | |
856 | ||
b882e7b1 | 857 | ch->cmt = cmt; |
740a9518 | 858 | ch->index = index; |
81b3b271 LP |
859 | ch->hwidx = hwidx; |
860 | ||
861 | /* | |
862 | * Compute the address of the channel control register block. For the | |
863 | * timers with a per-channel start/stop register, compute its address | |
864 | * as well. | |
81b3b271 | 865 | */ |
31e912f5 LP |
866 | switch (cmt->info->model) { |
867 | case SH_CMT_16BIT: | |
868 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
869 | break; | |
870 | case SH_CMT_32BIT: | |
871 | case SH_CMT_48BIT: | |
872 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
873 | break; | |
874 | case SH_CMT_32BIT_FAST: | |
875 | /* | |
876 | * The 32-bit "fast" timer has a single channel at hwidx 5 but | |
877 | * is located at offset 0x40 instead of 0x60 for some reason. | |
878 | */ | |
879 | ch->ioctrl = cmt->mapbase + 0x40; | |
880 | break; | |
881 | case SH_CMT_48BIT_GEN2: | |
882 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; | |
883 | ch->ioctrl = ch->iostart + 0x10; | |
884 | break; | |
81b3b271 LP |
885 | } |
886 | ||
2cda3ac4 | 887 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
888 | ch->max_match_value = ~0; |
889 | else | |
2cda3ac4 | 890 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
891 | |
892 | ch->match_value = ch->max_match_value; | |
893 | raw_spin_lock_init(&ch->lock); | |
894 | ||
31e912f5 | 895 | ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; |
81b3b271 | 896 | |
1d053e1d | 897 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 898 | clockevent, clocksource); |
b882e7b1 | 899 | if (ret) { |
740a9518 LP |
900 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
901 | ch->index); | |
b882e7b1 LP |
902 | return ret; |
903 | } | |
904 | ch->cs_enabled = false; | |
905 | ||
b882e7b1 LP |
906 | return 0; |
907 | } | |
908 | ||
81b3b271 | 909 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 910 | { |
81b3b271 | 911 | struct resource *mem; |
3fb1b6ad | 912 | |
81b3b271 LP |
913 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
914 | if (!mem) { | |
915 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
916 | return -ENXIO; | |
917 | } | |
3fb1b6ad | 918 | |
81b3b271 LP |
919 | cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); |
920 | if (cmt->mapbase == NULL) { | |
921 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
922 | return -ENXIO; | |
3fb1b6ad MD |
923 | } |
924 | ||
81b3b271 LP |
925 | return 0; |
926 | } | |
927 | ||
1768aa2f LP |
928 | static const struct platform_device_id sh_cmt_id_table[] = { |
929 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
930 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1768aa2f LP |
931 | { } |
932 | }; | |
933 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
934 | ||
935 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
936 | { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] }, | |
937 | { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, | |
938 | { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, | |
939 | { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, | |
940 | { } | |
941 | }; | |
942 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
943 | ||
944 | static int sh_cmt_parse_dt(struct sh_cmt_device *cmt) | |
945 | { | |
946 | struct device_node *np = cmt->pdev->dev.of_node; | |
947 | ||
948 | return of_property_read_u32(np, "renesas,channels-mask", | |
949 | &cmt->hw_channels); | |
950 | } | |
951 | ||
81b3b271 LP |
952 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
953 | { | |
31e912f5 LP |
954 | unsigned int mask; |
955 | unsigned int i; | |
81b3b271 LP |
956 | int ret; |
957 | ||
81b3b271 | 958 | cmt->pdev = pdev; |
de599c88 | 959 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 960 | |
1768aa2f LP |
961 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
962 | const struct of_device_id *id; | |
963 | ||
964 | id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); | |
965 | cmt->info = id->data; | |
966 | ||
967 | ret = sh_cmt_parse_dt(cmt); | |
968 | if (ret < 0) | |
969 | return ret; | |
970 | } else if (pdev->dev.platform_data) { | |
971 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
972 | const struct platform_device_id *id = pdev->id_entry; | |
973 | ||
974 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
975 | cmt->hw_channels = cfg->channels_mask; | |
976 | } else { | |
81b3b271 LP |
977 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
978 | return -ENXIO; | |
979 | } | |
980 | ||
81b3b271 | 981 | /* Get hold of clock. */ |
31e912f5 | 982 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
983 | if (IS_ERR(cmt->clk)) { |
984 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 985 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
986 | } |
987 | ||
2653caf4 | 988 | ret = clk_prepare(cmt->clk); |
57dee992 | 989 | if (ret < 0) |
81b3b271 | 990 | goto err_clk_put; |
57dee992 | 991 | |
890f423b NS |
992 | /* Determine clock rate. */ |
993 | ret = clk_enable(cmt->clk); | |
994 | if (ret < 0) | |
995 | goto err_clk_unprepare; | |
996 | ||
997 | if (cmt->info->width == 16) | |
998 | cmt->rate = clk_get_rate(cmt->clk) / 512; | |
999 | else | |
1000 | cmt->rate = clk_get_rate(cmt->clk) / 8; | |
1001 | ||
1002 | clk_disable(cmt->clk); | |
1003 | ||
31e912f5 LP |
1004 | /* Map the memory resource(s). */ |
1005 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 LP |
1006 | if (ret < 0) |
1007 | goto err_clk_unprepare; | |
1008 | ||
1009 | /* Allocate and setup the channels. */ | |
1768aa2f | 1010 | cmt->num_channels = hweight8(cmt->hw_channels); |
81b3b271 LP |
1011 | cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), |
1012 | GFP_KERNEL); | |
f5ec9b19 LP |
1013 | if (cmt->channels == NULL) { |
1014 | ret = -ENOMEM; | |
81b3b271 | 1015 | goto err_unmap; |
f5ec9b19 LP |
1016 | } |
1017 | ||
31e912f5 LP |
1018 | /* |
1019 | * Use the first channel as a clock event device and the second channel | |
1020 | * as a clock source. If only one channel is available use it for both. | |
1021 | */ | |
1768aa2f | 1022 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1023 | unsigned int hwidx = ffs(mask) - 1; |
1024 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1025 | bool clockevent = i == 0; | |
1026 | ||
1027 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1028 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1029 | if (ret < 0) |
1030 | goto err_unmap; | |
f5ec9b19 | 1031 | |
31e912f5 | 1032 | mask &= ~(1 << hwidx); |
81b3b271 | 1033 | } |
da64c2a8 | 1034 | |
2653caf4 | 1035 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1036 | |
da64c2a8 | 1037 | return 0; |
81b3b271 LP |
1038 | |
1039 | err_unmap: | |
f5ec9b19 | 1040 | kfree(cmt->channels); |
31e912f5 | 1041 | iounmap(cmt->mapbase); |
81b3b271 | 1042 | err_clk_unprepare: |
2653caf4 | 1043 | clk_unprepare(cmt->clk); |
81b3b271 | 1044 | err_clk_put: |
2653caf4 | 1045 | clk_put(cmt->clk); |
3fb1b6ad MD |
1046 | return ret; |
1047 | } | |
1048 | ||
1850514b | 1049 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1050 | { |
2653caf4 | 1051 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1052 | int ret; |
1053 | ||
9bb5ec88 | 1054 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
1055 | pm_runtime_set_active(&pdev->dev); |
1056 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1057 | } |
615a445f | 1058 | |
2653caf4 | 1059 | if (cmt) { |
214a607a | 1060 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1061 | goto out; |
e475eedb MD |
1062 | } |
1063 | ||
b262bc74 | 1064 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1065 | if (cmt == NULL) |
3fb1b6ad | 1066 | return -ENOMEM; |
3fb1b6ad | 1067 | |
2653caf4 | 1068 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1069 | if (ret) { |
2653caf4 | 1070 | kfree(cmt); |
bad81383 RW |
1071 | pm_runtime_idle(&pdev->dev); |
1072 | return ret; | |
3fb1b6ad | 1073 | } |
bad81383 RW |
1074 | if (is_early_platform_device(pdev)) |
1075 | return 0; | |
1076 | ||
1077 | out: | |
81b3b271 | 1078 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1079 | pm_runtime_irq_safe(&pdev->dev); |
1080 | else | |
1081 | pm_runtime_idle(&pdev->dev); | |
1082 | ||
1083 | return 0; | |
3fb1b6ad MD |
1084 | } |
1085 | ||
1850514b | 1086 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1087 | { |
1088 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1089 | } | |
1090 | ||
1091 | static struct platform_driver sh_cmt_device_driver = { | |
1092 | .probe = sh_cmt_probe, | |
1850514b | 1093 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1094 | .driver = { |
1095 | .name = "sh_cmt", | |
1768aa2f | 1096 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
81b3b271 LP |
1097 | }, |
1098 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1099 | }; |
1100 | ||
1101 | static int __init sh_cmt_init(void) | |
1102 | { | |
1103 | return platform_driver_register(&sh_cmt_device_driver); | |
1104 | } | |
1105 | ||
1106 | static void __exit sh_cmt_exit(void) | |
1107 | { | |
1108 | platform_driver_unregister(&sh_cmt_device_driver); | |
1109 | } | |
1110 | ||
e475eedb | 1111 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1112 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1113 | module_exit(sh_cmt_exit); |
1114 | ||
1115 | MODULE_AUTHOR("Magnus Damm"); | |
1116 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1117 | MODULE_LICENSE("GPL v2"); |