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Commit | Line | Data |
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3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
3fb1b6ad MD |
14 | */ |
15 | ||
e7a9bcc2 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/clocksource.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
3fb1b6ad | 21 | #include <linux/init.h> |
3fb1b6ad | 22 | #include <linux/interrupt.h> |
3fb1b6ad | 23 | #include <linux/io.h> |
e7a9bcc2 | 24 | #include <linux/ioport.h> |
3fb1b6ad | 25 | #include <linux/irq.h> |
7deeab5d | 26 | #include <linux/module.h> |
1768aa2f | 27 | #include <linux/of.h> |
e7a9bcc2 | 28 | #include <linux/platform_device.h> |
615a445f | 29 | #include <linux/pm_domain.h> |
bad81383 | 30 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
31 | #include <linux/sh_timer.h> |
32 | #include <linux/slab.h> | |
33 | #include <linux/spinlock.h> | |
3fb1b6ad | 34 | |
2653caf4 | 35 | struct sh_cmt_device; |
7269f933 | 36 | |
2cda3ac4 LP |
37 | /* |
38 | * The CMT comes in 5 different identified flavours, depending not only on the | |
39 | * SoC but also on the particular instance. The following table lists the main | |
40 | * characteristics of those flavours. | |
41 | * | |
42 | * 16B 32B 32B-F 48B 48B-2 | |
43 | * ----------------------------------------------------------------------------- | |
44 | * Channels 2 1/4 1 6 2/8 | |
45 | * Control Width 16 16 16 16 32 | |
46 | * Counter Width 16 32 32 32/48 32/48 | |
47 | * Shared Start/Stop Y Y Y Y N | |
48 | * | |
49 | * The 48-bit gen2 version has a per-channel start/stop register located in the | |
50 | * channel registers block. All other versions have a shared start/stop register | |
51 | * located in the global space. | |
52 | * | |
81b3b271 LP |
53 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
54 | * infers the start/stop bit position in the control register and the channel | |
55 | * registers block address. Some CMT instances have a subset of channels | |
56 | * available, in which case the index in the documentation doesn't match the | |
57 | * "real" index as implemented in hardware. This is for instance the case with | |
58 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
59 | * in the documentation but using start/stop bit 5 and having its registers | |
60 | * block at 0x60. | |
61 | * | |
62 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
63 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
64 | */ | |
65 | ||
66 | enum sh_cmt_model { | |
67 | SH_CMT_16BIT, | |
68 | SH_CMT_32BIT, | |
69 | SH_CMT_32BIT_FAST, | |
70 | SH_CMT_48BIT, | |
71 | SH_CMT_48BIT_GEN2, | |
72 | }; | |
73 | ||
74 | struct sh_cmt_info { | |
75 | enum sh_cmt_model model; | |
76 | ||
77 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
78 | unsigned long overflow_bit; | |
79 | unsigned long clear_bits; | |
80 | ||
81 | /* callbacks for CMSTR and CMCSR access */ | |
82 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
83 | void (*write_control)(void __iomem *base, unsigned long offs, | |
84 | unsigned long value); | |
85 | ||
86 | /* callbacks for CMCNT and CMCOR access */ | |
87 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
88 | void (*write_count)(void __iomem *base, unsigned long offs, | |
89 | unsigned long value); | |
90 | }; | |
91 | ||
7269f933 | 92 | struct sh_cmt_channel { |
2653caf4 | 93 | struct sh_cmt_device *cmt; |
3fb1b6ad | 94 | |
81b3b271 LP |
95 | unsigned int index; /* Index in the documentation */ |
96 | unsigned int hwidx; /* Real hardware index */ | |
97 | ||
98 | void __iomem *iostart; | |
99 | void __iomem *ioctrl; | |
c924d2d2 | 100 | |
81b3b271 | 101 | unsigned int timer_bit; |
3fb1b6ad MD |
102 | unsigned long flags; |
103 | unsigned long match_value; | |
104 | unsigned long next_match_value; | |
105 | unsigned long max_match_value; | |
106 | unsigned long rate; | |
7d0c399f | 107 | raw_spinlock_t lock; |
3fb1b6ad | 108 | struct clock_event_device ced; |
19bdc9d0 | 109 | struct clocksource cs; |
3fb1b6ad | 110 | unsigned long total_cycles; |
bad81383 | 111 | bool cs_enabled; |
7269f933 LP |
112 | }; |
113 | ||
2653caf4 | 114 | struct sh_cmt_device { |
7269f933 LP |
115 | struct platform_device *pdev; |
116 | ||
2cda3ac4 LP |
117 | const struct sh_cmt_info *info; |
118 | ||
7269f933 | 119 | void __iomem *mapbase; |
7269f933 LP |
120 | struct clk *clk; |
121 | ||
de599c88 LP |
122 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
123 | ||
f5ec9b19 LP |
124 | struct sh_cmt_channel *channels; |
125 | unsigned int num_channels; | |
1768aa2f | 126 | unsigned int hw_channels; |
81b3b271 LP |
127 | |
128 | bool has_clockevent; | |
129 | bool has_clocksource; | |
3fb1b6ad MD |
130 | }; |
131 | ||
d14be99b LP |
132 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
133 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
134 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
135 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
136 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
137 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
138 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
139 | ||
140 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
141 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
142 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
143 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
144 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
145 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
146 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
147 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
148 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
149 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
150 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
151 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
152 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
153 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
154 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
155 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
156 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
157 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
158 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
159 | ||
a6a912ca | 160 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
161 | { |
162 | return ioread16(base + (offs << 1)); | |
163 | } | |
164 | ||
a6a912ca MD |
165 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
166 | { | |
167 | return ioread32(base + (offs << 2)); | |
168 | } | |
169 | ||
170 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
171 | unsigned long value) | |
587acb3d MD |
172 | { |
173 | iowrite16(value, base + (offs << 1)); | |
174 | } | |
3fb1b6ad | 175 | |
a6a912ca MD |
176 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
177 | unsigned long value) | |
178 | { | |
179 | iowrite32(value, base + (offs << 2)); | |
180 | } | |
181 | ||
2cda3ac4 LP |
182 | static const struct sh_cmt_info sh_cmt_info[] = { |
183 | [SH_CMT_16BIT] = { | |
184 | .model = SH_CMT_16BIT, | |
185 | .width = 16, | |
d14be99b LP |
186 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
187 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
188 | .read_control = sh_cmt_read16, |
189 | .write_control = sh_cmt_write16, | |
190 | .read_count = sh_cmt_read16, | |
191 | .write_count = sh_cmt_write16, | |
192 | }, | |
193 | [SH_CMT_32BIT] = { | |
194 | .model = SH_CMT_32BIT, | |
195 | .width = 32, | |
d14be99b LP |
196 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
197 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
198 | .read_control = sh_cmt_read16, |
199 | .write_control = sh_cmt_write16, | |
200 | .read_count = sh_cmt_read32, | |
201 | .write_count = sh_cmt_write32, | |
202 | }, | |
203 | [SH_CMT_32BIT_FAST] = { | |
204 | .model = SH_CMT_32BIT_FAST, | |
205 | .width = 32, | |
d14be99b LP |
206 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
207 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
208 | .read_control = sh_cmt_read16, |
209 | .write_control = sh_cmt_write16, | |
210 | .read_count = sh_cmt_read32, | |
211 | .write_count = sh_cmt_write32, | |
212 | }, | |
213 | [SH_CMT_48BIT] = { | |
214 | .model = SH_CMT_48BIT, | |
215 | .width = 32, | |
d14be99b LP |
216 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
217 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
218 | .read_control = sh_cmt_read32, |
219 | .write_control = sh_cmt_write32, | |
220 | .read_count = sh_cmt_read32, | |
221 | .write_count = sh_cmt_write32, | |
222 | }, | |
223 | [SH_CMT_48BIT_GEN2] = { | |
224 | .model = SH_CMT_48BIT_GEN2, | |
225 | .width = 32, | |
d14be99b LP |
226 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
227 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
228 | .read_control = sh_cmt_read32, |
229 | .write_control = sh_cmt_write32, | |
230 | .read_count = sh_cmt_read32, | |
231 | .write_count = sh_cmt_write32, | |
232 | }, | |
233 | }; | |
234 | ||
3fb1b6ad MD |
235 | #define CMCSR 0 /* channel register */ |
236 | #define CMCNT 1 /* channel register */ | |
237 | #define CMCOR 2 /* channel register */ | |
238 | ||
7269f933 | 239 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 240 | { |
81b3b271 LP |
241 | if (ch->iostart) |
242 | return ch->cmt->info->read_control(ch->iostart, 0); | |
243 | else | |
244 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
245 | } |
246 | ||
81b3b271 LP |
247 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
248 | unsigned long value) | |
1b56b96b | 249 | { |
81b3b271 LP |
250 | if (ch->iostart) |
251 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
252 | else | |
253 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
254 | } |
255 | ||
81b3b271 | 256 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 257 | { |
81b3b271 | 258 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
259 | } |
260 | ||
81b3b271 | 261 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
262 | unsigned long value) |
263 | { | |
81b3b271 | 264 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
265 | } |
266 | ||
81b3b271 | 267 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 268 | { |
81b3b271 | 269 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
270 | } |
271 | ||
7269f933 | 272 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
273 | unsigned long value) |
274 | { | |
81b3b271 | 275 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
276 | } |
277 | ||
7269f933 | 278 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
279 | unsigned long value) |
280 | { | |
81b3b271 | 281 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
282 | } |
283 | ||
7269f933 | 284 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
285 | int *has_wrapped) |
286 | { | |
287 | unsigned long v1, v2, v3; | |
5b644c7a MD |
288 | int o1, o2; |
289 | ||
2cda3ac4 | 290 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
291 | |
292 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
293 | do { | |
5b644c7a | 294 | o2 = o1; |
7269f933 LP |
295 | v1 = sh_cmt_read_cmcnt(ch); |
296 | v2 = sh_cmt_read_cmcnt(ch); | |
297 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 298 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
299 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
300 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 301 | |
5b644c7a | 302 | *has_wrapped = o1; |
3fb1b6ad MD |
303 | return v2; |
304 | } | |
305 | ||
7269f933 | 306 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 307 | { |
3fb1b6ad MD |
308 | unsigned long flags, value; |
309 | ||
310 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 311 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 312 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
313 | |
314 | if (start) | |
81b3b271 | 315 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 316 | else |
81b3b271 | 317 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 318 | |
7269f933 | 319 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 320 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
321 | } |
322 | ||
7269f933 | 323 | static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) |
3fb1b6ad | 324 | { |
3f7e5e24 | 325 | int k, ret; |
3fb1b6ad | 326 | |
7269f933 LP |
327 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
328 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 329 | |
9436b4ab | 330 | /* enable clock */ |
7269f933 | 331 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 332 | if (ret) { |
740a9518 LP |
333 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
334 | ch->index); | |
3f7e5e24 | 335 | goto err0; |
3fb1b6ad | 336 | } |
3fb1b6ad MD |
337 | |
338 | /* make sure channel is disabled */ | |
7269f933 | 339 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
340 | |
341 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 342 | if (ch->cmt->info->width == 16) { |
7269f933 | 343 | *rate = clk_get_rate(ch->cmt->clk) / 512; |
d14be99b LP |
344 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
345 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 346 | } else { |
7269f933 | 347 | *rate = clk_get_rate(ch->cmt->clk) / 8; |
d14be99b LP |
348 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
349 | SH_CMT32_CMCSR_CMTOUT_IE | | |
350 | SH_CMT32_CMCSR_CMR_IRQ | | |
351 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 352 | } |
3fb1b6ad | 353 | |
7269f933 LP |
354 | sh_cmt_write_cmcor(ch, 0xffffffff); |
355 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 356 | |
3f7e5e24 MD |
357 | /* |
358 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
359 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
360 | * modifying CMCNT register; two RCLK cycles are necessary before | |
361 | * this register is either read or any modification of the value | |
362 | * it holds is reflected in the LSI's actual operation. | |
363 | * | |
364 | * While at it, we're supposed to clear out the CMCNT as of this | |
365 | * moment, so make sure it's processed properly here. This will | |
366 | * take RCLKx2 at maximum. | |
367 | */ | |
368 | for (k = 0; k < 100; k++) { | |
7269f933 | 369 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
370 | break; |
371 | udelay(1); | |
372 | } | |
373 | ||
7269f933 | 374 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
375 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
376 | ch->index); | |
3f7e5e24 MD |
377 | ret = -ETIMEDOUT; |
378 | goto err1; | |
379 | } | |
380 | ||
3fb1b6ad | 381 | /* enable channel */ |
7269f933 | 382 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 383 | return 0; |
3f7e5e24 MD |
384 | err1: |
385 | /* stop clock */ | |
7269f933 | 386 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
387 | |
388 | err0: | |
389 | return ret; | |
3fb1b6ad MD |
390 | } |
391 | ||
7269f933 | 392 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
393 | { |
394 | /* disable channel */ | |
7269f933 | 395 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 396 | |
be890a1a | 397 | /* disable interrupts in CMT block */ |
7269f933 | 398 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 399 | |
9436b4ab | 400 | /* stop clock */ |
7269f933 | 401 | clk_disable(ch->cmt->clk); |
bad81383 | 402 | |
7269f933 LP |
403 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
404 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
405 | } |
406 | ||
407 | /* private flags */ | |
408 | #define FLAG_CLOCKEVENT (1 << 0) | |
409 | #define FLAG_CLOCKSOURCE (1 << 1) | |
410 | #define FLAG_REPROGRAM (1 << 2) | |
411 | #define FLAG_SKIPEVENT (1 << 3) | |
412 | #define FLAG_IRQCONTEXT (1 << 4) | |
413 | ||
7269f933 | 414 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
415 | int absolute) |
416 | { | |
417 | unsigned long new_match; | |
7269f933 | 418 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
419 | unsigned long delay = 0; |
420 | unsigned long now = 0; | |
421 | int has_wrapped; | |
422 | ||
7269f933 LP |
423 | now = sh_cmt_get_counter(ch, &has_wrapped); |
424 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
425 | |
426 | if (has_wrapped) { | |
427 | /* we're competing with the interrupt handler. | |
428 | * -> let the interrupt handler reprogram the timer. | |
429 | * -> interrupt number two handles the event. | |
430 | */ | |
7269f933 | 431 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
432 | return; |
433 | } | |
434 | ||
435 | if (absolute) | |
436 | now = 0; | |
437 | ||
438 | do { | |
439 | /* reprogram the timer hardware, | |
440 | * but don't save the new match value yet. | |
441 | */ | |
442 | new_match = now + value + delay; | |
7269f933 LP |
443 | if (new_match > ch->max_match_value) |
444 | new_match = ch->max_match_value; | |
3fb1b6ad | 445 | |
7269f933 | 446 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 447 | |
7269f933 LP |
448 | now = sh_cmt_get_counter(ch, &has_wrapped); |
449 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
450 | /* we are changing to a greater match value, |
451 | * so this wrap must be caused by the counter | |
452 | * matching the old value. | |
453 | * -> first interrupt reprograms the timer. | |
454 | * -> interrupt number two handles the event. | |
455 | */ | |
7269f933 | 456 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
457 | break; |
458 | } | |
459 | ||
460 | if (has_wrapped) { | |
461 | /* we are changing to a smaller match value, | |
462 | * so the wrap must be caused by the counter | |
463 | * matching the new value. | |
464 | * -> save programmed match value. | |
465 | * -> let isr handle the event. | |
466 | */ | |
7269f933 | 467 | ch->match_value = new_match; |
3fb1b6ad MD |
468 | break; |
469 | } | |
470 | ||
471 | /* be safe: verify hardware settings */ | |
472 | if (now < new_match) { | |
473 | /* timer value is below match value, all good. | |
474 | * this makes sure we won't miss any match events. | |
475 | * -> save programmed match value. | |
476 | * -> let isr handle the event. | |
477 | */ | |
7269f933 | 478 | ch->match_value = new_match; |
3fb1b6ad MD |
479 | break; |
480 | } | |
481 | ||
482 | /* the counter has reached a value greater | |
483 | * than our new match value. and since the | |
484 | * has_wrapped flag isn't set we must have | |
485 | * programmed a too close event. | |
486 | * -> increase delay and retry. | |
487 | */ | |
488 | if (delay) | |
489 | delay <<= 1; | |
490 | else | |
491 | delay = 1; | |
492 | ||
493 | if (!delay) | |
740a9518 LP |
494 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
495 | ch->index); | |
3fb1b6ad MD |
496 | |
497 | } while (delay); | |
498 | } | |
499 | ||
7269f933 | 500 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 501 | { |
7269f933 | 502 | if (delta > ch->max_match_value) |
740a9518 LP |
503 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
504 | ch->index); | |
3fb1b6ad | 505 | |
7269f933 LP |
506 | ch->next_match_value = delta; |
507 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
508 | } |
509 | ||
7269f933 | 510 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
511 | { |
512 | unsigned long flags; | |
513 | ||
7269f933 LP |
514 | raw_spin_lock_irqsave(&ch->lock, flags); |
515 | __sh_cmt_set_next(ch, delta); | |
516 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
517 | } |
518 | ||
519 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
520 | { | |
7269f933 | 521 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
522 | |
523 | /* clear flags */ | |
2cda3ac4 LP |
524 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
525 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
526 | |
527 | /* update clock source counter to begin with if enabled | |
528 | * the wrap flag should be cleared by the timer specific | |
529 | * isr before we end up here. | |
530 | */ | |
7269f933 LP |
531 | if (ch->flags & FLAG_CLOCKSOURCE) |
532 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 533 | |
7269f933 LP |
534 | if (!(ch->flags & FLAG_REPROGRAM)) |
535 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 536 | |
7269f933 | 537 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 538 | |
7269f933 LP |
539 | if (ch->flags & FLAG_CLOCKEVENT) { |
540 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
541 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
542 | ch->next_match_value = ch->max_match_value; | |
543 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
544 | } |
545 | ||
7269f933 | 546 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
547 | } |
548 | } | |
549 | ||
7269f933 | 550 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 551 | |
7269f933 LP |
552 | if (ch->flags & FLAG_REPROGRAM) { |
553 | ch->flags &= ~FLAG_REPROGRAM; | |
554 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 555 | |
7269f933 LP |
556 | if (ch->flags & FLAG_CLOCKEVENT) |
557 | if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
558 | || (ch->match_value == ch->next_match_value)) | |
559 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
560 | } |
561 | ||
7269f933 | 562 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
563 | |
564 | return IRQ_HANDLED; | |
565 | } | |
566 | ||
7269f933 | 567 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
568 | { |
569 | int ret = 0; | |
570 | unsigned long flags; | |
571 | ||
7269f933 | 572 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 573 | |
7269f933 LP |
574 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
575 | ret = sh_cmt_enable(ch, &ch->rate); | |
3fb1b6ad MD |
576 | |
577 | if (ret) | |
578 | goto out; | |
7269f933 | 579 | ch->flags |= flag; |
3fb1b6ad MD |
580 | |
581 | /* setup timeout if no clockevent */ | |
7269f933 LP |
582 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
583 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 584 | out: |
7269f933 | 585 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
586 | |
587 | return ret; | |
588 | } | |
589 | ||
7269f933 | 590 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
591 | { |
592 | unsigned long flags; | |
593 | unsigned long f; | |
594 | ||
7269f933 | 595 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 596 | |
7269f933 LP |
597 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
598 | ch->flags &= ~flag; | |
3fb1b6ad | 599 | |
7269f933 LP |
600 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
601 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
602 | |
603 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
604 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
605 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 606 | |
7269f933 | 607 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
608 | } |
609 | ||
7269f933 | 610 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 611 | { |
7269f933 | 612 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
613 | } |
614 | ||
615 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
616 | { | |
7269f933 | 617 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
618 | unsigned long flags, raw; |
619 | unsigned long value; | |
620 | int has_wrapped; | |
621 | ||
7269f933 LP |
622 | raw_spin_lock_irqsave(&ch->lock, flags); |
623 | value = ch->total_cycles; | |
624 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
625 | |
626 | if (unlikely(has_wrapped)) | |
7269f933 LP |
627 | raw += ch->match_value + 1; |
628 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
629 | |
630 | return value + raw; | |
631 | } | |
632 | ||
633 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
634 | { | |
3593f5fe | 635 | int ret; |
7269f933 | 636 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 637 | |
7269f933 | 638 | WARN_ON(ch->cs_enabled); |
bad81383 | 639 | |
7269f933 | 640 | ch->total_cycles = 0; |
19bdc9d0 | 641 | |
7269f933 | 642 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
bad81383 | 643 | if (!ret) { |
fba9e072 | 644 | __clocksource_update_freq_hz(cs, ch->rate); |
7269f933 | 645 | ch->cs_enabled = true; |
bad81383 | 646 | } |
3593f5fe | 647 | return ret; |
19bdc9d0 MD |
648 | } |
649 | ||
650 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
651 | { | |
7269f933 | 652 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 653 | |
7269f933 | 654 | WARN_ON(!ch->cs_enabled); |
bad81383 | 655 | |
7269f933 LP |
656 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
657 | ch->cs_enabled = false; | |
19bdc9d0 MD |
658 | } |
659 | ||
9bb5ec88 RW |
660 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
661 | { | |
7269f933 | 662 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 663 | |
54d46b7f GU |
664 | if (!ch->cs_enabled) |
665 | return; | |
666 | ||
7269f933 LP |
667 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
668 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
669 | } |
670 | ||
c8162884 MD |
671 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
672 | { | |
7269f933 | 673 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 674 | |
54d46b7f GU |
675 | if (!ch->cs_enabled) |
676 | return; | |
677 | ||
7269f933 LP |
678 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
679 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
680 | } |
681 | ||
7269f933 | 682 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 683 | const char *name) |
19bdc9d0 | 684 | { |
7269f933 | 685 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
686 | |
687 | cs->name = name; | |
fb28a659 | 688 | cs->rating = 125; |
19bdc9d0 MD |
689 | cs->read = sh_cmt_clocksource_read; |
690 | cs->enable = sh_cmt_clocksource_enable; | |
691 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 692 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 693 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
694 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
695 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 696 | |
740a9518 LP |
697 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
698 | ch->index); | |
f4d7c356 | 699 | |
3593f5fe MD |
700 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
701 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
702 | return 0; |
703 | } | |
704 | ||
7269f933 | 705 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 706 | { |
7269f933 | 707 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
708 | } |
709 | ||
7269f933 | 710 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 711 | { |
7269f933 | 712 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad | 713 | |
7269f933 | 714 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
715 | |
716 | /* TODO: calculate good shift from rate and counter bit width */ | |
717 | ||
718 | ced->shift = 32; | |
7269f933 LP |
719 | ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift); |
720 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
3fb1b6ad MD |
721 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
722 | ||
723 | if (periodic) | |
7269f933 | 724 | sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 725 | else |
7269f933 | 726 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
727 | } |
728 | ||
729 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
730 | struct clock_event_device *ced) | |
731 | { | |
7269f933 | 732 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
733 | |
734 | /* deal with old setting first */ | |
735 | switch (ced->mode) { | |
736 | case CLOCK_EVT_MODE_PERIODIC: | |
737 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 738 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
739 | break; |
740 | default: | |
741 | break; | |
742 | } | |
743 | ||
744 | switch (mode) { | |
745 | case CLOCK_EVT_MODE_PERIODIC: | |
7269f933 | 746 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 747 | "ch%u: used for periodic clock events\n", ch->index); |
7269f933 | 748 | sh_cmt_clock_event_start(ch, 1); |
3fb1b6ad MD |
749 | break; |
750 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 751 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 752 | "ch%u: used for oneshot clock events\n", ch->index); |
7269f933 | 753 | sh_cmt_clock_event_start(ch, 0); |
3fb1b6ad MD |
754 | break; |
755 | case CLOCK_EVT_MODE_SHUTDOWN: | |
756 | case CLOCK_EVT_MODE_UNUSED: | |
7269f933 | 757 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
758 | break; |
759 | default: | |
760 | break; | |
761 | } | |
762 | } | |
763 | ||
764 | static int sh_cmt_clock_event_next(unsigned long delta, | |
765 | struct clock_event_device *ced) | |
766 | { | |
7269f933 | 767 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
768 | |
769 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
7269f933 LP |
770 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
771 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 772 | else |
7269f933 | 773 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
774 | |
775 | return 0; | |
776 | } | |
777 | ||
9bb5ec88 RW |
778 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
779 | { | |
7269f933 | 780 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 781 | |
7269f933 LP |
782 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
783 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
784 | } |
785 | ||
786 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
787 | { | |
7269f933 | 788 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 789 | |
7269f933 LP |
790 | clk_prepare(ch->cmt->clk); |
791 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
792 | } |
793 | ||
bfa76bb1 LP |
794 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
795 | const char *name) | |
3fb1b6ad | 796 | { |
7269f933 | 797 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
798 | int irq; |
799 | int ret; | |
800 | ||
31e912f5 | 801 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
bfa76bb1 LP |
802 | if (irq < 0) { |
803 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", | |
804 | ch->index); | |
805 | return irq; | |
806 | } | |
807 | ||
808 | ret = request_irq(irq, sh_cmt_interrupt, | |
809 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
810 | dev_name(&ch->cmt->pdev->dev), ch); | |
811 | if (ret) { | |
812 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
813 | ch->index, irq); | |
814 | return ret; | |
815 | } | |
3fb1b6ad | 816 | |
3fb1b6ad MD |
817 | ced->name = name; |
818 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
819 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 820 | ced->rating = 125; |
f1ebe1e4 | 821 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad MD |
822 | ced->set_next_event = sh_cmt_clock_event_next; |
823 | ced->set_mode = sh_cmt_clock_event_mode; | |
9bb5ec88 RW |
824 | ced->suspend = sh_cmt_clock_event_suspend; |
825 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 826 | |
740a9518 LP |
827 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
828 | ch->index); | |
3fb1b6ad | 829 | clockevents_register_device(ced); |
bfa76bb1 LP |
830 | |
831 | return 0; | |
3fb1b6ad MD |
832 | } |
833 | ||
1d053e1d | 834 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 835 | bool clockevent, bool clocksource) |
3fb1b6ad | 836 | { |
bfa76bb1 LP |
837 | int ret; |
838 | ||
81b3b271 LP |
839 | if (clockevent) { |
840 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
841 | ret = sh_cmt_register_clockevent(ch, name); |
842 | if (ret < 0) | |
843 | return ret; | |
81b3b271 | 844 | } |
3fb1b6ad | 845 | |
81b3b271 LP |
846 | if (clocksource) { |
847 | ch->cmt->has_clocksource = true; | |
fb28a659 | 848 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 849 | } |
19bdc9d0 | 850 | |
3fb1b6ad MD |
851 | return 0; |
852 | } | |
853 | ||
740a9518 | 854 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
855 | unsigned int hwidx, bool clockevent, |
856 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 857 | { |
b882e7b1 LP |
858 | int ret; |
859 | ||
81b3b271 LP |
860 | /* Skip unused channels. */ |
861 | if (!clockevent && !clocksource) | |
862 | return 0; | |
863 | ||
b882e7b1 | 864 | ch->cmt = cmt; |
740a9518 | 865 | ch->index = index; |
81b3b271 LP |
866 | ch->hwidx = hwidx; |
867 | ||
868 | /* | |
869 | * Compute the address of the channel control register block. For the | |
870 | * timers with a per-channel start/stop register, compute its address | |
871 | * as well. | |
81b3b271 | 872 | */ |
31e912f5 LP |
873 | switch (cmt->info->model) { |
874 | case SH_CMT_16BIT: | |
875 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
876 | break; | |
877 | case SH_CMT_32BIT: | |
878 | case SH_CMT_48BIT: | |
879 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
880 | break; | |
881 | case SH_CMT_32BIT_FAST: | |
882 | /* | |
883 | * The 32-bit "fast" timer has a single channel at hwidx 5 but | |
884 | * is located at offset 0x40 instead of 0x60 for some reason. | |
885 | */ | |
886 | ch->ioctrl = cmt->mapbase + 0x40; | |
887 | break; | |
888 | case SH_CMT_48BIT_GEN2: | |
889 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; | |
890 | ch->ioctrl = ch->iostart + 0x10; | |
891 | break; | |
81b3b271 LP |
892 | } |
893 | ||
2cda3ac4 | 894 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
895 | ch->max_match_value = ~0; |
896 | else | |
2cda3ac4 | 897 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
898 | |
899 | ch->match_value = ch->max_match_value; | |
900 | raw_spin_lock_init(&ch->lock); | |
901 | ||
31e912f5 | 902 | ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; |
81b3b271 | 903 | |
1d053e1d | 904 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 905 | clockevent, clocksource); |
b882e7b1 | 906 | if (ret) { |
740a9518 LP |
907 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
908 | ch->index); | |
b882e7b1 LP |
909 | return ret; |
910 | } | |
911 | ch->cs_enabled = false; | |
912 | ||
b882e7b1 LP |
913 | return 0; |
914 | } | |
915 | ||
81b3b271 | 916 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 917 | { |
81b3b271 | 918 | struct resource *mem; |
3fb1b6ad | 919 | |
81b3b271 LP |
920 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
921 | if (!mem) { | |
922 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
923 | return -ENXIO; | |
924 | } | |
3fb1b6ad | 925 | |
81b3b271 LP |
926 | cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); |
927 | if (cmt->mapbase == NULL) { | |
928 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
929 | return -ENXIO; | |
3fb1b6ad MD |
930 | } |
931 | ||
81b3b271 LP |
932 | return 0; |
933 | } | |
934 | ||
1768aa2f LP |
935 | static const struct platform_device_id sh_cmt_id_table[] = { |
936 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, | |
937 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
938 | { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] }, | |
939 | { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] }, | |
940 | { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] }, | |
941 | { } | |
942 | }; | |
943 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
944 | ||
945 | static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { | |
946 | { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] }, | |
947 | { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, | |
948 | { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, | |
949 | { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, | |
950 | { } | |
951 | }; | |
952 | MODULE_DEVICE_TABLE(of, sh_cmt_of_table); | |
953 | ||
954 | static int sh_cmt_parse_dt(struct sh_cmt_device *cmt) | |
955 | { | |
956 | struct device_node *np = cmt->pdev->dev.of_node; | |
957 | ||
958 | return of_property_read_u32(np, "renesas,channels-mask", | |
959 | &cmt->hw_channels); | |
960 | } | |
961 | ||
81b3b271 LP |
962 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
963 | { | |
31e912f5 LP |
964 | unsigned int mask; |
965 | unsigned int i; | |
81b3b271 LP |
966 | int ret; |
967 | ||
968 | memset(cmt, 0, sizeof(*cmt)); | |
969 | cmt->pdev = pdev; | |
de599c88 | 970 | raw_spin_lock_init(&cmt->lock); |
81b3b271 | 971 | |
1768aa2f LP |
972 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { |
973 | const struct of_device_id *id; | |
974 | ||
975 | id = of_match_node(sh_cmt_of_table, pdev->dev.of_node); | |
976 | cmt->info = id->data; | |
977 | ||
978 | ret = sh_cmt_parse_dt(cmt); | |
979 | if (ret < 0) | |
980 | return ret; | |
981 | } else if (pdev->dev.platform_data) { | |
982 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
983 | const struct platform_device_id *id = pdev->id_entry; | |
984 | ||
985 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
986 | cmt->hw_channels = cfg->channels_mask; | |
987 | } else { | |
81b3b271 LP |
988 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
989 | return -ENXIO; | |
990 | } | |
991 | ||
81b3b271 | 992 | /* Get hold of clock. */ |
31e912f5 | 993 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
994 | if (IS_ERR(cmt->clk)) { |
995 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 996 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
997 | } |
998 | ||
2653caf4 | 999 | ret = clk_prepare(cmt->clk); |
57dee992 | 1000 | if (ret < 0) |
81b3b271 | 1001 | goto err_clk_put; |
57dee992 | 1002 | |
31e912f5 LP |
1003 | /* Map the memory resource(s). */ |
1004 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 LP |
1005 | if (ret < 0) |
1006 | goto err_clk_unprepare; | |
1007 | ||
1008 | /* Allocate and setup the channels. */ | |
1768aa2f | 1009 | cmt->num_channels = hweight8(cmt->hw_channels); |
81b3b271 LP |
1010 | cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), |
1011 | GFP_KERNEL); | |
f5ec9b19 LP |
1012 | if (cmt->channels == NULL) { |
1013 | ret = -ENOMEM; | |
81b3b271 | 1014 | goto err_unmap; |
f5ec9b19 LP |
1015 | } |
1016 | ||
31e912f5 LP |
1017 | /* |
1018 | * Use the first channel as a clock event device and the second channel | |
1019 | * as a clock source. If only one channel is available use it for both. | |
1020 | */ | |
1768aa2f | 1021 | for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { |
31e912f5 LP |
1022 | unsigned int hwidx = ffs(mask) - 1; |
1023 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
1024 | bool clockevent = i == 0; | |
1025 | ||
1026 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
1027 | clockevent, clocksource, cmt); | |
81b3b271 LP |
1028 | if (ret < 0) |
1029 | goto err_unmap; | |
f5ec9b19 | 1030 | |
31e912f5 | 1031 | mask &= ~(1 << hwidx); |
81b3b271 | 1032 | } |
da64c2a8 | 1033 | |
2653caf4 | 1034 | platform_set_drvdata(pdev, cmt); |
adccc69e | 1035 | |
da64c2a8 | 1036 | return 0; |
81b3b271 LP |
1037 | |
1038 | err_unmap: | |
f5ec9b19 | 1039 | kfree(cmt->channels); |
31e912f5 | 1040 | iounmap(cmt->mapbase); |
81b3b271 | 1041 | err_clk_unprepare: |
2653caf4 | 1042 | clk_unprepare(cmt->clk); |
81b3b271 | 1043 | err_clk_put: |
2653caf4 | 1044 | clk_put(cmt->clk); |
3fb1b6ad MD |
1045 | return ret; |
1046 | } | |
1047 | ||
1850514b | 1048 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1049 | { |
2653caf4 | 1050 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1051 | int ret; |
1052 | ||
9bb5ec88 | 1053 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
1054 | pm_runtime_set_active(&pdev->dev); |
1055 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1056 | } |
615a445f | 1057 | |
2653caf4 | 1058 | if (cmt) { |
214a607a | 1059 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1060 | goto out; |
e475eedb MD |
1061 | } |
1062 | ||
b262bc74 | 1063 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1064 | if (cmt == NULL) |
3fb1b6ad | 1065 | return -ENOMEM; |
3fb1b6ad | 1066 | |
2653caf4 | 1067 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1068 | if (ret) { |
2653caf4 | 1069 | kfree(cmt); |
bad81383 RW |
1070 | pm_runtime_idle(&pdev->dev); |
1071 | return ret; | |
3fb1b6ad | 1072 | } |
bad81383 RW |
1073 | if (is_early_platform_device(pdev)) |
1074 | return 0; | |
1075 | ||
1076 | out: | |
81b3b271 | 1077 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1078 | pm_runtime_irq_safe(&pdev->dev); |
1079 | else | |
1080 | pm_runtime_idle(&pdev->dev); | |
1081 | ||
1082 | return 0; | |
3fb1b6ad MD |
1083 | } |
1084 | ||
1850514b | 1085 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1086 | { |
1087 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1088 | } | |
1089 | ||
1090 | static struct platform_driver sh_cmt_device_driver = { | |
1091 | .probe = sh_cmt_probe, | |
1850514b | 1092 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1093 | .driver = { |
1094 | .name = "sh_cmt", | |
1768aa2f | 1095 | .of_match_table = of_match_ptr(sh_cmt_of_table), |
81b3b271 LP |
1096 | }, |
1097 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1098 | }; |
1099 | ||
1100 | static int __init sh_cmt_init(void) | |
1101 | { | |
1102 | return platform_driver_register(&sh_cmt_device_driver); | |
1103 | } | |
1104 | ||
1105 | static void __exit sh_cmt_exit(void) | |
1106 | { | |
1107 | platform_driver_unregister(&sh_cmt_device_driver); | |
1108 | } | |
1109 | ||
e475eedb | 1110 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1111 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1112 | module_exit(sh_cmt_exit); |
1113 | ||
1114 | MODULE_AUTHOR("Magnus Damm"); | |
1115 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1116 | MODULE_LICENSE("GPL v2"); |