[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / sun4i_timer.c

/*
 * Allwinner A1X SoCs timer handling.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <benn@allwinnertech.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_IRQ_EN_REG	0x00
#define TIMER_IRQ_EN(val)		BIT(val)
#define TIMER_IRQ_ST_REG	0x04
#define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
#define TIMER_CTL_ENABLE		BIT(0)
#define TIMER_CTL_RELOAD		BIT(1)
#define TIMER_CTL_ONESHOT		BIT(7)
#define TIMER_INTVAL_REG(val)	(0x10 * (val) + 0x14)
#define TIMER_CNTVAL_REG(val)	(0x10 * (val) + 0x18)

#define TIMER_SCAL		16

static void __iomem *timer_base;

static void sun4i_clkevt_mode(enum clock_event_mode mode,
			      struct clock_event_device *clk)
{
	u32 u = readl(timer_base + TIMER_CTL_REG(0));

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		u &= ~(TIMER_CTL_ONESHOT);
		writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
		break;
	}
}

static int sun4i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *unused)
{
	u32 u = readl(timer_base + TIMER_CTL_REG(0));
	writel(evt, timer_base + TIMER_CNTVAL_REG(0));
	writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
	       timer_base + TIMER_CTL_REG(0));

	return 0;
}

static struct clock_event_device sun4i_clockevent = {
	.name = "sun4i_tick",
	.rating = 300,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = sun4i_clkevt_mode,
	.set_next_event = sun4i_clkevt_next_event,
};


static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;

	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction sun4i_timer_irq = {
	.name = "sun4i_timer0",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler = sun4i_timer_interrupt,
	.dev_id = &sun4i_clockevent,
};

static u32 sun4i_timer_sched_read(void)
{
	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
}

static void __init sun4i_timer_init(struct device_node *node)
{
	unsigned long rate = 0;
	struct clk *clk;
	int ret, irq;
	u32 val;

	timer_base = of_iomap(node, 0);
	if (!timer_base)
		panic("Can't map registers");

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0)
		panic("Can't parse IRQ");

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk))
		panic("Can't get timer clock");

	rate = clk_get_rate(clk);

	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_base + TIMER_CTL_REG(1));

	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
			      rate, 300, 32, clocksource_mmio_readl_down);

	writel(rate / (TIMER_SCAL * HZ),
	       timer_base + TIMER_INTVAL_REG(0));

	/* set clock source to HOSC, 16 pre-division */
	val = readl(timer_base + TIMER_CTL_REG(0));
	val &= ~(0x07 << 4);
	val &= ~(0x03 << 2);
	val |= (4 << 4) | (1 << 2);
	writel(val, timer_base + TIMER_CTL_REG(0));

	/* set mode to auto reload */
	val = readl(timer_base + TIMER_CTL_REG(0));
	writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));

	ret = setup_irq(irq, &sun4i_timer_irq);
	if (ret)
		pr_warn("failed to setup irq %d\n", irq);

	/* Enable timer0 interrupt */
	val = readl(timer_base + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);

	sun4i_clockevent.cpumask = cpumask_of(0);

	clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
					0x1, 0xff);
}
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
		       sun4i_timer_init);
Commit	Line	Data
b2ac5d75 MR	1	/*
	2	* Allwinner A1X SoCs timer handling.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* Based on code from
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	* Benn Huang <benn@allwinnertech.com>
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/irqreturn.h>
137c6b3c	22	#include <linux/sched_clock.h>
b2ac5d75 MR	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
b2ac5d75	26
04981731	27	#define TIMER_IRQ_EN_REG 0x00
40777645	28	#define TIMER_IRQ_EN(val) BIT(val)
b2ac5d75	29	#define TIMER_IRQ_ST_REG 0x04
04981731	30	#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
40777645	31	#define TIMER_CTL_ENABLE BIT(0)
9eded232	32	#define TIMER_CTL_RELOAD BIT(1)
40777645	33	#define TIMER_CTL_ONESHOT BIT(7)
bb008b9e MR	34	#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
bb008b9e MR	35	#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
b2ac5d75 MR	36
	37	#define TIMER_SCAL 16
	38
	39	static void __iomem *timer_base;
	40
119fd635	41	static void sun4i_clkevt_mode(enum clock_event_mode mode,
b2ac5d75 MR	42	struct clock_event_device *clk)
b2ac5d75 MR	43	{
04981731	44	u32 u = readl(timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	45
	46	switch (mode) {
	47	case CLOCK_EVT_MODE_PERIODIC:
04981731 MR	48	u &= ~(TIMER_CTL_ONESHOT);
04981731 MR	49	writel(u \| TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	50	break;
	51
	52	case CLOCK_EVT_MODE_ONESHOT:
04981731	53	writel(u \| TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	54	break;
	55	case CLOCK_EVT_MODE_UNUSED:
	56	case CLOCK_EVT_MODE_SHUTDOWN:
	57	default:
04981731	58	writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	59	break;
	60	}
	61	}
	62
119fd635	63	static int sun4i_clkevt_next_event(unsigned long evt,
b2ac5d75 MR	64	struct clock_event_device *unused)
b2ac5d75 MR	65	{
04981731 MR	66	u32 u = readl(timer_base + TIMER_CTL_REG(0));
	67	writel(evt, timer_base + TIMER_CNTVAL_REG(0));
	68	writel(u \| TIMER_CTL_ENABLE \| TIMER_CTL_AUTORELOAD,
	69	timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	70
	71	return 0;
	72	}
	73
119fd635 MR	74	static struct clock_event_device sun4i_clockevent = {
119fd635 MR	75	.name = "sun4i_tick",
b2ac5d75 MR	76	.rating = 300,
b2ac5d75 MR	77	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
119fd635 MR	78	.set_mode = sun4i_clkevt_mode,
119fd635 MR	79	.set_next_event = sun4i_clkevt_next_event,
b2ac5d75 MR	80	};
	81
	82
119fd635	83	static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
b2ac5d75 MR	84	{
	85	struct clock_event_device evt = (struct clock_event_device )dev_id;
	86
	87	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	88	evt->event_handler(evt);
	89
	90	return IRQ_HANDLED;
	91	}
	92
119fd635 MR	93	static struct irqaction sun4i_timer_irq = {
119fd635 MR	94	.name = "sun4i_timer0",
b2ac5d75	95	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
119fd635 MR	96	.handler = sun4i_timer_interrupt,
119fd635 MR	97	.dev_id = &sun4i_clockevent,
b2ac5d75 MR	98	};
b2ac5d75 MR	99
137c6b3c MR	100	static u32 sun4i_timer_sched_read(void)
	101	{
	102	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
	103	}
	104
119fd635	105	static void __init sun4i_timer_init(struct device_node *node)
b2ac5d75	106	{
b2ac5d75 MR	107	unsigned long rate = 0;
	108	struct clk *clk;
	109	int ret, irq;
	110	u32 val;
	111
b2ac5d75 MR	112	timer_base = of_iomap(node, 0);
	113	if (!timer_base)
	114	panic("Can't map registers");
	115
	116	irq = irq_of_parse_and_map(node, 0);
	117	if (irq <= 0)
	118	panic("Can't parse IRQ");
	119
b2ac5d75 MR	120	clk = of_clk_get(node, 0);
	121	if (IS_ERR(clk))
	122	panic("Can't get timer clock");
	123
	124	rate = clk_get_rate(clk);
	125
137c6b3c MR	126	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	127	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD \|
	128	TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	129	timer_base + TIMER_CTL_REG(1));
	130
	131	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
	132	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
	133	rate, 300, 32, clocksource_mmio_readl_down);
	134
b2ac5d75	135	writel(rate / (TIMER_SCAL * HZ),
04981731	136	timer_base + TIMER_INTVAL_REG(0));
b2ac5d75 MR	137
b2ac5d75 MR	138	/* set clock source to HOSC, 16 pre-division */
04981731	139	val = readl(timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	140	val &= ~(0x07 << 4);
	141	val &= ~(0x03 << 2);
	142	val \|= (4 << 4) \| (1 << 2);
04981731	143	writel(val, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	144
b2ac5d75 MR	145	/* set mode to auto reload */
04981731	146	val = readl(timer_base + TIMER_CTL_REG(0));
9eded232	147	writel(val \| TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
b2ac5d75	148
119fd635	149	ret = setup_irq(irq, &sun4i_timer_irq);
b2ac5d75 MR	150	if (ret)
	151	pr_warn("failed to setup irq %d\n", irq);
	152
	153	/* Enable timer0 interrupt */
04981731 MR	154	val = readl(timer_base + TIMER_IRQ_EN_REG);
04981731 MR	155	writel(val \| TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
b2ac5d75	156
119fd635	157	sun4i_clockevent.cpumask = cpumask_of(0);
b2ac5d75	158
119fd635	159	clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
77cc982f	160	0x1, 0xff);
b2ac5d75	161	}
119fd635 MR	162	CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
119fd635 MR	163	sun4i_timer_init);