[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / sun4i_timer.c

/*
 * Allwinner A1X SoCs timer handling.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <benn@allwinnertech.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_IRQ_EN_REG	0x00
#define TIMER_IRQ_EN(val)		BIT(val)
#define TIMER_IRQ_ST_REG	0x04
#define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
#define TIMER_CTL_ENABLE		BIT(0)
#define TIMER_CTL_RELOAD		BIT(1)
#define TIMER_CTL_CLK_SRC(val)		(((val) & 0x3) << 2)
#define TIMER_CTL_CLK_SRC_OSC24M		(1)
#define TIMER_CTL_CLK_PRES(val)		(((val) & 0x7) << 4)
#define TIMER_CTL_ONESHOT		BIT(7)
#define TIMER_INTVAL_REG(val)	(0x10 * (val) + 0x14)
#define TIMER_CNTVAL_REG(val)	(0x10 * (val) + 0x18)

#define TIMER_SYNC_TICKS	3

static void __iomem *timer_base;
static u32 ticks_per_jiffy;

/*
 * When we disable a timer, we need to wait at least for 2 cycles of
 * the timer source clock. We will use for that the clocksource timer
 * that is already setup and runs at the same frequency than the other
 * timers, and we never will be disabled.
 */
static void sun4i_clkevt_sync(void)
{
	u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));

	while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
		cpu_relax();
}

static void sun4i_clkevt_time_stop(u8 timer)
{
	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
	sun4i_clkevt_sync();
}

static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
{
	writel(delay, timer_base + TIMER_INTVAL_REG(timer));
}

static void sun4i_clkevt_time_start(u8 timer, bool periodic)
{
	u32 val = readl(timer_base + TIMER_CTL_REG(timer));

	if (periodic)
		val &= ~TIMER_CTL_ONESHOT;
	else
		val |= TIMER_CTL_ONESHOT;

	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       timer_base + TIMER_CTL_REG(timer));
}

static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
{
	sun4i_clkevt_time_stop(0);
	return 0;
}

static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
{
	sun4i_clkevt_time_stop(0);
	sun4i_clkevt_time_start(0, false);
	return 0;
}

static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
{
	sun4i_clkevt_time_stop(0);
	sun4i_clkevt_time_setup(0, ticks_per_jiffy);
	sun4i_clkevt_time_start(0, true);
	return 0;
}

static int sun4i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *unused)
{
	sun4i_clkevt_time_stop(0);
	sun4i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
	sun4i_clkevt_time_start(0, false);

	return 0;
}

static struct clock_event_device sun4i_clockevent = {
	.name = "sun4i_tick",
	.rating = 350,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown = sun4i_clkevt_shutdown,
	.set_state_periodic = sun4i_clkevt_set_periodic,
	.set_state_oneshot = sun4i_clkevt_set_oneshot,
	.tick_resume = sun4i_clkevt_shutdown,
	.set_next_event = sun4i_clkevt_next_event,
};


static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;

	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction sun4i_timer_irq = {
	.name = "sun4i_timer0",
	.flags = IRQF_TIMER | IRQF_IRQPOLL,
	.handler = sun4i_timer_interrupt,
	.dev_id = &sun4i_clockevent,
};

static u64 notrace sun4i_timer_sched_read(void)
{
	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
}

static int __init sun4i_timer_init(struct device_node *node)
{
	unsigned long rate = 0;
	struct clk *clk;
	int ret, irq;
	u32 val;

	timer_base = of_iomap(node, 0);
	if (!timer_base) {
		pr_crit("Can't map registers");
		return -ENXIO;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0) {
		pr_crit("Can't parse IRQ");
		return -EINVAL;
	}

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_crit("Can't get timer clock");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Failed to prepare clock");
		return ret;
	}

	rate = clk_get_rate(clk);

	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_base + TIMER_CTL_REG(1));

	/*
	 * sched_clock_register does not have priorities, and on sun6i and
	 * later there is a better sched_clock registered by arm_arch_timer.c
	 */
	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
	    of_machine_is_compatible("allwinner,sun5i-a13") ||
	    of_machine_is_compatible("allwinner,sun5i-a10s"))
		sched_clock_register(sun4i_timer_sched_read, 32, rate);

	ret = clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
				    rate, 350, 32, clocksource_mmio_readl_down);
	if (ret) {
		pr_err("Failed to register clocksource");
		return ret;
	}

	ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);

	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_base + TIMER_CTL_REG(0));

	/* Make sure timer is stopped before playing with interrupts */
	sun4i_clkevt_time_stop(0);

	sun4i_clockevent.cpumask = cpu_possible_mask;
	sun4i_clockevent.irq = irq;

	clockevents_config_and_register(&sun4i_clockevent, rate,
					TIMER_SYNC_TICKS, 0xffffffff);

	ret = setup_irq(irq, &sun4i_timer_irq);
	if (ret) {
		pr_err("failed to setup irq %d\n", irq);
		return ret;
	}

	/* Enable timer0 interrupt */
	val = readl(timer_base + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);

	return ret;
}
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
		       sun4i_timer_init);
Commit	Line	Data
b2ac5d75 MR	1	/*
	2	* Allwinner A1X SoCs timer handling.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* Based on code from
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	* Benn Huang <benn@allwinnertech.com>
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/irqreturn.h>
137c6b3c	22	#include <linux/sched_clock.h>
b2ac5d75 MR	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
b2ac5d75	26
04981731	27	#define TIMER_IRQ_EN_REG 0x00
40777645	28	#define TIMER_IRQ_EN(val) BIT(val)
b2ac5d75	29	#define TIMER_IRQ_ST_REG 0x04
04981731	30	#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
40777645	31	#define TIMER_CTL_ENABLE BIT(0)
9eded232	32	#define TIMER_CTL_RELOAD BIT(1)
a2c49e7b MR	33	#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
	34	#define TIMER_CTL_CLK_SRC_OSC24M (1)
	35	#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
40777645	36	#define TIMER_CTL_ONESHOT BIT(7)
bb008b9e MR	37	#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
bb008b9e MR	38	#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
b2ac5d75	39
12e1480b MR	40	#define TIMER_SYNC_TICKS 3
12e1480b MR	41
b2ac5d75	42	static void __iomem *timer_base;
7e141834	43	static u32 ticks_per_jiffy;
b2ac5d75	44
63d88f1a MR	45	/*
	46	* When we disable a timer, we need to wait at least for 2 cycles of
	47	* the timer source clock. We will use for that the clocksource timer
	48	* that is already setup and runs at the same frequency than the other
	49	* timers, and we never will be disabled.
	50	*/
	51	static void sun4i_clkevt_sync(void)
	52	{
	53	u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
	54
12e1480b	55	while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
63d88f1a MR	56	cpu_relax();
	57	}
	58
96651a07 MR	59	static void sun4i_clkevt_time_stop(u8 timer)
	60	{
	61	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	62	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
	63	sun4i_clkevt_sync();
	64	}
	65
	66	static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
	67	{
	68	writel(delay, timer_base + TIMER_INTVAL_REG(timer));
	69	}
	70
	71	static void sun4i_clkevt_time_start(u8 timer, bool periodic)
	72	{
	73	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	74
	75	if (periodic)
	76	val &= ~TIMER_CTL_ONESHOT;
	77	else
	78	val \|= TIMER_CTL_ONESHOT;
	79
7e141834 MR	80	writel(val \| TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
7e141834 MR	81	timer_base + TIMER_CTL_REG(timer));
96651a07 MR	82	}
96651a07 MR	83
6de6c977	84	static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
b2ac5d75	85	{
6de6c977 VK	86	sun4i_clkevt_time_stop(0);
	87	return 0;
	88	}
	89
	90	static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
	91	{
	92	sun4i_clkevt_time_stop(0);
	93	sun4i_clkevt_time_start(0, false);
	94	return 0;
	95	}
	96
	97	static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
	98	{
	99	sun4i_clkevt_time_stop(0);
	100	sun4i_clkevt_time_setup(0, ticks_per_jiffy);
	101	sun4i_clkevt_time_start(0, true);
	102	return 0;
b2ac5d75 MR	103	}
b2ac5d75 MR	104
119fd635	105	static int sun4i_clkevt_next_event(unsigned long evt,
b2ac5d75 MR	106	struct clock_event_device *unused)
b2ac5d75 MR	107	{
96651a07	108	sun4i_clkevt_time_stop(0);
12e1480b	109	sun4i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
96651a07	110	sun4i_clkevt_time_start(0, false);
b2ac5d75 MR	111
	112	return 0;
	113	}
	114
119fd635 MR	115	static struct clock_event_device sun4i_clockevent = {
119fd635 MR	116	.name = "sun4i_tick",
5df9affb	117	.rating = 350,
b2ac5d75	118	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
6de6c977 VK	119	.set_state_shutdown = sun4i_clkevt_shutdown,
	120	.set_state_periodic = sun4i_clkevt_set_periodic,
	121	.set_state_oneshot = sun4i_clkevt_set_oneshot,
	122	.tick_resume = sun4i_clkevt_shutdown,
119fd635	123	.set_next_event = sun4i_clkevt_next_event,
b2ac5d75 MR	124	};
	125
	126
119fd635	127	static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
b2ac5d75 MR	128	{
	129	struct clock_event_device evt = (struct clock_event_device )dev_id;
	130
	131	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	132	evt->event_handler(evt);
	133
	134	return IRQ_HANDLED;
	135	}
	136
119fd635 MR	137	static struct irqaction sun4i_timer_irq = {
119fd635 MR	138	.name = "sun4i_timer0",
3353652c	139	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
119fd635 MR	140	.handler = sun4i_timer_interrupt,
119fd635 MR	141	.dev_id = &sun4i_clockevent,
b2ac5d75 MR	142	};
b2ac5d75 MR	143
662e7230	144	static u64 notrace sun4i_timer_sched_read(void)
137c6b3c MR	145	{
	146	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
	147	}
	148
ce5dc743	149	static int __init sun4i_timer_init(struct device_node *node)
b2ac5d75	150	{
b2ac5d75 MR	151	unsigned long rate = 0;
	152	struct clk *clk;
	153	int ret, irq;
	154	u32 val;
	155
b2ac5d75	156	timer_base = of_iomap(node, 0);
ce5dc743 DL	157	if (!timer_base) {
	158	pr_crit("Can't map registers");
	159	return -ENXIO;
	160	}
b2ac5d75 MR	161
b2ac5d75 MR	162	irq = irq_of_parse_and_map(node, 0);
ce5dc743 DL	163	if (irq <= 0) {
	164	pr_crit("Can't parse IRQ");
	165	return -EINVAL;
	166	}
b2ac5d75	167
b2ac5d75	168	clk = of_clk_get(node, 0);
ce5dc743 DL	169	if (IS_ERR(clk)) {
	170	pr_crit("Can't get timer clock");
	171	return PTR_ERR(clk);
	172	}
	173
	174	ret = clk_prepare_enable(clk);
	175	if (ret) {
	176	pr_err("Failed to prepare clock");
	177	return ret;
	178	}
b2ac5d75 MR	179
	180	rate = clk_get_rate(clk);
	181
137c6b3c MR	182	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	183	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD \|
	184	TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	185	timer_base + TIMER_CTL_REG(1));
	186
37b8b003 HG	187	/*
	188	* sched_clock_register does not have priorities, and on sun6i and
	189	* later there is a better sched_clock registered by arm_arch_timer.c
	190	*/
	191	if (of_machine_is_compatible("allwinner,sun4i-a10") \|\|
	192	of_machine_is_compatible("allwinner,sun5i-a13") \|\|
	193	of_machine_is_compatible("allwinner,sun5i-a10s"))
	194	sched_clock_register(sun4i_timer_sched_read, 32, rate);
	195
ce5dc743 DL	196	ret = clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
	197	rate, 350, 32, clocksource_mmio_readl_down);
	198	if (ret) {
	199	pr_err("Failed to register clocksource");
	200	return ret;
	201	}
137c6b3c	202
7e141834	203	ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
b2ac5d75	204
7e141834	205	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
a2c49e7b	206	timer_base + TIMER_CTL_REG(0));
b2ac5d75	207
6db50bb6 MZ	208	/* Make sure timer is stopped before playing with interrupts */
	209	sun4i_clkevt_time_stop(0);
	210
6bab4a8a MR	211	sun4i_clockevent.cpumask = cpu_possible_mask;
	212	sun4i_clockevent.irq = irq;
	213
	214	clockevents_config_and_register(&sun4i_clockevent, rate,
	215	TIMER_SYNC_TICKS, 0xffffffff);
	216
119fd635	217	ret = setup_irq(irq, &sun4i_timer_irq);
ce5dc743 DL	218	if (ret) {
	219	pr_err("failed to setup irq %d\n", irq);
	220	return ret;
	221	}
b2ac5d75 MR	222
b2ac5d75 MR	223	/* Enable timer0 interrupt */
04981731 MR	224	val = readl(timer_base + TIMER_IRQ_EN_REG);
04981731 MR	225	writel(val \| TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
ce5dc743 DL	226
ce5dc743 DL	227	return ret;
b2ac5d75	228	}
177cf6e5	229	CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
119fd635	230	sun4i_timer_init);