[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / tcb_clksrc.c

#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/atmel_tc.h>


/*
 * We're configured to use a specific TC block, one that's not hooked
 * up to external hardware, to provide a time solution:
 *
 *   - Two channels combine to create a free-running 32 bit counter
 *     with a base rate of 5+ MHz, packaged as a clocksource (with
 *     resolution better than 200 nsec).
 *   - Some chips support 32 bit counter. A single channel is used for
 *     this 32 bit free-running counter. the second channel is not used.
 *
 *   - The third channel may be used to provide a 16-bit clockevent
 *     source, used in either periodic or oneshot mode.  This runs
 *     at 32 KiHZ, and can handle delays of up to two seconds.
 *
 * A boot clocksource and clockevent source are also currently needed,
 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
 * this code can be used when init_timers() is called, well before most
 * devices are set up.  (Some low end AT91 parts, which can run uClinux,
 * have only the timers in one TC block... they currently don't support
 * the tclib code, because of that initialization issue.)
 *
 * REVISIT behavior during system suspend states... we should disable
 * all clocks and save the power.  Easily done for clockevent devices,
 * but clocksources won't necessarily get the needed notifications.
 * For deeper system sleep states, this will be mandatory...
 */

static void __iomem *tcaddr;
static struct
{
	u32 cmr;
	u32 imr;
	u32 rc;
	bool clken;
} tcb_cache[3];
static u32 bmr_cache;

static u64 tc_get_cycles(struct clocksource *cs)
{
	unsigned long	flags;
	u32		lower, upper;

	raw_local_irq_save(flags);
	do {
		upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
		lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));

	raw_local_irq_restore(flags);
	return (upper << 16) | lower;
}

static u64 tc_get_cycles32(struct clocksource *cs)
{
	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
}

void tc_clksrc_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
		tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
		tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
		tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
		tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
					ATMEL_TC_CLKSTA);
	}

	bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
}

void tc_clksrc_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
		/* Restore registers for the channel, RA and RB are not used  */
		writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
		writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
		writel(0, tcaddr + ATMEL_TC_REG(i, RA));
		writel(0, tcaddr + ATMEL_TC_REG(i, RB));
		/* Disable all the interrupts */
		writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
		/* Reenable interrupts that were enabled before suspending */
		writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
		/* Start the clock if it was used */
		if (tcb_cache[i].clken)
			writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
	}

	/* Dual channel, chain channels */
	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
	/* Finally, trigger all the channels*/
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static struct clocksource clksrc = {
	.name           = "tcb_clksrc",
	.rating         = 200,
	.read           = tc_get_cycles,
	.mask           = CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.suspend	= tc_clksrc_suspend,
	.resume		= tc_clksrc_resume,
};

#ifdef CONFIG_GENERIC_CLOCKEVENTS

struct tc_clkevt_device {
	struct clock_event_device	clkevt;
	struct clk			*clk;
	void __iomem			*regs;
};

static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
{
	return container_of(clkevt, struct tc_clkevt_device, clkevt);
}

/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
 * because using one of the divided clocks would usually mean the
 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
 *
 * A divided clock could be good for high resolution timers, since
 * 30.5 usec resolution can seem "low".
 */
static u32 timer_clock;

static int tc_shutdown(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	writel(0xff, regs + ATMEL_TC_REG(2, IDR));
	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
	if (!clockevent_state_detached(d))
		clk_disable(tcd->clk);

	return 0;
}

static int tc_set_oneshot(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	clk_enable(tcd->clk);

	/* slow clock, count up to RC, then irq and stop */
	writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* set_next_event() configures and starts the timer */
	return 0;
}

static int tc_set_periodic(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	/* By not making the gentime core emulate periodic mode on top
	 * of oneshot, we get lower overhead and improved accuracy.
	 */
	clk_enable(tcd->clk);

	/* slow clock, count up to RC, then irq and restart */
	writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
		     regs + ATMEL_TC_REG(2, CMR));
	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));

	/* Enable clock and interrupts on RC compare */
	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* go go gadget! */
	writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
		     ATMEL_TC_REG(2, CCR));
	return 0;
}

static int tc_next_event(unsigned long delta, struct clock_event_device *d)
{
	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));

	/* go go gadget! */
	writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
			tcaddr + ATMEL_TC_REG(2, CCR));
	return 0;
}

static struct tc_clkevt_device clkevt = {
	.clkevt	= {
		.name			= "tc_clkevt",
		.features		= CLOCK_EVT_FEAT_PERIODIC |
					  CLOCK_EVT_FEAT_ONESHOT,
		/* Should be lower than at91rm9200's system timer */
		.rating			= 125,
		.set_next_event		= tc_next_event,
		.set_state_shutdown	= tc_shutdown,
		.set_state_periodic	= tc_set_periodic,
		.set_state_oneshot	= tc_set_oneshot,
	},
};

static irqreturn_t ch2_irq(int irq, void *handle)
{
	struct tc_clkevt_device	*dev = handle;
	unsigned int		sr;

	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
	if (sr & ATMEL_TC_CPCS) {
		dev->clkevt.event_handler(&dev->clkevt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
{
	int ret;
	struct clk *t2_clk = tc->clk[2];
	int irq = tc->irq[2];

	ret = clk_prepare_enable(tc->slow_clk);
	if (ret)
		return ret;

	/* try to enable t2 clk to avoid future errors in mode change */
	ret = clk_prepare_enable(t2_clk);
	if (ret) {
		clk_disable_unprepare(tc->slow_clk);
		return ret;
	}

	clk_disable(t2_clk);

	clkevt.regs = tc->regs;
	clkevt.clk = t2_clk;

	timer_clock = clk32k_divisor_idx;

	clkevt.clkevt.cpumask = cpumask_of(0);

	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
	if (ret) {
		clk_unprepare(t2_clk);
		clk_disable_unprepare(tc->slow_clk);
		return ret;
	}

	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);

	return ret;
}

#else /* !CONFIG_GENERIC_CLOCKEVENTS */

static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
{
	/* NOTHING */
	return 0;
}

#endif

static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
	writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP		/* free-run */
			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
			tcaddr + ATMEL_TC_REG(0, CMR));
	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* channel 1:  waveform mode, input TIOA0 */
	writel(ATMEL_TC_XC1			/* input: TIOA0 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(1, CMR));
	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));

	/* chain channel 0 to channel 1*/
	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
	/* then reset all the timers */
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8 */
	writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(0, CMR));
	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* then reset all the timers */
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static int __init tcb_clksrc_init(void)
{
	static char bootinfo[] __initdata
		= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";

	struct platform_device *pdev;
	struct atmel_tc *tc;
	struct clk *t0_clk;
	u32 rate, divided_rate = 0;
	int best_divisor_idx = -1;
	int clk32k_divisor_idx = -1;
	int i;
	int ret;

	tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
	if (!tc) {
		pr_debug("can't alloc TC for clocksource\n");
		return -ENODEV;
	}
	tcaddr = tc->regs;
	pdev = tc->pdev;

	t0_clk = tc->clk[0];
	ret = clk_prepare_enable(t0_clk);
	if (ret) {
		pr_debug("can't enable T0 clk\n");
		goto err_free_tc;
	}

	/* How fast will we be counting?  Pick something over 5 MHz.  */
	rate = (u32) clk_get_rate(t0_clk);
	for (i = 0; i < 5; i++) {
		unsigned divisor = atmel_tc_divisors[i];
		unsigned tmp;

		/* remember 32 KiHz clock for later */
		if (!divisor) {
			clk32k_divisor_idx = i;
			continue;
		}

		tmp = rate / divisor;
		pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
		if (best_divisor_idx > 0) {
			if (tmp < 5 * 1000 * 1000)
				continue;
		}
		divided_rate = tmp;
		best_divisor_idx = i;
	}


	printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
			divided_rate / 1000000,
			((divided_rate + 500000) % 1000000) / 1000);

	if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
		/* use apropriate function to read 32 bit counter */
		clksrc.read = tc_get_cycles32;
		/* setup ony channel 0 */
		tcb_setup_single_chan(tc, best_divisor_idx);
	} else {
		/* tclib will give us three clocks no matter what the
		 * underlying platform supports.
		 */
		ret = clk_prepare_enable(tc->clk[1]);
		if (ret) {
			pr_debug("can't enable T1 clk\n");
			goto err_disable_t0;
		}
		/* setup both channel 0 & 1 */
		tcb_setup_dual_chan(tc, best_divisor_idx);
	}

	/* and away we go! */
	ret = clocksource_register_hz(&clksrc, divided_rate);
	if (ret)
		goto err_disable_t1;

	/* channel 2:  periodic and oneshot timer support */
	ret = setup_clkevents(tc, clk32k_divisor_idx);
	if (ret)
		goto err_unregister_clksrc;

	return 0;

err_unregister_clksrc:
	clocksource_unregister(&clksrc);

err_disable_t1:
	if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
		clk_disable_unprepare(tc->clk[1]);

err_disable_t0:
	clk_disable_unprepare(t0_clk);

err_free_tc:
	atmel_tc_free(tc);
	return ret;
}
arch_initcall(tcb_clksrc_init);
Commit	Line	Data
4d243f92 DB	1	#include <linux/init.h>
	2	#include <linux/clocksource.h>
	3	#include <linux/clockchips.h>
	4	#include <linux/interrupt.h>
	5	#include <linux/irq.h>
	6
	7	#include <linux/clk.h>
	8	#include <linux/err.h>
	9	#include <linux/ioport.h>
	10	#include <linux/io.h>
	11	#include <linux/platform_device.h>
2a515e5d	12	#include <linux/syscore_ops.h>
4d243f92 DB	13	#include <linux/atmel_tc.h>
	14
	15
	16	/*
	17	* We're configured to use a specific TC block, one that's not hooked
	18	* up to external hardware, to provide a time solution:
	19	*
	20	* - Two channels combine to create a free-running 32 bit counter
	21	* with a base rate of 5+ MHz, packaged as a clocksource (with
	22	* resolution better than 200 nsec).
8e315a7b NF	23	* - Some chips support 32 bit counter. A single channel is used for
8e315a7b NF	24	* this 32 bit free-running counter. the second channel is not used.
4d243f92 DB	25	*
	26	* - The third channel may be used to provide a 16-bit clockevent
	27	* source, used in either periodic or oneshot mode. This runs
	28	* at 32 KiHZ, and can handle delays of up to two seconds.
	29	*
	30	* A boot clocksource and clockevent source are also currently needed,
	31	* unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
	32	* this code can be used when init_timers() is called, well before most
	33	* devices are set up. (Some low end AT91 parts, which can run uClinux,
	34	* have only the timers in one TC block... they currently don't support
	35	* the tclib code, because of that initialization issue.)
	36	*
	37	* REVISIT behavior during system suspend states... we should disable
	38	* all clocks and save the power. Easily done for clockevent devices,
	39	* but clocksources won't necessarily get the needed notifications.
	40	* For deeper system sleep states, this will be mandatory...
	41	*/
	42
	43	static void __iomem *tcaddr;
2a515e5d AB	44	static struct
	45	{
	46	u32 cmr;
	47	u32 imr;
	48	u32 rc;
	49	bool clken;
	50	} tcb_cache[3];
	51	static u32 bmr_cache;
4d243f92	52
a5a1d1c2	53	static u64 tc_get_cycles(struct clocksource *cs)
4d243f92 DB	54	{
	55	unsigned long flags;
	56	u32 lower, upper;
	57
	58	raw_local_irq_save(flags);
	59	do {
6ec8be25 AB	60	upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
	61	lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
	62	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
4d243f92 DB	63
	64	raw_local_irq_restore(flags);
	65	return (upper << 16) \| lower;
	66	}
	67
7b9f1d16 DE	68	static u64 tc_get_cycles32(struct clocksource *cs)
7b9f1d16 DE	69	{
6ec8be25	70	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
7b9f1d16 DE	71	}
7b9f1d16 DE	72
2a515e5d AB	73	void tc_clksrc_suspend(struct clocksource *cs)
	74	{
	75	int i;
	76
	77	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
	78	tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
	79	tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
	80	tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
	81	tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
	82	ATMEL_TC_CLKSTA);
	83	}
	84
	85	bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
	86	}
	87
	88	void tc_clksrc_resume(struct clocksource *cs)
	89	{
	90	int i;
	91
	92	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
	93	/* Restore registers for the channel, RA and RB are not used */
	94	writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
	95	writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
	96	writel(0, tcaddr + ATMEL_TC_REG(i, RA));
	97	writel(0, tcaddr + ATMEL_TC_REG(i, RB));
	98	/* Disable all the interrupts */
	99	writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
	100	/* Reenable interrupts that were enabled before suspending */
	101	writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
	102	/* Start the clock if it was used */
	103	if (tcb_cache[i].clken)
	104	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
	105	}
	106
	107	/* Dual channel, chain channels */
	108	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
	109	/* Finally, trigger all the channels*/
	110	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
	111	}
	112
4d243f92 DB	113	static struct clocksource clksrc = {
	114	.name = "tcb_clksrc",
	115	.rating = 200,
	116	.read = tc_get_cycles,
	117	.mask = CLOCKSOURCE_MASK(32),
4d243f92	118	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
2a515e5d AB	119	.suspend = tc_clksrc_suspend,
2a515e5d AB	120	.resume = tc_clksrc_resume,
4d243f92 DB	121	};
	122
	123	#ifdef CONFIG_GENERIC_CLOCKEVENTS
	124
	125	struct tc_clkevt_device {
	126	struct clock_event_device clkevt;
	127	struct clk *clk;
	128	void __iomem *regs;
	129	};
	130
	131	static struct tc_clkevt_device to_tc_clkevt(struct clock_event_device clkevt)
	132	{
	133	return container_of(clkevt, struct tc_clkevt_device, clkevt);
	134	}
	135
	136	/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
	137	* because using one of the divided clocks would usually mean the
	138	* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
	139	*
	140	* A divided clock could be good for high resolution timers, since
	141	* 30.5 usec resolution can seem "low".
	142	*/
	143	static u32 timer_clock;
	144
cf4541c1	145	static int tc_shutdown(struct clock_event_device *d)
4d243f92 DB	146	{
	147	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	148	void __iomem *regs = tcd->regs;
	149
6ec8be25 AB	150	writel(0xff, regs + ATMEL_TC_REG(2, IDR));
6ec8be25 AB	151	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
f02b4b72 AB	152	if (!clockevent_state_detached(d))
f02b4b72 AB	153	clk_disable(tcd->clk);
4d243f92	154
cf4541c1 VK	155	return 0;
cf4541c1 VK	156	}
4d243f92	157
cf4541c1 VK	158	static int tc_set_oneshot(struct clock_event_device *d)
	159	{
	160	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	161	void __iomem *regs = tcd->regs;
4d243f92	162
cf4541c1 VK	163	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	164	tc_shutdown(d);
4d243f92	165
cf4541c1	166	clk_enable(tcd->clk);
4d243f92	167
cf4541c1	168	/* slow clock, count up to RC, then irq and stop */
6ec8be25	169	writel(timer_clock \| ATMEL_TC_CPCSTOP \| ATMEL_TC_WAVE \|
cf4541c1	170	ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
6ec8be25	171	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
4d243f92	172
cf4541c1 VK	173	/* set_next_event() configures and starts the timer */
	174	return 0;
	175	}
4d243f92	176
cf4541c1 VK	177	static int tc_set_periodic(struct clock_event_device *d)
	178	{
	179	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	180	void __iomem *regs = tcd->regs;
4d243f92	181
cf4541c1 VK	182	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	183	tc_shutdown(d);
4d243f92	184
cf4541c1 VK	185	/* By not making the gentime core emulate periodic mode on top
	186	* of oneshot, we get lower overhead and improved accuracy.
	187	*/
	188	clk_enable(tcd->clk);
	189
	190	/* slow clock, count up to RC, then irq and restart */
6ec8be25	191	writel(timer_clock \| ATMEL_TC_WAVE \| ATMEL_TC_WAVESEL_UP_AUTO,
cf4541c1	192	regs + ATMEL_TC_REG(2, CMR));
6ec8be25	193	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
cf4541c1 VK	194
cf4541c1 VK	195	/* Enable clock and interrupts on RC compare */
6ec8be25	196	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
cf4541c1 VK	197
cf4541c1 VK	198	/* go go gadget! */
6ec8be25	199	writel(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG, regs +
cf4541c1 VK	200	ATMEL_TC_REG(2, CCR));
cf4541c1 VK	201	return 0;
4d243f92 DB	202	}
	203
	204	static int tc_next_event(unsigned long delta, struct clock_event_device *d)
	205	{
6ec8be25	206	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
4d243f92 DB	207
4d243f92 DB	208	/* go go gadget! */
6ec8be25	209	writel_relaxed(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG,
4d243f92 DB	210	tcaddr + ATMEL_TC_REG(2, CCR));
	211	return 0;
	212	}
	213
	214	static struct tc_clkevt_device clkevt = {
	215	.clkevt = {
cf4541c1 VK	216	.name = "tc_clkevt",
	217	.features = CLOCK_EVT_FEAT_PERIODIC \|
	218	CLOCK_EVT_FEAT_ONESHOT,
4d243f92	219	/* Should be lower than at91rm9200's system timer */
cf4541c1 VK	220	.rating = 125,
	221	.set_next_event = tc_next_event,
	222	.set_state_shutdown = tc_shutdown,
	223	.set_state_periodic = tc_set_periodic,
	224	.set_state_oneshot = tc_set_oneshot,
4d243f92 DB	225	},
	226	};
	227
	228	static irqreturn_t ch2_irq(int irq, void *handle)
	229	{
	230	struct tc_clkevt_device *dev = handle;
	231	unsigned int sr;
	232
6ec8be25	233	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
4d243f92 DB	234	if (sr & ATMEL_TC_CPCS) {
	235	dev->clkevt.event_handler(&dev->clkevt);
	236	return IRQ_HANDLED;
	237	}
	238
	239	return IRQ_NONE;
	240	}
	241
5b3c11da	242	static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
4d243f92	243	{
5b3c11da	244	int ret;
4d243f92 DB	245	struct clk *t2_clk = tc->clk[2];
	246	int irq = tc->irq[2];
	247
7d8d05d1 BB	248	ret = clk_prepare_enable(tc->slow_clk);
	249	if (ret)
	250	return ret;
	251
5b3c11da BB	252	/* try to enable t2 clk to avoid future errors in mode change */
5b3c11da BB	253	ret = clk_prepare_enable(t2_clk);
7d8d05d1 BB	254	if (ret) {
7d8d05d1 BB	255	clk_disable_unprepare(tc->slow_clk);
5b3c11da	256	return ret;
7d8d05d1 BB	257	}
7d8d05d1 BB	258
acbf6d21	259	clk_disable(t2_clk);
5b3c11da	260
4d243f92 DB	261	clkevt.regs = tc->regs;
4d243f92 DB	262	clkevt.clk = t2_clk;
4d243f92 DB	263
	264	timer_clock = clk32k_divisor_idx;
	265
320ab2b0	266	clkevt.clkevt.cpumask = cpumask_of(0);
4d243f92	267
d07a1ecd GP	268	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
d07a1ecd GP	269	if (ret) {
eed9fb9d	270	clk_unprepare(t2_clk);
7d8d05d1	271	clk_disable_unprepare(tc->slow_clk);
5b3c11da	272	return ret;
d07a1ecd	273	}
5b3c11da	274
77cc982f	275	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
1817dc03	276
5b3c11da	277	return ret;
4d243f92 DB	278	}
	279
	280	#else /* !CONFIG_GENERIC_CLOCKEVENTS */
	281
5b3c11da	282	static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
4d243f92 DB	283	{
4d243f92 DB	284	/* NOTHING */
5b3c11da	285	return 0;
4d243f92 DB	286	}
	287
	288	#endif
	289
8e315a7b NF	290	static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
	291	{
	292	/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
6ec8be25	293	writel(mck_divisor_idx /* likely divide-by-8 */
8e315a7b NF	294	\| ATMEL_TC_WAVE
	295	\| ATMEL_TC_WAVESEL_UP /* free-run */
	296	\| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
	297	\| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
	298	tcaddr + ATMEL_TC_REG(0, CMR));
6ec8be25 AB	299	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	300	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	301	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
	302	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
8e315a7b NF	303
8e315a7b NF	304	/* channel 1: waveform mode, input TIOA0 */
6ec8be25	305	writel(ATMEL_TC_XC1 /* input: TIOA0 */
8e315a7b NF	306	\| ATMEL_TC_WAVE
	307	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	308	tcaddr + ATMEL_TC_REG(1, CMR));
6ec8be25 AB	309	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
6ec8be25 AB	310	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
8e315a7b NF	311
8e315a7b NF	312	/* chain channel 0 to channel 1*/
6ec8be25	313	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
8e315a7b	314	/* then reset all the timers */
6ec8be25	315	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
8e315a7b NF	316	}
	317
	318	static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
	319	{
	320	/* channel 0: waveform mode, input mclk/8 */
6ec8be25	321	writel(mck_divisor_idx /* likely divide-by-8 */
8e315a7b NF	322	\| ATMEL_TC_WAVE
	323	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	324	tcaddr + ATMEL_TC_REG(0, CMR));
6ec8be25 AB	325	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
6ec8be25 AB	326	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
8e315a7b NF	327
8e315a7b NF	328	/* then reset all the timers */
6ec8be25	329	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
8e315a7b NF	330	}
8e315a7b NF	331
4d243f92 DB	332	static int __init tcb_clksrc_init(void)
	333	{
	334	static char bootinfo[] __initdata
	335	= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
	336
	337	struct platform_device *pdev;
	338	struct atmel_tc *tc;
3ee08aea	339	struct clk *t0_clk;
4d243f92 DB	340	u32 rate, divided_rate = 0;
	341	int best_divisor_idx = -1;
	342	int clk32k_divisor_idx = -1;
	343	int i;
0e746ec5	344	int ret;
4d243f92	345
4930d247	346	tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
4d243f92 DB	347	if (!tc) {
	348	pr_debug("can't alloc TC for clocksource\n");
	349	return -ENODEV;
	350	}
	351	tcaddr = tc->regs;
	352	pdev = tc->pdev;
	353
	354	t0_clk = tc->clk[0];
0e746ec5 BB	355	ret = clk_prepare_enable(t0_clk);
	356	if (ret) {
	357	pr_debug("can't enable T0 clk\n");
	358	goto err_free_tc;
	359	}
4d243f92 DB	360
	361	/* How fast will we be counting? Pick something over 5 MHz. */
	362	rate = (u32) clk_get_rate(t0_clk);
	363	for (i = 0; i < 5; i++) {
	364	unsigned divisor = atmel_tc_divisors[i];
	365	unsigned tmp;
	366
	367	/* remember 32 KiHz clock for later */
	368	if (!divisor) {
	369	clk32k_divisor_idx = i;
	370	continue;
	371	}
	372
	373	tmp = rate / divisor;
	374	pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
	375	if (best_divisor_idx > 0) {
	376	if (tmp < 5 * 1000 * 1000)
	377	continue;
	378	}
	379	divided_rate = tmp;
	380	best_divisor_idx = i;
	381	}
	382
4d243f92 DB	383
	384	printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
	385	divided_rate / 1000000,
	386	((divided_rate + 500000) % 1000000) / 1000);
	387
8e315a7b NF	388	if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
	389	/* use apropriate function to read 32 bit counter */
	390	clksrc.read = tc_get_cycles32;
	391	/* setup ony channel 0 */
	392	tcb_setup_single_chan(tc, best_divisor_idx);
	393	} else {
	394	/* tclib will give us three clocks no matter what the
	395	* underlying platform supports.
	396	*/
0e746ec5 BB	397	ret = clk_prepare_enable(tc->clk[1]);
	398	if (ret) {
	399	pr_debug("can't enable T1 clk\n");
	400	goto err_disable_t0;
	401	}
8e315a7b NF	402	/* setup both channel 0 & 1 */
	403	tcb_setup_dual_chan(tc, best_divisor_idx);
	404	}
4d243f92 DB	405
4d243f92 DB	406	/* and away we go! */
5b3c11da BB	407	ret = clocksource_register_hz(&clksrc, divided_rate);
	408	if (ret)
	409	goto err_disable_t1;
4d243f92 DB	410
4d243f92 DB	411	/* channel 2: periodic and oneshot timer support */
5b3c11da BB	412	ret = setup_clkevents(tc, clk32k_divisor_idx);
	413	if (ret)
	414	goto err_unregister_clksrc;
4d243f92 DB	415
4d243f92 DB	416	return 0;
0e746ec5	417
5b3c11da BB	418	err_unregister_clksrc:
	419	clocksource_unregister(&clksrc);
	420
	421	err_disable_t1:
	422	if (!tc->tcb_config \|\| tc->tcb_config->counter_width != 32)
	423	clk_disable_unprepare(tc->clk[1]);
	424
0e746ec5 BB	425	err_disable_t0:
	426	clk_disable_unprepare(t0_clk);
	427
	428	err_free_tc:
	429	atmel_tc_free(tc);
	430	return ret;
4d243f92 DB	431	}
4d243f92 DB	432	arch_initcall(tcb_clksrc_init);