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6fe9cbd1 GC |
1 | /* |
2 | * Marvell Armada 370/XP SoC timer handling. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * Timer 0 is used as free-running clocksource, while timer 1 is | |
15 | * used as clock_event_device. | |
7cd6392c EG |
16 | * |
17 | * --- | |
18 | * Clocksource driver for Armada 370 and Armada XP SoC. | |
19 | * This driver implements one compatible string for each SoC, given | |
20 | * each has its own characteristics: | |
21 | * | |
22 | * * Armada 370 has no 25 MHz fixed timer. | |
23 | * | |
24 | * * Armada XP cannot work properly without such 25 MHz fixed timer as | |
25 | * doing otherwise leads to using a clocksource whose frequency varies | |
26 | * when doing cpufreq frequency changes. | |
27 | * | |
28 | * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt | |
6fe9cbd1 GC |
29 | */ |
30 | ||
31 | #include <linux/init.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/kernel.h> | |
307c2bf4 | 34 | #include <linux/clk.h> |
5ddb6d21 | 35 | #include <linux/cpu.h> |
6fe9cbd1 GC |
36 | #include <linux/timer.h> |
37 | #include <linux/clockchips.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/of.h> | |
40 | #include <linux/of_irq.h> | |
41 | #include <linux/of_address.h> | |
42 | #include <linux/irq.h> | |
43 | #include <linux/module.h> | |
38ff87f7 | 44 | #include <linux/sched_clock.h> |
ddd3f69f | 45 | #include <linux/percpu.h> |
6fe9cbd1 GC |
46 | |
47 | /* | |
48 | * Timer block registers. | |
49 | */ | |
50 | #define TIMER_CTRL_OFF 0x0000 | |
ad48bd61 EG |
51 | #define TIMER0_EN BIT(0) |
52 | #define TIMER0_RELOAD_EN BIT(1) | |
53 | #define TIMER0_25MHZ BIT(11) | |
6fe9cbd1 | 54 | #define TIMER0_DIV(div) ((div) << 19) |
ad48bd61 EG |
55 | #define TIMER1_EN BIT(2) |
56 | #define TIMER1_RELOAD_EN BIT(3) | |
57 | #define TIMER1_25MHZ BIT(12) | |
6fe9cbd1 GC |
58 | #define TIMER1_DIV(div) ((div) << 22) |
59 | #define TIMER_EVENTS_STATUS 0x0004 | |
60 | #define TIMER0_CLR_MASK (~0x1) | |
61 | #define TIMER1_CLR_MASK (~0x100) | |
62 | #define TIMER0_RELOAD_OFF 0x0010 | |
63 | #define TIMER0_VAL_OFF 0x0014 | |
64 | #define TIMER1_RELOAD_OFF 0x0018 | |
65 | #define TIMER1_VAL_OFF 0x001c | |
66 | ||
ddd3f69f | 67 | #define LCL_TIMER_EVENTS_STATUS 0x0028 |
6fe9cbd1 GC |
68 | /* Global timers are connected to the coherency fabric clock, and the |
69 | below divider reduces their incrementing frequency. */ | |
70 | #define TIMER_DIVIDER_SHIFT 5 | |
71 | #define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT) | |
72 | ||
73 | /* | |
74 | * SoC-specific data. | |
75 | */ | |
ddd3f69f GC |
76 | static void __iomem *timer_base, *local_base; |
77 | static unsigned int timer_clk; | |
78 | static bool timer25Mhz = true; | |
6fe9cbd1 GC |
79 | |
80 | /* | |
81 | * Number of timer ticks per jiffy. | |
82 | */ | |
83 | static u32 ticks_per_jiffy; | |
84 | ||
5ddb6d21 | 85 | static struct clock_event_device __percpu *armada_370_xp_evt; |
ddd3f69f | 86 | |
3579698e EG |
87 | static void timer_ctrl_clrset(u32 clr, u32 set) |
88 | { | |
89 | writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set, | |
90 | timer_base + TIMER_CTRL_OFF); | |
91 | } | |
92 | ||
93 | static void local_timer_ctrl_clrset(u32 clr, u32 set) | |
94 | { | |
95 | writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, | |
96 | local_base + TIMER_CTRL_OFF); | |
97 | } | |
ddd3f69f | 98 | |
d9dbcbe0 | 99 | static u64 notrace armada_370_xp_read_sched_clock(void) |
6fe9cbd1 GC |
100 | { |
101 | return ~readl(timer_base + TIMER0_VAL_OFF); | |
102 | } | |
103 | ||
104 | /* | |
105 | * Clockevent handling. | |
106 | */ | |
107 | static int | |
108 | armada_370_xp_clkevt_next_event(unsigned long delta, | |
109 | struct clock_event_device *dev) | |
110 | { | |
6fe9cbd1 GC |
111 | /* |
112 | * Clear clockevent timer interrupt. | |
113 | */ | |
ddd3f69f | 114 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
6fe9cbd1 GC |
115 | |
116 | /* | |
117 | * Setup new clockevent timer value. | |
118 | */ | |
ddd3f69f | 119 | writel(delta, local_base + TIMER0_VAL_OFF); |
6fe9cbd1 GC |
120 | |
121 | /* | |
122 | * Enable the timer. | |
123 | */ | |
3579698e EG |
124 | local_timer_ctrl_clrset(TIMER0_RELOAD_EN, |
125 | TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT)); | |
6fe9cbd1 GC |
126 | return 0; |
127 | } | |
128 | ||
129 | static void | |
130 | armada_370_xp_clkevt_mode(enum clock_event_mode mode, | |
131 | struct clock_event_device *dev) | |
132 | { | |
6fe9cbd1 | 133 | if (mode == CLOCK_EVT_MODE_PERIODIC) { |
ddd3f69f | 134 | |
6fe9cbd1 GC |
135 | /* |
136 | * Setup timer to fire at 1/HZ intervals. | |
137 | */ | |
ddd3f69f GC |
138 | writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF); |
139 | writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF); | |
6fe9cbd1 GC |
140 | |
141 | /* | |
142 | * Enable timer. | |
143 | */ | |
3579698e EG |
144 | local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | |
145 | TIMER0_EN | | |
146 | TIMER0_DIV(TIMER_DIVIDER_SHIFT)); | |
6fe9cbd1 GC |
147 | } else { |
148 | /* | |
149 | * Disable timer. | |
150 | */ | |
3579698e | 151 | local_timer_ctrl_clrset(TIMER0_EN, 0); |
6fe9cbd1 GC |
152 | |
153 | /* | |
154 | * ACK pending timer interrupt. | |
155 | */ | |
ddd3f69f | 156 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
6fe9cbd1 GC |
157 | } |
158 | } | |
159 | ||
5ddb6d21 | 160 | static int armada_370_xp_clkevt_irq; |
6fe9cbd1 GC |
161 | |
162 | static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id) | |
163 | { | |
164 | /* | |
165 | * ACK timer interrupt and call event handler. | |
166 | */ | |
5ddb6d21 | 167 | struct clock_event_device *evt = dev_id; |
6fe9cbd1 | 168 | |
ddd3f69f GC |
169 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
170 | evt->event_handler(evt); | |
6fe9cbd1 GC |
171 | |
172 | return IRQ_HANDLED; | |
173 | } | |
174 | ||
ddd3f69f GC |
175 | /* |
176 | * Setup the local clock events for a CPU. | |
177 | */ | |
8c37bb3a | 178 | static int armada_370_xp_timer_setup(struct clock_event_device *evt) |
ddd3f69f | 179 | { |
3579698e | 180 | u32 clr = 0, set = 0; |
ddd3f69f GC |
181 | int cpu = smp_processor_id(); |
182 | ||
ddd3f69f | 183 | if (timer25Mhz) |
3579698e | 184 | set = TIMER0_25MHZ; |
ddd3f69f | 185 | else |
3579698e EG |
186 | clr = TIMER0_25MHZ; |
187 | local_timer_ctrl_clrset(clr, set); | |
ddd3f69f | 188 | |
5ddb6d21 SB |
189 | evt->name = "armada_370_xp_per_cpu_tick", |
190 | evt->features = CLOCK_EVT_FEAT_ONESHOT | | |
191 | CLOCK_EVT_FEAT_PERIODIC; | |
192 | evt->shift = 32, | |
193 | evt->rating = 300, | |
ddd3f69f GC |
194 | evt->set_next_event = armada_370_xp_clkevt_next_event, |
195 | evt->set_mode = armada_370_xp_clkevt_mode, | |
5ddb6d21 | 196 | evt->irq = armada_370_xp_clkevt_irq; |
ddd3f69f GC |
197 | evt->cpumask = cpumask_of(cpu); |
198 | ||
ddd3f69f GC |
199 | clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe); |
200 | enable_percpu_irq(evt->irq, 0); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
47dcd356 | 205 | static void armada_370_xp_timer_stop(struct clock_event_device *evt) |
ddd3f69f GC |
206 | { |
207 | evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); | |
208 | disable_percpu_irq(evt->irq); | |
209 | } | |
210 | ||
47dcd356 | 211 | static int armada_370_xp_timer_cpu_notify(struct notifier_block *self, |
5ddb6d21 SB |
212 | unsigned long action, void *hcpu) |
213 | { | |
214 | /* | |
215 | * Grab cpu pointer in each case to avoid spurious | |
216 | * preemptible warnings | |
217 | */ | |
218 | switch (action & ~CPU_TASKS_FROZEN) { | |
219 | case CPU_STARTING: | |
220 | armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt)); | |
221 | break; | |
222 | case CPU_DYING: | |
223 | armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt)); | |
224 | break; | |
225 | } | |
226 | ||
227 | return NOTIFY_OK; | |
228 | } | |
229 | ||
47dcd356 | 230 | static struct notifier_block armada_370_xp_timer_cpu_nb = { |
5ddb6d21 | 231 | .notifier_call = armada_370_xp_timer_cpu_notify, |
6fe9cbd1 GC |
232 | }; |
233 | ||
7cd6392c | 234 | static void __init armada_370_xp_timer_common_init(struct device_node *np) |
6fe9cbd1 | 235 | { |
3579698e | 236 | u32 clr = 0, set = 0; |
ddd3f69f GC |
237 | int res; |
238 | ||
6fe9cbd1 GC |
239 | timer_base = of_iomap(np, 0); |
240 | WARN_ON(!timer_base); | |
ddd3f69f | 241 | local_base = of_iomap(np, 1); |
6fe9cbd1 | 242 | |
7cd6392c | 243 | if (timer25Mhz) |
a4ae54f9 | 244 | set = TIMER0_25MHZ; |
7cd6392c | 245 | else |
3579698e | 246 | clr = TIMER0_25MHZ; |
3579698e EG |
247 | timer_ctrl_clrset(clr, set); |
248 | local_timer_ctrl_clrset(clr, set); | |
6fe9cbd1 | 249 | |
ddd3f69f GC |
250 | /* |
251 | * We use timer 0 as clocksource, and private(local) timer 0 | |
252 | * for clockevents | |
253 | */ | |
5ddb6d21 | 254 | armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4); |
6fe9cbd1 GC |
255 | |
256 | ticks_per_jiffy = (timer_clk + HZ / 2) / HZ; | |
257 | ||
6fe9cbd1 GC |
258 | /* |
259 | * Setup free-running clocksource timer (interrupts | |
260 | * disabled). | |
261 | */ | |
262 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); | |
263 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); | |
264 | ||
3579698e EG |
265 | timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN | |
266 | TIMER0_DIV(TIMER_DIVIDER_SHIFT)); | |
6fe9cbd1 | 267 | |
c813eff0 EG |
268 | /* |
269 | * Set scale and timer for sched_clock. | |
270 | */ | |
271 | sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk); | |
272 | ||
6fe9cbd1 GC |
273 | clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, |
274 | "armada_370_xp_clocksource", | |
275 | timer_clk, 300, 32, clocksource_mmio_readl_down); | |
276 | ||
5ddb6d21 | 277 | register_cpu_notifier(&armada_370_xp_timer_cpu_nb); |
6fe9cbd1 | 278 | |
5ddb6d21 | 279 | armada_370_xp_evt = alloc_percpu(struct clock_event_device); |
ddd3f69f GC |
280 | |
281 | ||
282 | /* | |
283 | * Setup clockevent timer (interrupt-driven). | |
284 | */ | |
5ddb6d21 | 285 | res = request_percpu_irq(armada_370_xp_clkevt_irq, |
ddd3f69f | 286 | armada_370_xp_timer_interrupt, |
5ddb6d21 SB |
287 | "armada_370_xp_per_cpu_tick", |
288 | armada_370_xp_evt); | |
289 | /* Immediately configure the timer on the boot CPU */ | |
290 | if (!res) | |
291 | armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt)); | |
ddd3f69f | 292 | } |
7cd6392c EG |
293 | |
294 | static void __init armada_xp_timer_init(struct device_node *np) | |
295 | { | |
5e9fe6cb EG |
296 | struct clk *clk = of_clk_get_by_name(np, "fixed"); |
297 | ||
298 | /* The 25Mhz fixed clock is mandatory, and must always be available */ | |
299 | BUG_ON(IS_ERR(clk)); | |
300 | timer_clk = clk_get_rate(clk); | |
7cd6392c EG |
301 | |
302 | armada_370_xp_timer_common_init(np); | |
303 | } | |
304 | CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer", | |
305 | armada_xp_timer_init); | |
306 | ||
307 | static void __init armada_370_timer_init(struct device_node *np) | |
308 | { | |
309 | struct clk *clk = of_clk_get(np, 0); | |
310 | ||
ec8e5112 | 311 | BUG_ON(IS_ERR(clk)); |
7cd6392c EG |
312 | timer_clk = clk_get_rate(clk) / TIMER_DIVIDER; |
313 | timer25Mhz = false; | |
314 | ||
315 | armada_370_xp_timer_common_init(np); | |
ddd3f69f | 316 | } |
7cd6392c EG |
317 | CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer", |
318 | armada_370_timer_init); |