[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / time-armada-370-xp.c

/*
 * Marvell Armada 370/XP SoC timer handling.
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Timer 0 is used as free-running clocksource, while timer 1 is
 * used as clock_event_device.
 *
 * ---
 * Clocksource driver for Armada 370 and Armada XP SoC.
 * This driver implements one compatible string for each SoC, given
 * each has its own characteristics:
 *
 *   * Armada 370 has no 25 MHz fixed timer.
 *
 *   * Armada XP cannot work properly without such 25 MHz fixed timer as
 *     doing otherwise leads to using a clocksource whose frequency varies
 *     when doing cpufreq frequency changes.
 *
 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/timer.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/sched_clock.h>
#include <linux/percpu.h>
#include <linux/syscore_ops.h>

#include <asm/delay.h>

/*
 * Timer block registers.
 */
#define TIMER_CTRL_OFF		0x0000
#define  TIMER0_EN		 BIT(0)
#define  TIMER0_RELOAD_EN	 BIT(1)
#define  TIMER0_25MHZ            BIT(11)
#define  TIMER0_DIV(div)         ((div) << 19)
#define  TIMER1_EN		 BIT(2)
#define  TIMER1_RELOAD_EN	 BIT(3)
#define  TIMER1_25MHZ            BIT(12)
#define  TIMER1_DIV(div)         ((div) << 22)
#define TIMER_EVENTS_STATUS	0x0004
#define  TIMER0_CLR_MASK         (~0x1)
#define  TIMER1_CLR_MASK         (~0x100)
#define TIMER0_RELOAD_OFF	0x0010
#define TIMER0_VAL_OFF		0x0014
#define TIMER1_RELOAD_OFF	0x0018
#define TIMER1_VAL_OFF		0x001c

#define LCL_TIMER_EVENTS_STATUS	0x0028
/* Global timers are connected to the coherency fabric clock, and the
   below divider reduces their incrementing frequency. */
#define TIMER_DIVIDER_SHIFT     5
#define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)

/*
 * SoC-specific data.
 */
static void __iomem *timer_base, *local_base;
static unsigned int timer_clk;
static bool timer25Mhz = true;
static u32 enable_mask;

/*
 * Number of timer ticks per jiffy.
 */
static u32 ticks_per_jiffy;

static struct clock_event_device __percpu *armada_370_xp_evt;

static void local_timer_ctrl_clrset(u32 clr, u32 set)
{
	writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
		local_base + TIMER_CTRL_OFF);
}

static u64 notrace armada_370_xp_read_sched_clock(void)
{
	return ~readl(timer_base + TIMER0_VAL_OFF);
}

/*
 * Clockevent handling.
 */
static int
armada_370_xp_clkevt_next_event(unsigned long delta,
				struct clock_event_device *dev)
{
	/*
	 * Clear clockevent timer interrupt.
	 */
	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);

	/*
	 * Setup new clockevent timer value.
	 */
	writel(delta, local_base + TIMER0_VAL_OFF);

	/*
	 * Enable the timer.
	 */
	local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
	return 0;
}

static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
{
	/*
	 * Disable timer.
	 */
	local_timer_ctrl_clrset(TIMER0_EN, 0);

	/*
	 * ACK pending timer interrupt.
	 */
	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
	return 0;
}

static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
{
	/*
	 * Setup timer to fire at 1/HZ intervals.
	 */
	writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
	writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);

	/*
	 * Enable timer.
	 */
	local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
	return 0;
}

static int armada_370_xp_clkevt_irq;

static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
{
	/*
	 * ACK timer interrupt and call event handler.
	 */
	struct clock_event_device *evt = dev_id;

	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

/*
 * Setup the local clock events for a CPU.
 */
static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
	u32 clr = 0, set = 0;

	if (timer25Mhz)
		set = TIMER0_25MHZ;
	else
		clr = TIMER0_25MHZ;
	local_timer_ctrl_clrset(clr, set);

	evt->name		= "armada_370_xp_per_cpu_tick",
	evt->features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_PERIODIC;
	evt->shift		= 32,
	evt->rating		= 300,
	evt->set_next_event	= armada_370_xp_clkevt_next_event,
	evt->set_state_shutdown	= armada_370_xp_clkevt_shutdown;
	evt->set_state_periodic	= armada_370_xp_clkevt_set_periodic;
	evt->set_state_oneshot	= armada_370_xp_clkevt_shutdown;
	evt->tick_resume	= armada_370_xp_clkevt_shutdown;
	evt->irq		= armada_370_xp_clkevt_irq;
	evt->cpumask		= cpumask_of(cpu);

	clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
	enable_percpu_irq(evt->irq, 0);

	return 0;
}

static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
{
	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);

	evt->set_state_shutdown(evt);
	disable_percpu_irq(evt->irq);
	return 0;
}

static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;

static int armada_370_xp_timer_suspend(void)
{
	timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
	timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
	return 0;
}

static void armada_370_xp_timer_resume(void)
{
	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
	writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
}

static struct syscore_ops armada_370_xp_timer_syscore_ops = {
	.suspend	= armada_370_xp_timer_suspend,
	.resume		= armada_370_xp_timer_resume,
};

static unsigned long armada_370_delay_timer_read(void)
{
	return ~readl(timer_base + TIMER0_VAL_OFF);
}

static struct delay_timer armada_370_delay_timer = {
	.read_current_timer = armada_370_delay_timer_read,
};

static int __init armada_370_xp_timer_common_init(struct device_node *np)
{
	u32 clr = 0, set = 0;
	int res;

	timer_base = of_iomap(np, 0);
	if (!timer_base) {
		pr_err("Failed to iomap");
		return -ENXIO;
	}

	local_base = of_iomap(np, 1);
	if (!local_base) {
		pr_err("Failed to iomap");
		return -ENXIO;
	}

	if (timer25Mhz) {
		set = TIMER0_25MHZ;		
		enable_mask = TIMER0_EN;
	} else {
		clr = TIMER0_25MHZ;
		enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
	}
	atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
	local_timer_ctrl_clrset(clr, set);

	/*
	 * We use timer 0 as clocksource, and private(local) timer 0
	 * for clockevents
	 */
	armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);

	ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;

	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled).
	 */
	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);

	atomic_io_modify(timer_base + TIMER_CTRL_OFF,
		TIMER0_RELOAD_EN | enable_mask,
		TIMER0_RELOAD_EN | enable_mask);

	armada_370_delay_timer.freq = timer_clk;
	register_current_timer_delay(&armada_370_delay_timer);

	/*
	 * Set scale and timer for sched_clock.
	 */
	sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);

	res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
				    "armada_370_xp_clocksource",
				    timer_clk, 300, 32, clocksource_mmio_readl_down);
	if (res) {
		pr_err("Failed to initialize clocksource mmio");
		return res;
	}

	armada_370_xp_evt = alloc_percpu(struct clock_event_device);
	if (!armada_370_xp_evt)
		return -ENOMEM;

	/*
	 * Setup clockevent timer (interrupt-driven).
	 */
	res = request_percpu_irq(armada_370_xp_clkevt_irq,
				armada_370_xp_timer_interrupt,
				"armada_370_xp_per_cpu_tick",
				armada_370_xp_evt);
	/* Immediately configure the timer on the boot CPU */
	if (res) {
		pr_err("Failed to request percpu irq");
		return res;
	}

	res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
				"AP_ARMADA_TIMER_STARTING",
				armada_370_xp_timer_starting_cpu,
				armada_370_xp_timer_dying_cpu);
	if (res) {
		pr_err("Failed to setup hotplug state and timer");
		return res;
	}

	register_syscore_ops(&armada_370_xp_timer_syscore_ops);
	
	return 0;
}

static int __init armada_xp_timer_init(struct device_node *np)
{
	struct clk *clk = of_clk_get_by_name(np, "fixed");
	int ret;

	if (IS_ERR(clk)) {
		pr_err("Failed to get clock");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	timer_clk = clk_get_rate(clk);

	return armada_370_xp_timer_common_init(np);
}
CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
		       armada_xp_timer_init);

static int __init armada_375_timer_init(struct device_node *np)
{
	struct clk *clk;
	int ret;

	clk = of_clk_get_by_name(np, "fixed");
	if (!IS_ERR(clk)) {
		ret = clk_prepare_enable(clk);
		if (ret)
			return ret;
		timer_clk = clk_get_rate(clk);
	} else {

		/*
		 * This fallback is required in order to retain proper
		 * devicetree backwards compatibility.
		 */
		clk = of_clk_get(np, 0);

		/* Must have at least a clock */
		if (IS_ERR(clk)) {
			pr_err("Failed to get clock");
			return PTR_ERR(clk);
		}

		ret = clk_prepare_enable(clk);
		if (ret)
			return ret;

		timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
		timer25Mhz = false;
	}

	return armada_370_xp_timer_common_init(np);
}
CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
		       armada_375_timer_init);

static int __init armada_370_timer_init(struct device_node *np)
{
	struct clk *clk;
	int ret;

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get clock");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
	timer25Mhz = false;

	return armada_370_xp_timer_common_init(np);
}
CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
		       armada_370_timer_init);
Commit	Line	Data
6fe9cbd1 GC	1	/*
	2	* Marvell Armada 370/XP SoC timer handling.
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
	14	* Timer 0 is used as free-running clocksource, while timer 1 is
	15	* used as clock_event_device.
7cd6392c EG	16	*
	17	* ---
	18	* Clocksource driver for Armada 370 and Armada XP SoC.
	19	* This driver implements one compatible string for each SoC, given
	20	* each has its own characteristics:
	21	*
	22	* * Armada 370 has no 25 MHz fixed timer.
	23	*
	24	* * Armada XP cannot work properly without such 25 MHz fixed timer as
	25	* doing otherwise leads to using a clocksource whose frequency varies
	26	* when doing cpufreq frequency changes.
	27	*
	28	* See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
6fe9cbd1 GC	29	*/
	30
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/kernel.h>
307c2bf4	34	#include <linux/clk.h>
5ddb6d21	35	#include <linux/cpu.h>
6fe9cbd1 GC	36	#include <linux/timer.h>
	37	#include <linux/clockchips.h>
	38	#include <linux/interrupt.h>
	39	#include <linux/of.h>
	40	#include <linux/of_irq.h>
	41	#include <linux/of_address.h>
	42	#include <linux/irq.h>
	43	#include <linux/module.h>
38ff87f7	44	#include <linux/sched_clock.h>
ddd3f69f	45	#include <linux/percpu.h>
f9a49ab5	46	#include <linux/syscore_ops.h>
6fe9cbd1	47
cb0f2538 RK	48	#include <asm/delay.h>
cb0f2538 RK	49
6fe9cbd1 GC	50	/*
	51	* Timer block registers.
	52	*/
	53	#define TIMER_CTRL_OFF 0x0000
ad48bd61 EG	54	#define TIMER0_EN BIT(0)
	55	#define TIMER0_RELOAD_EN BIT(1)
	56	#define TIMER0_25MHZ BIT(11)
6fe9cbd1	57	#define TIMER0_DIV(div) ((div) << 19)
ad48bd61 EG	58	#define TIMER1_EN BIT(2)
	59	#define TIMER1_RELOAD_EN BIT(3)
	60	#define TIMER1_25MHZ BIT(12)
6fe9cbd1 GC	61	#define TIMER1_DIV(div) ((div) << 22)
	62	#define TIMER_EVENTS_STATUS 0x0004
	63	#define TIMER0_CLR_MASK (~0x1)
	64	#define TIMER1_CLR_MASK (~0x100)
	65	#define TIMER0_RELOAD_OFF 0x0010
	66	#define TIMER0_VAL_OFF 0x0014
	67	#define TIMER1_RELOAD_OFF 0x0018
	68	#define TIMER1_VAL_OFF 0x001c
	69
ddd3f69f	70	#define LCL_TIMER_EVENTS_STATUS 0x0028
6fe9cbd1 GC	71	/* Global timers are connected to the coherency fabric clock, and the
	72	below divider reduces their incrementing frequency. */
	73	#define TIMER_DIVIDER_SHIFT 5
	74	#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
	75
	76	/*
	77	* SoC-specific data.
	78	*/
ddd3f69f GC	79	static void __iomem timer_base, local_base;
	80	static unsigned int timer_clk;
	81	static bool timer25Mhz = true;
08cb8e46	82	static u32 enable_mask;
6fe9cbd1 GC	83
	84	/*
	85	* Number of timer ticks per jiffy.
	86	*/
	87	static u32 ticks_per_jiffy;
	88
5ddb6d21	89	static struct clock_event_device __percpu *armada_370_xp_evt;
ddd3f69f	90
3579698e EG	91	static void local_timer_ctrl_clrset(u32 clr, u32 set)
	92	{
	93	writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) \| set,
	94	local_base + TIMER_CTRL_OFF);
	95	}
ddd3f69f	96
d9dbcbe0	97	static u64 notrace armada_370_xp_read_sched_clock(void)
6fe9cbd1 GC	98	{
	99	return ~readl(timer_base + TIMER0_VAL_OFF);
	100	}
	101
	102	/*
	103	* Clockevent handling.
	104	*/
	105	static int
	106	armada_370_xp_clkevt_next_event(unsigned long delta,
	107	struct clock_event_device *dev)
	108	{
6fe9cbd1 GC	109	/*
	110	* Clear clockevent timer interrupt.
	111	*/
ddd3f69f	112	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
6fe9cbd1 GC	113
	114	/*
	115	* Setup new clockevent timer value.
	116	*/
ddd3f69f	117	writel(delta, local_base + TIMER0_VAL_OFF);
6fe9cbd1 GC	118
	119	/*
	120	* Enable the timer.
	121	*/
08cb8e46	122	local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
6fe9cbd1 GC	123	return 0;
	124	}
	125
d96f4412	126	static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
6fe9cbd1	127	{
d96f4412 VK	128	/*
	129	* Disable timer.
	130	*/
	131	local_timer_ctrl_clrset(TIMER0_EN, 0);
	132
	133	/*
	134	* ACK pending timer interrupt.
	135	*/
	136	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
	137	return 0;
	138	}
	139
	140	static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
	141	{
	142	/*
	143	* Setup timer to fire at 1/HZ intervals.
	144	*/
	145	writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
	146	writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
	147
	148	/*
	149	* Enable timer.
	150	*/
	151	local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN \| enable_mask);
	152	return 0;
6fe9cbd1 GC	153	}
6fe9cbd1 GC	154
5ddb6d21	155	static int armada_370_xp_clkevt_irq;
6fe9cbd1 GC	156
	157	static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
	158	{
	159	/*
	160	* ACK timer interrupt and call event handler.
	161	*/
5ddb6d21	162	struct clock_event_device *evt = dev_id;
6fe9cbd1	163
ddd3f69f GC	164	writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
ddd3f69f GC	165	evt->event_handler(evt);
6fe9cbd1 GC	166
	167	return IRQ_HANDLED;
	168	}
	169
ddd3f69f GC	170	/*
	171	* Setup the local clock events for a CPU.
	172	*/
2c48fef7	173	static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
ddd3f69f	174	{
2c48fef7	175	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
3579698e	176	u32 clr = 0, set = 0;
ddd3f69f	177
ddd3f69f	178	if (timer25Mhz)
3579698e	179	set = TIMER0_25MHZ;
ddd3f69f	180	else
3579698e EG	181	clr = TIMER0_25MHZ;
3579698e EG	182	local_timer_ctrl_clrset(clr, set);
ddd3f69f	183
5ddb6d21 SB	184	evt->name = "armada_370_xp_per_cpu_tick",
	185	evt->features = CLOCK_EVT_FEAT_ONESHOT \|
	186	CLOCK_EVT_FEAT_PERIODIC;
	187	evt->shift = 32,
	188	evt->rating = 300,
ddd3f69f	189	evt->set_next_event = armada_370_xp_clkevt_next_event,
d96f4412 VK	190	evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
	191	evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
	192	evt->set_state_oneshot = armada_370_xp_clkevt_shutdown;
	193	evt->tick_resume = armada_370_xp_clkevt_shutdown;
5ddb6d21	194	evt->irq = armada_370_xp_clkevt_irq;
ddd3f69f GC	195	evt->cpumask = cpumask_of(cpu);
ddd3f69f GC	196
ddd3f69f GC	197	clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
	198	enable_percpu_irq(evt->irq, 0);
	199
	200	return 0;
	201	}
	202
2c48fef7	203	static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
ddd3f69f	204	{
2c48fef7 RC	205	struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
2c48fef7 RC	206
d96f4412	207	evt->set_state_shutdown(evt);
ddd3f69f	208	disable_percpu_irq(evt->irq);
2c48fef7	209	return 0;
ddd3f69f GC	210	}
ddd3f69f GC	211
f9a49ab5 TP	212	static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
	213
	214	static int armada_370_xp_timer_suspend(void)
	215	{
	216	timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
	217	timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
	218	return 0;
	219	}
	220
	221	static void armada_370_xp_timer_resume(void)
	222	{
	223	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	224	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	225	writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
	226	writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
	227	}
	228
2c436e46	229	static struct syscore_ops armada_370_xp_timer_syscore_ops = {
f9a49ab5 TP	230	.suspend = armada_370_xp_timer_suspend,
	231	.resume = armada_370_xp_timer_resume,
	232	};
	233
cb0f2538 RK	234	static unsigned long armada_370_delay_timer_read(void)
	235	{
	236	return ~readl(timer_base + TIMER0_VAL_OFF);
	237	}
	238
	239	static struct delay_timer armada_370_delay_timer = {
	240	.read_current_timer = armada_370_delay_timer_read,
	241	};
	242
12549e27	243	static int __init armada_370_xp_timer_common_init(struct device_node *np)
6fe9cbd1	244	{
3579698e	245	u32 clr = 0, set = 0;
ddd3f69f GC	246	int res;
ddd3f69f GC	247
6fe9cbd1	248	timer_base = of_iomap(np, 0);
12549e27 DL	249	if (!timer_base) {
	250	pr_err("Failed to iomap");
	251	return -ENXIO;
	252	}
	253
ddd3f69f	254	local_base = of_iomap(np, 1);
12549e27 DL	255	if (!local_base) {
	256	pr_err("Failed to iomap");
	257	return -ENXIO;
	258	}
6fe9cbd1	259
08cb8e46	260	if (timer25Mhz) {
a4ae54f9	261	set = TIMER0_25MHZ;
08cb8e46 EG	262	enable_mask = TIMER0_EN;
08cb8e46 EG	263	} else {
3579698e	264	clr = TIMER0_25MHZ;
08cb8e46 EG	265	enable_mask = TIMER0_EN \| TIMER0_DIV(TIMER_DIVIDER_SHIFT);
08cb8e46 EG	266	}
c8af34b4	267	atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr \| set, set);
3579698e	268	local_timer_ctrl_clrset(clr, set);
6fe9cbd1	269
ddd3f69f GC	270	/*
	271	* We use timer 0 as clocksource, and private(local) timer 0
	272	* for clockevents
	273	*/
5ddb6d21	274	armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
6fe9cbd1 GC	275
	276	ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
	277
6fe9cbd1 GC	278	/*
	279	* Setup free-running clocksource timer (interrupts
	280	* disabled).
	281	*/
	282	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	283	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	284
c8af34b4 EG	285	atomic_io_modify(timer_base + TIMER_CTRL_OFF,
	286	TIMER0_RELOAD_EN \| enable_mask,
	287	TIMER0_RELOAD_EN \| enable_mask);
6fe9cbd1	288
cb0f2538 RK	289	armada_370_delay_timer.freq = timer_clk;
	290	register_current_timer_delay(&armada_370_delay_timer);
	291
c813eff0 EG	292	/*
	293	* Set scale and timer for sched_clock.
	294	*/
	295	sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
	296
12549e27 DL	297	res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
	298	"armada_370_xp_clocksource",
	299	timer_clk, 300, 32, clocksource_mmio_readl_down);
	300	if (res) {
	301	pr_err("Failed to initialize clocksource mmio");
	302	return res;
	303	}
6fe9cbd1	304
5ddb6d21	305	armada_370_xp_evt = alloc_percpu(struct clock_event_device);
12549e27 DL	306	if (!armada_370_xp_evt)
12549e27 DL	307	return -ENOMEM;
ddd3f69f GC	308
	309	/*
	310	* Setup clockevent timer (interrupt-driven).
	311	*/
5ddb6d21	312	res = request_percpu_irq(armada_370_xp_clkevt_irq,
ddd3f69f	313	armada_370_xp_timer_interrupt,
5ddb6d21 SB	314	"armada_370_xp_per_cpu_tick",
	315	armada_370_xp_evt);
	316	/* Immediately configure the timer on the boot CPU */
12549e27 DL	317	if (res) {
	318	pr_err("Failed to request percpu irq");
	319	return res;
	320	}
	321
2c48fef7 RC	322	res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
	323	"AP_ARMADA_TIMER_STARTING",
	324	armada_370_xp_timer_starting_cpu,
	325	armada_370_xp_timer_dying_cpu);
1d661bf5	326	if (res) {
2c48fef7	327	pr_err("Failed to setup hotplug state and timer");
12549e27 DL	328	return res;
12549e27 DL	329	}
f9a49ab5 TP	330
f9a49ab5 TP	331	register_syscore_ops(&armada_370_xp_timer_syscore_ops);
12549e27 DL	332
12549e27 DL	333	return 0;
ddd3f69f	334	}
7cd6392c	335
12549e27	336	static int __init armada_xp_timer_init(struct device_node *np)
7cd6392c	337	{
5e9fe6cb	338	struct clk *clk = of_clk_get_by_name(np, "fixed");
12549e27 DL	339	int ret;
12549e27 DL	340
12549e27 DL	341	if (IS_ERR(clk)) {
	342	pr_err("Failed to get clock");
	343	return PTR_ERR(clk);
	344	}
	345
	346	ret = clk_prepare_enable(clk);
	347	if (ret)
	348	return ret;
5e9fe6cb	349
5e9fe6cb	350	timer_clk = clk_get_rate(clk);
7cd6392c	351
12549e27	352	return armada_370_xp_timer_common_init(np);
7cd6392c	353	}
177cf6e5	354	CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
7cd6392c EG	355	armada_xp_timer_init);
7cd6392c EG	356
12549e27	357	static int __init armada_375_timer_init(struct device_node *np)
4a22d9c9 EG	358	{
4a22d9c9 EG	359	struct clk *clk;
12549e27	360	int ret;
4a22d9c9 EG	361
	362	clk = of_clk_get_by_name(np, "fixed");
	363	if (!IS_ERR(clk)) {
12549e27 DL	364	ret = clk_prepare_enable(clk);
	365	if (ret)
	366	return ret;
4a22d9c9 EG	367	timer_clk = clk_get_rate(clk);
	368	} else {
	369
	370	/*
	371	* This fallback is required in order to retain proper
	372	* devicetree backwards compatibility.
	373	*/
	374	clk = of_clk_get(np, 0);
	375
	376	/* Must have at least a clock */
12549e27 DL	377	if (IS_ERR(clk)) {
	378	pr_err("Failed to get clock");
	379	return PTR_ERR(clk);
	380	}
	381
	382	ret = clk_prepare_enable(clk);
	383	if (ret)
	384	return ret;
	385
4a22d9c9 EG	386	timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
	387	timer25Mhz = false;
	388	}
	389
12549e27	390	return armada_370_xp_timer_common_init(np);
4a22d9c9	391	}
177cf6e5	392	CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
4a22d9c9 EG	393	armada_375_timer_init);
4a22d9c9 EG	394
12549e27	395	static int __init armada_370_timer_init(struct device_node *np)
7cd6392c	396	{
12549e27 DL	397	struct clk *clk;
	398	int ret;
	399
	400	clk = of_clk_get(np, 0);
	401	if (IS_ERR(clk)) {
	402	pr_err("Failed to get clock");
	403	return PTR_ERR(clk);
	404	}
	405
	406	ret = clk_prepare_enable(clk);
	407	if (ret)
	408	return ret;
7cd6392c	409
7cd6392c EG	410	timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
	411	timer25Mhz = false;
	412
12549e27	413	return armada_370_xp_timer_common_init(np);
ddd3f69f	414	}
177cf6e5	415	CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
7cd6392c	416	armada_370_timer_init);