[mirror_ubuntu-zesty-kernel.git] / drivers / clocksource / timer-atlas7.c

/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>

#define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
#define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
#define SIRFSOC_TIMER_MATCH_0				0x0018
#define SIRFSOC_TIMER_MATCH_1				0x001c
#define SIRFSOC_TIMER_COUNTER_0				0x0048
#define SIRFSOC_TIMER_COUNTER_1				0x004c
#define SIRFSOC_TIMER_INTR_STATUS			0x0060
#define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
#define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
#define SIRFSOC_TIMER_64COUNTER_LO			0x006c
#define SIRFSOC_TIMER_64COUNTER_HI			0x0070
#define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
#define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080

#define SIRFSOC_TIMER_REG_CNT 6

static unsigned long atlas7_timer_rate;

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_WATCHDOG_EN,
	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	SIRFSOC_TIMER_64COUNTER_CTRL,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* disable count and interrupt */
static inline void sirfsoc_timer_count_disable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* enable count and interrupt */
static inline void sirfsoc_timer_count_enable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* timer interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;
	int cpu = smp_processor_id();

	/* clear timer interrupt */
	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	if (clockevent_state_oneshot(ce))
		sirfsoc_timer_count_disable(cpu);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static cycle_t sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);

	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	/* disable timer first, then modify the related registers */
	sirfsoc_timer_count_disable(cpu);

	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
		4 * cpu);
	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
		4 * cpu);

	/* enable the tick */
	sirfsoc_timer_count_enable(cpu);

	return 0;
}

/* Oneshot is enabled in set_next_event */
static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
{
	sirfsoc_timer_count_disable(smp_processor_id());
	return 0;
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);

	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
}

static struct clock_event_device __percpu *sirfsoc_clockevent;

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

static struct irqaction sirfsoc_timer_irq = {
	.name = "sirfsoc_timer0",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static struct irqaction sirfsoc_timer1_irq = {
	.name = "sirfsoc_timer1",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
{
	int cpu = smp_processor_id();
	struct irqaction *action;

	if (cpu == 0)
		action = &sirfsoc_timer_irq;
	else
		action = &sirfsoc_timer1_irq;

	ce->irq = action->irq;
	ce->name = "local_timer";
	ce->features = CLOCK_EVT_FEAT_ONESHOT;
	ce->rating = 200;
	ce->set_state_shutdown = sirfsoc_timer_shutdown;
	ce->set_state_oneshot = sirfsoc_timer_shutdown;
	ce->tick_resume = sirfsoc_timer_shutdown;
	ce->set_next_event = sirfsoc_timer_set_next_event;
	clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	ce->cpumask = cpumask_of(cpu);

	action->dev_id = ce;
	BUG_ON(setup_irq(ce->irq, action));
	irq_force_affinity(action->irq, cpumask_of(cpu));

	clockevents_register_device(ce);
	return 0;
}

static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	sirfsoc_timer_count_disable(1);

	if (cpu == 0)
		remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	else
		remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
}

static int sirfsoc_cpu_notify(struct notifier_block *self,
			      unsigned long action, void *hcpu)
{
	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
		break;
	case CPU_DYING:
		sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block sirfsoc_cpu_nb = {
	.notifier_call = sirfsoc_cpu_notify,
};

static int __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	BUG_ON(!sirfsoc_clockevent);

	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));

	/* Immediately configure the timer on the boot CPU */
	return sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
}

/* initialize the kernel jiffy timer source */
static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
{
	struct clk *clk;

	clk = of_clk_get(np, 0);
	BUG_ON(IS_ERR(clk));

	BUG_ON(clk_prepare_enable(clk));

	atlas7_timer_rate = clk_get_rate(clk);

	/* timer dividers: 0, not divided */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);

	/* Initialize timer counters to 0 */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);

	/* Clear all interrupts */
	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));

	return sirfsoc_clockevent_init();
}

static int __init sirfsoc_of_timer_init(struct device_node *np)
{
	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base) {
		pr_err("unable to map timer cpu registers\n");
		return -ENXIO;
	}

	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
	if (!sirfsoc_timer_irq.irq) {
		pr_err("No irq passed for timer0 via DT\n");
		return -EINVAL;
	}

	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
	if (!sirfsoc_timer1_irq.irq) {
		pr_err("No irq passed for timer1 via DT\n");
		return -EINVAL;
	}

	return sirfsoc_atlas7_timer_init(np);
}
CLOCKSOURCE_OF_DECLARE_RET(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);
Commit	Line	Data
4898de3d BS	1	/*
	2	* System timer for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/clocksource.h>
05a65485	13	#include <linux/cpu.h>
4898de3d BS	14	#include <linux/bitops.h>
	15	#include <linux/irq.h>
	16	#include <linux/clk.h>
	17	#include <linux/slab.h>
	18	#include <linux/of.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/of_address.h>
38ff87f7	21	#include <linux/sched_clock.h>
980c51ab	22
4898de3d BS	23	#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
	24	#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
	25	#define SIRFSOC_TIMER_MATCH_0 0x0018
	26	#define SIRFSOC_TIMER_MATCH_1 0x001c
	27	#define SIRFSOC_TIMER_COUNTER_0 0x0048
	28	#define SIRFSOC_TIMER_COUNTER_1 0x004c
	29	#define SIRFSOC_TIMER_INTR_STATUS 0x0060
	30	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
	31	#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
	32	#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
	33	#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
	34	#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
	35	#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
	36	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
	37	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
	38
	39	#define SIRFSOC_TIMER_REG_CNT 6
	40
5833ac98	41	static unsigned long atlas7_timer_rate;
ef89af1f	42
4898de3d BS	43	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	44	SIRFSOC_TIMER_WATCHDOG_EN,
	45	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	46	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	47	SIRFSOC_TIMER_64COUNTER_CTRL,
	48	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	49	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
	50	};
	51
	52	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	53
	54	static void __iomem *sirfsoc_timer_base;
4898de3d BS	55
	56	/* disable count and interrupt */
	57	static inline void sirfsoc_timer_count_disable(int idx)
	58	{
	59	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
	60	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	61	}
	62
	63	/* enable count and interrupt */
	64	static inline void sirfsoc_timer_count_enable(int idx)
	65	{
28cf3567	66	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) \| 0x3,
4898de3d BS	67	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	68	}
	69
	70	/* timer interrupt handler */
	71	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	72	{
	73	struct clock_event_device *ce = dev_id;
	74	int cpu = smp_processor_id();
	75
	76	/* clear timer interrupt */
	77	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	78
1e729d37	79	if (clockevent_state_oneshot(ce))
4898de3d BS	80	sirfsoc_timer_count_disable(cpu);
	81
	82	ce->event_handler(ce);
	83
	84	return IRQ_HANDLED;
	85	}
	86
	87	/* read 64-bit timer counter */
	88	static cycle_t sirfsoc_timer_read(struct clocksource *cs)
	89	{
	90	u64 cycles;
	91
	92	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	93	BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	94
	95	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	96	cycles = (cycles << 32) \| readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
	97
	98	return cycles;
	99	}
	100
	101	static int sirfsoc_timer_set_next_event(unsigned long delta,
	102	struct clock_event_device *ce)
	103	{
	104	int cpu = smp_processor_id();
	105
28cf3567 HL	106	/* disable timer first, then modify the related registers */
	107	sirfsoc_timer_count_disable(cpu);
	108
4898de3d BS	109	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
	110	4 * cpu);
	111	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
	112	4 * cpu);
	113
	114	/* enable the tick */
	115	sirfsoc_timer_count_enable(cpu);
	116
	117	return 0;
	118	}
	119
1e729d37 VK	120	/* Oneshot is enabled in set_next_event */
1e729d37 VK	121	static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
4898de3d	122	{
4898de3d	123	sirfsoc_timer_count_disable(smp_processor_id());
1e729d37	124	return 0;
4898de3d BS	125	}
	126
	127	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
	128	{
	129	int i;
	130
	131	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
	132	sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	133	}
	134
	135	static void sirfsoc_clocksource_resume(struct clocksource *cs)
	136	{
	137	int i;
	138
	139	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
	140	writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	141
	142	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
	143	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	144	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
	145	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	146
	147	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	148	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	149	}
	150
05a65485	151	static struct clock_event_device __percpu *sirfsoc_clockevent;
4898de3d BS	152
	153	static struct clocksource sirfsoc_clocksource = {
	154	.name = "sirfsoc_clocksource",
	155	.rating = 200,
	156	.mask = CLOCKSOURCE_MASK(64),
	157	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	158	.read = sirfsoc_timer_read,
	159	.suspend = sirfsoc_clocksource_suspend,
	160	.resume = sirfsoc_clocksource_resume,
	161	};
	162
	163	static struct irqaction sirfsoc_timer_irq = {
	164	.name = "sirfsoc_timer0",
	165	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	166	.handler = sirfsoc_timer_interrupt,
4898de3d BS	167	};
4898de3d BS	168
4898de3d BS	169	static struct irqaction sirfsoc_timer1_irq = {
	170	.name = "sirfsoc_timer1",
	171	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	172	.handler = sirfsoc_timer_interrupt,
	173	};
	174
8c37bb3a	175	static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
4898de3d	176	{
05a65485 SB	177	int cpu = smp_processor_id();
	178	struct irqaction *action;
	179
	180	if (cpu == 0)
	181	action = &sirfsoc_timer_irq;
	182	else
	183	action = &sirfsoc_timer1_irq;
4898de3d	184
05a65485	185	ce->irq = action->irq;
4898de3d	186	ce->name = "local_timer";
05a65485 SB	187	ce->features = CLOCK_EVT_FEAT_ONESHOT;
05a65485 SB	188	ce->rating = 200;
1e729d37 VK	189	ce->set_state_shutdown = sirfsoc_timer_shutdown;
	190	ce->set_state_oneshot = sirfsoc_timer_shutdown;
	191	ce->tick_resume = sirfsoc_timer_shutdown;
4898de3d	192	ce->set_next_event = sirfsoc_timer_set_next_event;
5833ac98	193	clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60);
05a65485 SB	194	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	195	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	196	ce->cpumask = cpumask_of(cpu);
4898de3d	197
05a65485 SB	198	action->dev_id = ce;
05a65485 SB	199	BUG_ON(setup_irq(ce->irq, action));
f214be50	200	irq_force_affinity(action->irq, cpumask_of(cpu));
4898de3d BS	201
	202	clockevents_register_device(ce);
	203	return 0;
	204	}
	205
	206	static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
	207	{
05a65485 SB	208	int cpu = smp_processor_id();
05a65485 SB	209
4898de3d BS	210	sirfsoc_timer_count_disable(1);
4898de3d BS	211
05a65485 SB	212	if (cpu == 0)
	213	remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	214	else
	215	remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
4898de3d BS	216	}
4898de3d BS	217
47dcd356 OJ	218	static int sirfsoc_cpu_notify(struct notifier_block *self,
47dcd356 OJ	219	unsigned long action, void *hcpu)
05a65485 SB	220	{
	221	/*
	222	* Grab cpu pointer in each case to avoid spurious
	223	* preemptible warnings
	224	*/
	225	switch (action & ~CPU_TASKS_FROZEN) {
	226	case CPU_STARTING:
	227	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
	228	break;
	229	case CPU_DYING:
	230	sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
	231	break;
	232	}
	233
	234	return NOTIFY_OK;
	235	}
	236
47dcd356	237	static struct notifier_block sirfsoc_cpu_nb = {
05a65485	238	.notifier_call = sirfsoc_cpu_notify,
4898de3d	239	};
4898de3d	240
c41c96dd	241	static int __init sirfsoc_clockevent_init(void)
4898de3d	242	{
05a65485 SB	243	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	244	BUG_ON(!sirfsoc_clockevent);
	245
	246	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));
	247
	248	/* Immediately configure the timer on the boot CPU */
c41c96dd	249	return sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
4898de3d BS	250	}
	251
	252	/* initialize the kernel jiffy timer source */
c41c96dd	253	static int __init sirfsoc_atlas7_timer_init(struct device_node *np)
4898de3d	254	{
4898de3d BS	255	struct clk *clk;
4898de3d BS	256
c7cff54d	257	clk = of_clk_get(np, 0);
4898de3d	258	BUG_ON(IS_ERR(clk));
38941522 ZS	259
	260	BUG_ON(clk_prepare_enable(clk));
	261
5833ac98	262	atlas7_timer_rate = clk_get_rate(clk);
4898de3d	263
ef89af1f YL	264	/* timer dividers: 0, not divided */
	265	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	266	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	267	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
4898de3d BS	268
	269	/* Initialize timer counters to 0 */
	270	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	271	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	272	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	273	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	274	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	275	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
	276
	277	/* Clear all interrupts */
	278	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	279
5833ac98	280	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate));
4898de3d	281
c41c96dd	282	return sirfsoc_clockevent_init();
4898de3d BS	283	}
4898de3d BS	284
c41c96dd	285	static int __init sirfsoc_of_timer_init(struct device_node *np)
4898de3d	286	{
4898de3d	287	sirfsoc_timer_base = of_iomap(np, 0);
c41c96dd DL	288	if (!sirfsoc_timer_base) {
	289	pr_err("unable to map timer cpu registers\n");
	290	return -ENXIO;
	291	}
4898de3d BS	292
4898de3d BS	293	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
c41c96dd DL	294	if (!sirfsoc_timer_irq.irq) {
	295	pr_err("No irq passed for timer0 via DT\n");
	296	return -EINVAL;
	297	}
4898de3d	298
4898de3d	299	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
c41c96dd DL	300	if (!sirfsoc_timer1_irq.irq) {
	301	pr_err("No irq passed for timer1 via DT\n");
	302	return -EINVAL;
	303	}
4898de3d	304
c41c96dd	305	return sirfsoc_atlas7_timer_init(np);
4898de3d	306	}
c41c96dd	307	CLOCKSOURCE_OF_DECLARE_RET(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);