[mirror_ubuntu-hirsute-kernel.git] / drivers / clocksource / timer-atmel-tcb.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/syscore_ops.h>
#include <soc/at91/atmel_tcb.h>


/*
 * We're configured to use a specific TC block, one that's not hooked
 * up to external hardware, to provide a time solution:
 *
 *   - Two channels combine to create a free-running 32 bit counter
 *     with a base rate of 5+ MHz, packaged as a clocksource (with
 *     resolution better than 200 nsec).
 *   - Some chips support 32 bit counter. A single channel is used for
 *     this 32 bit free-running counter. the second channel is not used.
 *
 *   - The third channel may be used to provide a clockevent source, used in
 *   either periodic or oneshot mode. For 16-bit counter its runs at 32 KiHZ,
 *   and can handle delays of up to two seconds. For 32-bit counters, it runs at
 *   the same rate as the clocksource
 *
 * REVISIT behavior during system suspend states... we should disable
 * all clocks and save the power.  Easily done for clockevent devices,
 * but clocksources won't necessarily get the needed notifications.
 * For deeper system sleep states, this will be mandatory...
 */

static void __iomem *tcaddr;
static struct
{
	u32 cmr;
	u32 imr;
	u32 rc;
	bool clken;
} tcb_cache[3];
static u32 bmr_cache;

static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };

static u64 tc_get_cycles(struct clocksource *cs)
{
	unsigned long	flags;
	u32		lower, upper;

	raw_local_irq_save(flags);
	do {
		upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
		lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));

	raw_local_irq_restore(flags);
	return (upper << 16) | lower;
}

static u64 tc_get_cycles32(struct clocksource *cs)
{
	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
}

static void tc_clksrc_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
		tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
		tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
		tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
		tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
					ATMEL_TC_CLKSTA);
	}

	bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
}

static void tc_clksrc_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
		/* Restore registers for the channel, RA and RB are not used  */
		writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
		writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
		writel(0, tcaddr + ATMEL_TC_REG(i, RA));
		writel(0, tcaddr + ATMEL_TC_REG(i, RB));
		/* Disable all the interrupts */
		writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
		/* Reenable interrupts that were enabled before suspending */
		writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
		/* Start the clock if it was used */
		if (tcb_cache[i].clken)
			writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
	}

	/* Dual channel, chain channels */
	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
	/* Finally, trigger all the channels*/
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static struct clocksource clksrc = {
	.rating         = 200,
	.read           = tc_get_cycles,
	.mask           = CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.suspend	= tc_clksrc_suspend,
	.resume		= tc_clksrc_resume,
};

static u64 notrace tc_sched_clock_read(void)
{
	return tc_get_cycles(&clksrc);
}

static u64 notrace tc_sched_clock_read32(void)
{
	return tc_get_cycles32(&clksrc);
}

static struct delay_timer tc_delay_timer;

static unsigned long tc_delay_timer_read(void)
{
	return tc_get_cycles(&clksrc);
}

static unsigned long notrace tc_delay_timer_read32(void)
{
	return tc_get_cycles32(&clksrc);
}

#ifdef CONFIG_GENERIC_CLOCKEVENTS

struct tc_clkevt_device {
	struct clock_event_device	clkevt;
	struct clk			*clk;
	u32				rate;
	void __iomem			*regs;
};

static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
{
	return container_of(clkevt, struct tc_clkevt_device, clkevt);
}

static u32 timer_clock;

static int tc_shutdown(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	writel(0xff, regs + ATMEL_TC_REG(2, IDR));
	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
	if (!clockevent_state_detached(d))
		clk_disable(tcd->clk);

	return 0;
}

static int tc_set_oneshot(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	clk_enable(tcd->clk);

	/* count up to RC, then irq and stop */
	writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* set_next_event() configures and starts the timer */
	return 0;
}

static int tc_set_periodic(struct clock_event_device *d)
{
	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	void __iomem		*regs = tcd->regs;

	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
		tc_shutdown(d);

	/* By not making the gentime core emulate periodic mode on top
	 * of oneshot, we get lower overhead and improved accuracy.
	 */
	clk_enable(tcd->clk);

	/* count up to RC, then irq and restart */
	writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
		     regs + ATMEL_TC_REG(2, CMR));
	writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));

	/* Enable clock and interrupts on RC compare */
	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));

	/* go go gadget! */
	writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
		     ATMEL_TC_REG(2, CCR));
	return 0;
}

static int tc_next_event(unsigned long delta, struct clock_event_device *d)
{
	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));

	/* go go gadget! */
	writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
			tcaddr + ATMEL_TC_REG(2, CCR));
	return 0;
}

static struct tc_clkevt_device clkevt = {
	.clkevt	= {
		.features		= CLOCK_EVT_FEAT_PERIODIC |
					  CLOCK_EVT_FEAT_ONESHOT,
		/* Should be lower than at91rm9200's system timer */
		.rating			= 125,
		.set_next_event		= tc_next_event,
		.set_state_shutdown	= tc_shutdown,
		.set_state_periodic	= tc_set_periodic,
		.set_state_oneshot	= tc_set_oneshot,
	},
};

static irqreturn_t ch2_irq(int irq, void *handle)
{
	struct tc_clkevt_device	*dev = handle;
	unsigned int		sr;

	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
	if (sr & ATMEL_TC_CPCS) {
		dev->clkevt.event_handler(&dev->clkevt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
{
	int ret;
	struct clk *t2_clk = tc->clk[2];
	int irq = tc->irq[2];
	int bits = tc->tcb_config->counter_width;

	/* try to enable t2 clk to avoid future errors in mode change */
	ret = clk_prepare_enable(t2_clk);
	if (ret)
		return ret;

	clkevt.regs = tc->regs;
	clkevt.clk = t2_clk;

	if (bits == 32) {
		timer_clock = divisor_idx;
		clkevt.rate = clk_get_rate(t2_clk) / atmel_tcb_divisors[divisor_idx];
	} else {
		ret = clk_prepare_enable(tc->slow_clk);
		if (ret) {
			clk_disable_unprepare(t2_clk);
			return ret;
		}

		clkevt.rate = clk_get_rate(tc->slow_clk);
		timer_clock = ATMEL_TC_TIMER_CLOCK5;
	}

	clk_disable(t2_clk);

	clkevt.clkevt.cpumask = cpumask_of(0);

	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
	if (ret) {
		clk_unprepare(t2_clk);
		if (bits != 32)
			clk_disable_unprepare(tc->slow_clk);
		return ret;
	}

	clockevents_config_and_register(&clkevt.clkevt, clkevt.rate, 1, BIT(bits) - 1);

	return ret;
}

#else /* !CONFIG_GENERIC_CLOCKEVENTS */

static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
{
	/* NOTHING */
	return 0;
}

#endif

static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
	writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP		/* free-run */
			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
			tcaddr + ATMEL_TC_REG(0, CMR));
	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* channel 1:  waveform mode, input TIOA0 */
	writel(ATMEL_TC_XC1			/* input: TIOA0 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(1, CMR));
	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));

	/* chain channel 0 to channel 1*/
	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
	/* then reset all the timers */
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
{
	/* channel 0:  waveform mode, input mclk/8 */
	writel(mck_divisor_idx			/* likely divide-by-8 */
			| ATMEL_TC_WAVE
			| ATMEL_TC_WAVESEL_UP,		/* free-run */
			tcaddr + ATMEL_TC_REG(0, CMR));
	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));

	/* then reset all the timers */
	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}

static struct atmel_tcb_config tcb_rm9200_config = {
	.counter_width = 16,
};

static struct atmel_tcb_config tcb_sam9x5_config = {
	.counter_width = 32,
};

static struct atmel_tcb_config tcb_sama5d2_config = {
	.counter_width = 32,
	.has_gclk = 1,
};

static const struct of_device_id atmel_tcb_of_match[] = {
	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
	{ /* sentinel */ }
};

static int __init tcb_clksrc_init(struct device_node *node)
{
	struct atmel_tc tc;
	struct clk *t0_clk;
	const struct of_device_id *match;
	u64 (*tc_sched_clock)(void);
	u32 rate, divided_rate = 0;
	int best_divisor_idx = -1;
	int bits;
	int i;
	int ret;

	/* Protect against multiple calls */
	if (tcaddr)
		return 0;

	tc.regs = of_iomap(node->parent, 0);
	if (!tc.regs)
		return -ENXIO;

	t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
	if (IS_ERR(t0_clk))
		return PTR_ERR(t0_clk);

	tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
	if (IS_ERR(tc.slow_clk))
		return PTR_ERR(tc.slow_clk);

	tc.clk[0] = t0_clk;
	tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
	if (IS_ERR(tc.clk[1]))
		tc.clk[1] = t0_clk;
	tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
	if (IS_ERR(tc.clk[2]))
		tc.clk[2] = t0_clk;

	tc.irq[2] = of_irq_get(node->parent, 2);
	if (tc.irq[2] <= 0) {
		tc.irq[2] = of_irq_get(node->parent, 0);
		if (tc.irq[2] <= 0)
			return -EINVAL;
	}

	match = of_match_node(atmel_tcb_of_match, node->parent);
	if (!match)
		return -ENODEV;

	tc.tcb_config = match->data;
	bits = tc.tcb_config->counter_width;

	for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
		writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));

	ret = clk_prepare_enable(t0_clk);
	if (ret) {
		pr_debug("can't enable T0 clk\n");
		return ret;
	}

	/* How fast will we be counting?  Pick something over 5 MHz.  */
	rate = (u32) clk_get_rate(t0_clk);
	i = 0;
	if (tc.tcb_config->has_gclk)
		i = 1;
	for (; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
		unsigned divisor = atmel_tcb_divisors[i];
		unsigned tmp;

		tmp = rate / divisor;
		pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
		if ((best_divisor_idx >= 0) && (tmp < 5 * 1000 * 1000))
			break;
		divided_rate = tmp;
		best_divisor_idx = i;
	}

	clksrc.name = kbasename(node->parent->full_name);
	clkevt.clkevt.name = kbasename(node->parent->full_name);
	pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
			((divided_rate % 1000000) + 500) / 1000);

	tcaddr = tc.regs;

	if (bits == 32) {
		/* use apropriate function to read 32 bit counter */
		clksrc.read = tc_get_cycles32;
		/* setup ony channel 0 */
		tcb_setup_single_chan(&tc, best_divisor_idx);
		tc_sched_clock = tc_sched_clock_read32;
		tc_delay_timer.read_current_timer = tc_delay_timer_read32;
	} else {
		/* we have three clocks no matter what the
		 * underlying platform supports.
		 */
		ret = clk_prepare_enable(tc.clk[1]);
		if (ret) {
			pr_debug("can't enable T1 clk\n");
			goto err_disable_t0;
		}
		/* setup both channel 0 & 1 */
		tcb_setup_dual_chan(&tc, best_divisor_idx);
		tc_sched_clock = tc_sched_clock_read;
		tc_delay_timer.read_current_timer = tc_delay_timer_read;
	}

	/* and away we go! */
	ret = clocksource_register_hz(&clksrc, divided_rate);
	if (ret)
		goto err_disable_t1;

	/* channel 2:  periodic and oneshot timer support */
	ret = setup_clkevents(&tc, best_divisor_idx);
	if (ret)
		goto err_unregister_clksrc;

	sched_clock_register(tc_sched_clock, 32, divided_rate);

	tc_delay_timer.freq = divided_rate;
	register_current_timer_delay(&tc_delay_timer);

	return 0;

err_unregister_clksrc:
	clocksource_unregister(&clksrc);

err_disable_t1:
	if (bits != 32)
		clk_disable_unprepare(tc.clk[1]);

err_disable_t0:
	clk_disable_unprepare(t0_clk);

	tcaddr = NULL;

	return ret;
}
TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
4d243f92 DB	2	#include <linux/init.h>
	3	#include <linux/clocksource.h>
	4	#include <linux/clockchips.h>
	5	#include <linux/interrupt.h>
	6	#include <linux/irq.h>
	7
	8	#include <linux/clk.h>
1ce861ce	9	#include <linux/delay.h>
4d243f92 DB	10	#include <linux/err.h>
	11	#include <linux/ioport.h>
	12	#include <linux/io.h>
86232bfd AB	13	#include <linux/of_address.h>
86232bfd AB	14	#include <linux/of_irq.h>
f712a1e8	15	#include <linux/sched_clock.h>
2a515e5d	16	#include <linux/syscore_ops.h>
c2c9136b	17	#include <soc/at91/atmel_tcb.h>
4d243f92 DB	18
	19
	20	/*
	21	* We're configured to use a specific TC block, one that's not hooked
	22	* up to external hardware, to provide a time solution:
	23	*
	24	* - Two channels combine to create a free-running 32 bit counter
	25	* with a base rate of 5+ MHz, packaged as a clocksource (with
	26	* resolution better than 200 nsec).
8e315a7b NF	27	* - Some chips support 32 bit counter. A single channel is used for
8e315a7b NF	28	* this 32 bit free-running counter. the second channel is not used.
4d243f92	29	*
ef1d6a20 AB	30	* - The third channel may be used to provide a clockevent source, used in
	31	* either periodic or oneshot mode. For 16-bit counter its runs at 32 KiHZ,
	32	* and can handle delays of up to two seconds. For 32-bit counters, it runs at
	33	* the same rate as the clocksource
4d243f92	34	*
4d243f92 DB	35	* REVISIT behavior during system suspend states... we should disable
	36	* all clocks and save the power. Easily done for clockevent devices,
	37	* but clocksources won't necessarily get the needed notifications.
	38	* For deeper system sleep states, this will be mandatory...
	39	*/
	40
	41	static void __iomem *tcaddr;
2a515e5d AB	42	static struct
	43	{
	44	u32 cmr;
	45	u32 imr;
	46	u32 rc;
	47	bool clken;
	48	} tcb_cache[3];
	49	static u32 bmr_cache;
4d243f92	50
ef1d6a20 AB	51	static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
ef1d6a20 AB	52
a5a1d1c2	53	static u64 tc_get_cycles(struct clocksource *cs)
4d243f92 DB	54	{
	55	unsigned long flags;
	56	u32 lower, upper;
	57
	58	raw_local_irq_save(flags);
	59	do {
6ec8be25 AB	60	upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
	61	lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
	62	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
4d243f92 DB	63
	64	raw_local_irq_restore(flags);
	65	return (upper << 16) \| lower;
	66	}
	67
7b9f1d16 DE	68	static u64 tc_get_cycles32(struct clocksource *cs)
7b9f1d16 DE	69	{
6ec8be25	70	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
7b9f1d16 DE	71	}
7b9f1d16 DE	72
7ebe6810	73	static void tc_clksrc_suspend(struct clocksource *cs)
2a515e5d AB	74	{
	75	int i;
	76
	77	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
	78	tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
	79	tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
	80	tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
	81	tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
	82	ATMEL_TC_CLKSTA);
	83	}
	84
	85	bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
	86	}
	87
7ebe6810	88	static void tc_clksrc_resume(struct clocksource *cs)
2a515e5d AB	89	{
	90	int i;
	91
	92	for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
	93	/* Restore registers for the channel, RA and RB are not used */
	94	writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
	95	writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
	96	writel(0, tcaddr + ATMEL_TC_REG(i, RA));
	97	writel(0, tcaddr + ATMEL_TC_REG(i, RB));
	98	/* Disable all the interrupts */
	99	writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
	100	/* Reenable interrupts that were enabled before suspending */
	101	writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
	102	/* Start the clock if it was used */
	103	if (tcb_cache[i].clken)
	104	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
	105	}
	106
	107	/* Dual channel, chain channels */
	108	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
	109	/* Finally, trigger all the channels*/
	110	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
	111	}
	112
4d243f92	113	static struct clocksource clksrc = {
4d243f92 DB	114	.rating = 200,
	115	.read = tc_get_cycles,
	116	.mask = CLOCKSOURCE_MASK(32),
4d243f92	117	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
2a515e5d AB	118	.suspend = tc_clksrc_suspend,
2a515e5d AB	119	.resume = tc_clksrc_resume,
4d243f92 DB	120	};
4d243f92 DB	121
f712a1e8 AB	122	static u64 notrace tc_sched_clock_read(void)
	123	{
	124	return tc_get_cycles(&clksrc);
	125	}
	126
	127	static u64 notrace tc_sched_clock_read32(void)
	128	{
	129	return tc_get_cycles32(&clksrc);
	130	}
	131
1ce861ce AB	132	static struct delay_timer tc_delay_timer;
	133
	134	static unsigned long tc_delay_timer_read(void)
	135	{
	136	return tc_get_cycles(&clksrc);
	137	}
	138
	139	static unsigned long notrace tc_delay_timer_read32(void)
	140	{
	141	return tc_get_cycles32(&clksrc);
	142	}
	143
4d243f92 DB	144	#ifdef CONFIG_GENERIC_CLOCKEVENTS
	145
	146	struct tc_clkevt_device {
	147	struct clock_event_device clkevt;
	148	struct clk *clk;
ef1d6a20	149	u32 rate;
4d243f92 DB	150	void __iomem *regs;
	151	};
	152
	153	static struct tc_clkevt_device to_tc_clkevt(struct clock_event_device clkevt)
	154	{
	155	return container_of(clkevt, struct tc_clkevt_device, clkevt);
	156	}
	157
4d243f92 DB	158	static u32 timer_clock;
4d243f92 DB	159
cf4541c1	160	static int tc_shutdown(struct clock_event_device *d)
4d243f92 DB	161	{
	162	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	163	void __iomem *regs = tcd->regs;
	164
6ec8be25 AB	165	writel(0xff, regs + ATMEL_TC_REG(2, IDR));
6ec8be25 AB	166	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
f02b4b72 AB	167	if (!clockevent_state_detached(d))
f02b4b72 AB	168	clk_disable(tcd->clk);
4d243f92	169
cf4541c1 VK	170	return 0;
cf4541c1 VK	171	}
4d243f92	172
cf4541c1 VK	173	static int tc_set_oneshot(struct clock_event_device *d)
	174	{
	175	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	176	void __iomem *regs = tcd->regs;
4d243f92	177
cf4541c1 VK	178	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	179	tc_shutdown(d);
4d243f92	180
cf4541c1	181	clk_enable(tcd->clk);
4d243f92	182
ef1d6a20	183	/* count up to RC, then irq and stop */
6ec8be25	184	writel(timer_clock \| ATMEL_TC_CPCSTOP \| ATMEL_TC_WAVE \|
cf4541c1	185	ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
6ec8be25	186	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
4d243f92	187
cf4541c1 VK	188	/* set_next_event() configures and starts the timer */
	189	return 0;
	190	}
4d243f92	191
cf4541c1 VK	192	static int tc_set_periodic(struct clock_event_device *d)
	193	{
	194	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
	195	void __iomem *regs = tcd->regs;
4d243f92	196
cf4541c1 VK	197	if (clockevent_state_oneshot(d) \|\| clockevent_state_periodic(d))
cf4541c1 VK	198	tc_shutdown(d);
4d243f92	199
cf4541c1 VK	200	/* By not making the gentime core emulate periodic mode on top
	201	* of oneshot, we get lower overhead and improved accuracy.
	202	*/
	203	clk_enable(tcd->clk);
	204
ef1d6a20	205	/* count up to RC, then irq and restart */
6ec8be25	206	writel(timer_clock \| ATMEL_TC_WAVE \| ATMEL_TC_WAVESEL_UP_AUTO,
cf4541c1	207	regs + ATMEL_TC_REG(2, CMR));
ef1d6a20	208	writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
cf4541c1 VK	209
cf4541c1 VK	210	/* Enable clock and interrupts on RC compare */
6ec8be25	211	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
cf4541c1 VK	212
cf4541c1 VK	213	/* go go gadget! */
6ec8be25	214	writel(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG, regs +
cf4541c1 VK	215	ATMEL_TC_REG(2, CCR));
cf4541c1 VK	216	return 0;
4d243f92 DB	217	}
	218
	219	static int tc_next_event(unsigned long delta, struct clock_event_device *d)
	220	{
6ec8be25	221	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
4d243f92 DB	222
4d243f92 DB	223	/* go go gadget! */
6ec8be25	224	writel_relaxed(ATMEL_TC_CLKEN \| ATMEL_TC_SWTRG,
4d243f92 DB	225	tcaddr + ATMEL_TC_REG(2, CCR));
	226	return 0;
	227	}
	228
	229	static struct tc_clkevt_device clkevt = {
	230	.clkevt = {
cf4541c1 VK	231	.features = CLOCK_EVT_FEAT_PERIODIC \|
cf4541c1 VK	232	CLOCK_EVT_FEAT_ONESHOT,
4d243f92	233	/* Should be lower than at91rm9200's system timer */
cf4541c1 VK	234	.rating = 125,
	235	.set_next_event = tc_next_event,
	236	.set_state_shutdown = tc_shutdown,
	237	.set_state_periodic = tc_set_periodic,
	238	.set_state_oneshot = tc_set_oneshot,
4d243f92 DB	239	},
	240	};
	241
	242	static irqreturn_t ch2_irq(int irq, void *handle)
	243	{
	244	struct tc_clkevt_device *dev = handle;
	245	unsigned int sr;
	246
6ec8be25	247	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
4d243f92 DB	248	if (sr & ATMEL_TC_CPCS) {
	249	dev->clkevt.event_handler(&dev->clkevt);
	250	return IRQ_HANDLED;
	251	}
	252
	253	return IRQ_NONE;
	254	}
	255
ef1d6a20	256	static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
4d243f92	257	{
5b3c11da	258	int ret;
4d243f92 DB	259	struct clk *t2_clk = tc->clk[2];
4d243f92 DB	260	int irq = tc->irq[2];
ef1d6a20	261	int bits = tc->tcb_config->counter_width;
7d8d05d1	262
5b3c11da BB	263	/* try to enable t2 clk to avoid future errors in mode change */
5b3c11da BB	264	ret = clk_prepare_enable(t2_clk);
ef1d6a20	265	if (ret)
5b3c11da	266	return ret;
5b3c11da	267
4d243f92 DB	268	clkevt.regs = tc->regs;
4d243f92 DB	269	clkevt.clk = t2_clk;
4d243f92	270
ef1d6a20 AB	271	if (bits == 32) {
	272	timer_clock = divisor_idx;
	273	clkevt.rate = clk_get_rate(t2_clk) / atmel_tcb_divisors[divisor_idx];
	274	} else {
	275	ret = clk_prepare_enable(tc->slow_clk);
	276	if (ret) {
	277	clk_disable_unprepare(t2_clk);
	278	return ret;
	279	}
	280
	281	clkevt.rate = clk_get_rate(tc->slow_clk);
	282	timer_clock = ATMEL_TC_TIMER_CLOCK5;
	283	}
	284
	285	clk_disable(t2_clk);
4d243f92	286
320ab2b0	287	clkevt.clkevt.cpumask = cpumask_of(0);
4d243f92	288
d07a1ecd GP	289	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
d07a1ecd GP	290	if (ret) {
eed9fb9d	291	clk_unprepare(t2_clk);
ef1d6a20 AB	292	if (bits != 32)
ef1d6a20 AB	293	clk_disable_unprepare(tc->slow_clk);
5b3c11da	294	return ret;
d07a1ecd	295	}
5b3c11da	296
ef1d6a20	297	clockevents_config_and_register(&clkevt.clkevt, clkevt.rate, 1, BIT(bits) - 1);
1817dc03	298
5b3c11da	299	return ret;
4d243f92 DB	300	}
	301
	302	#else /* !CONFIG_GENERIC_CLOCKEVENTS */
	303
ef1d6a20	304	static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
4d243f92 DB	305	{
4d243f92 DB	306	/* NOTHING */
5b3c11da	307	return 0;
4d243f92 DB	308	}
	309
	310	#endif
	311
8e315a7b NF	312	static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
	313	{
	314	/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
6ec8be25	315	writel(mck_divisor_idx /* likely divide-by-8 */
8e315a7b NF	316	\| ATMEL_TC_WAVE
	317	\| ATMEL_TC_WAVESEL_UP /* free-run */
	318	\| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
	319	\| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
	320	tcaddr + ATMEL_TC_REG(0, CMR));
6ec8be25 AB	321	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
	322	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
	323	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
	324	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
8e315a7b NF	325
8e315a7b NF	326	/* channel 1: waveform mode, input TIOA0 */
6ec8be25	327	writel(ATMEL_TC_XC1 /* input: TIOA0 */
8e315a7b NF	328	\| ATMEL_TC_WAVE
	329	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	330	tcaddr + ATMEL_TC_REG(1, CMR));
6ec8be25 AB	331	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
6ec8be25 AB	332	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
8e315a7b NF	333
8e315a7b NF	334	/* chain channel 0 to channel 1*/
6ec8be25	335	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
8e315a7b	336	/* then reset all the timers */
6ec8be25	337	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
8e315a7b NF	338	}
	339
	340	static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
	341	{
	342	/* channel 0: waveform mode, input mclk/8 */
6ec8be25	343	writel(mck_divisor_idx /* likely divide-by-8 */
8e315a7b NF	344	\| ATMEL_TC_WAVE
	345	\| ATMEL_TC_WAVESEL_UP, /* free-run */
	346	tcaddr + ATMEL_TC_REG(0, CMR));
6ec8be25 AB	347	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
6ec8be25 AB	348	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
8e315a7b NF	349
8e315a7b NF	350	/* then reset all the timers */
6ec8be25	351	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
8e315a7b NF	352	}
8e315a7b NF	353
d2c60dcf AB	354	static struct atmel_tcb_config tcb_rm9200_config = {
	355	.counter_width = 16,
	356	};
	357
	358	static struct atmel_tcb_config tcb_sam9x5_config = {
	359	.counter_width = 32,
	360	};
	361
467ae18a AB	362	static struct atmel_tcb_config tcb_sama5d2_config = {
	363	.counter_width = 32,
	364	.has_gclk = 1,
	365	};
	366
86232bfd	367	static const struct of_device_id atmel_tcb_of_match[] = {
d2c60dcf AB	368	{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
d2c60dcf AB	369	{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
467ae18a	370	{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
86232bfd AB	371	{ /* sentinel */ }
86232bfd AB	372	};
4d243f92	373
86232bfd AB	374	static int __init tcb_clksrc_init(struct device_node *node)
	375	{
	376	struct atmel_tc tc;
3ee08aea	377	struct clk *t0_clk;
86232bfd	378	const struct of_device_id *match;
f712a1e8	379	u64 (*tc_sched_clock)(void);
4d243f92 DB	380	u32 rate, divided_rate = 0;
4d243f92 DB	381	int best_divisor_idx = -1;
86232bfd	382	int bits;
4d243f92	383	int i;
0e746ec5	384	int ret;
4d243f92	385
86232bfd AB	386	/* Protect against multiple calls */
	387	if (tcaddr)
	388	return 0;
	389
	390	tc.regs = of_iomap(node->parent, 0);
	391	if (!tc.regs)
	392	return -ENXIO;
	393
	394	t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
	395	if (IS_ERR(t0_clk))
	396	return PTR_ERR(t0_clk);
	397
	398	tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
	399	if (IS_ERR(tc.slow_clk))
	400	return PTR_ERR(tc.slow_clk);
	401
	402	tc.clk[0] = t0_clk;
	403	tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
	404	if (IS_ERR(tc.clk[1]))
	405	tc.clk[1] = t0_clk;
	406	tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
	407	if (IS_ERR(tc.clk[2]))
	408	tc.clk[2] = t0_clk;
	409
	410	tc.irq[2] = of_irq_get(node->parent, 2);
	411	if (tc.irq[2] <= 0) {
	412	tc.irq[2] = of_irq_get(node->parent, 0);
	413	if (tc.irq[2] <= 0)
	414	return -EINVAL;
4d243f92	415	}
4d243f92	416
86232bfd	417	match = of_match_node(atmel_tcb_of_match, node->parent);
d2c60dcf AB	418	if (!match)
	419	return -ENODEV;
	420
	421	tc.tcb_config = match->data;
	422	bits = tc.tcb_config->counter_width;
86232bfd AB	423
	424	for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
	425	writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
	426
0e746ec5 BB	427	ret = clk_prepare_enable(t0_clk);
	428	if (ret) {
	429	pr_debug("can't enable T0 clk\n");
86232bfd	430	return ret;
0e746ec5	431	}
4d243f92 DB	432
	433	/* How fast will we be counting? Pick something over 5 MHz. */
	434	rate = (u32) clk_get_rate(t0_clk);
467ae18a AB	435	i = 0;
	436	if (tc.tcb_config->has_gclk)
	437	i = 1;
	438	for (; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
86232bfd	439	unsigned divisor = atmel_tcb_divisors[i];
4d243f92 DB	440	unsigned tmp;
4d243f92 DB	441
4d243f92 DB	442	tmp = rate / divisor;
4d243f92 DB	443	pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
501465d5 AB	444	if ((best_divisor_idx >= 0) && (tmp < 5 * 1000 * 1000))
501465d5 AB	445	break;
4d243f92 DB	446	divided_rate = tmp;
	447	best_divisor_idx = i;
	448	}
	449
86232bfd AB	450	clksrc.name = kbasename(node->parent->full_name);
	451	clkevt.clkevt.name = kbasename(node->parent->full_name);
	452	pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
542f8246	453	((divided_rate % 1000000) + 500) / 1000);
4d243f92	454
86232bfd AB	455	tcaddr = tc.regs;
	456
	457	if (bits == 32) {
8e315a7b NF	458	/* use apropriate function to read 32 bit counter */
	459	clksrc.read = tc_get_cycles32;
	460	/* setup ony channel 0 */
86232bfd	461	tcb_setup_single_chan(&tc, best_divisor_idx);
f712a1e8	462	tc_sched_clock = tc_sched_clock_read32;
1ce861ce	463	tc_delay_timer.read_current_timer = tc_delay_timer_read32;
8e315a7b	464	} else {
86232bfd	465	/* we have three clocks no matter what the
8e315a7b NF	466	* underlying platform supports.
8e315a7b NF	467	*/
86232bfd	468	ret = clk_prepare_enable(tc.clk[1]);
0e746ec5 BB	469	if (ret) {
	470	pr_debug("can't enable T1 clk\n");
	471	goto err_disable_t0;
	472	}
8e315a7b	473	/* setup both channel 0 & 1 */
86232bfd	474	tcb_setup_dual_chan(&tc, best_divisor_idx);
f712a1e8	475	tc_sched_clock = tc_sched_clock_read;
1ce861ce	476	tc_delay_timer.read_current_timer = tc_delay_timer_read;
8e315a7b	477	}
4d243f92 DB	478
4d243f92 DB	479	/* and away we go! */
5b3c11da BB	480	ret = clocksource_register_hz(&clksrc, divided_rate);
	481	if (ret)
	482	goto err_disable_t1;
4d243f92 DB	483
4d243f92 DB	484	/* channel 2: periodic and oneshot timer support */
ef1d6a20	485	ret = setup_clkevents(&tc, best_divisor_idx);
5b3c11da BB	486	if (ret)
5b3c11da BB	487	goto err_unregister_clksrc;
4d243f92	488
f712a1e8 AB	489	sched_clock_register(tc_sched_clock, 32, divided_rate);
f712a1e8 AB	490
1ce861ce AB	491	tc_delay_timer.freq = divided_rate;
	492	register_current_timer_delay(&tc_delay_timer);
	493
4d243f92	494	return 0;
0e746ec5	495
5b3c11da BB	496	err_unregister_clksrc:
	497	clocksource_unregister(&clksrc);
	498
	499	err_disable_t1:
86232bfd AB	500	if (bits != 32)
86232bfd AB	501	clk_disable_unprepare(tc.clk[1]);
5b3c11da	502
0e746ec5 BB	503	err_disable_t0:
	504	clk_disable_unprepare(t0_clk);
	505
86232bfd AB	506	tcaddr = NULL;
86232bfd AB	507
0e746ec5	508	return ret;
4d243f92	509	}
86232bfd	510	TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);