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9b8bb773 BS |
1 | /* |
2 | * Conexant Digicolor timer driver | |
3 | * | |
4 | * Author: Baruch Siach <baruch@tkos.co.il> | |
5 | * | |
6 | * Copyright (C) 2014 Paradox Innovation Ltd. | |
7 | * | |
8 | * Based on: | |
9 | * Allwinner SoCs hstimer driver | |
10 | * | |
11 | * Copyright (C) 2013 Maxime Ripard | |
12 | * | |
13 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
14 | * | |
15 | * This file is licensed under the terms of the GNU General Public | |
16 | * License version 2. This program is licensed "as is" without any | |
17 | * warranty of any kind, whether express or implied. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * Conexant Digicolor SoCs have 8 configurable timers, named from "Timer A" to | |
22 | * "Timer H". Timer A is the only one with watchdog support, so it is dedicated | |
23 | * to the watchdog driver. This driver uses Timer B for sched_clock(), and | |
24 | * Timer C for clockevents. | |
25 | */ | |
26 | ||
27 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
28 | ||
29 | #include <linux/clk.h> | |
30 | #include <linux/clockchips.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/irqreturn.h> | |
34 | #include <linux/sched_clock.h> | |
35 | #include <linux/of.h> | |
36 | #include <linux/of_address.h> | |
37 | #include <linux/of_irq.h> | |
38 | ||
39 | enum { | |
40 | TIMER_A, | |
41 | TIMER_B, | |
42 | TIMER_C, | |
43 | TIMER_D, | |
44 | TIMER_E, | |
45 | TIMER_F, | |
46 | TIMER_G, | |
47 | TIMER_H, | |
48 | }; | |
49 | ||
50 | #define CONTROL(t) ((t)*8) | |
51 | #define COUNT(t) ((t)*8 + 4) | |
52 | ||
53 | #define CONTROL_DISABLE 0 | |
54 | #define CONTROL_ENABLE BIT(0) | |
55 | #define CONTROL_MODE(m) ((m) << 4) | |
56 | #define CONTROL_MODE_ONESHOT CONTROL_MODE(1) | |
57 | #define CONTROL_MODE_PERIODIC CONTROL_MODE(2) | |
58 | ||
59 | struct digicolor_timer { | |
60 | struct clock_event_device ce; | |
61 | void __iomem *base; | |
62 | u32 ticks_per_jiffy; | |
63 | int timer_id; /* one of TIMER_* */ | |
64 | }; | |
65 | ||
48419b1b | 66 | static struct digicolor_timer *dc_timer(struct clock_event_device *ce) |
9b8bb773 BS |
67 | { |
68 | return container_of(ce, struct digicolor_timer, ce); | |
69 | } | |
70 | ||
71 | static inline void dc_timer_disable(struct clock_event_device *ce) | |
72 | { | |
73 | struct digicolor_timer *dt = dc_timer(ce); | |
74 | writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); | |
75 | } | |
76 | ||
77 | static inline void dc_timer_enable(struct clock_event_device *ce, u32 mode) | |
78 | { | |
79 | struct digicolor_timer *dt = dc_timer(ce); | |
80 | writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); | |
81 | } | |
82 | ||
83 | static inline void dc_timer_set_count(struct clock_event_device *ce, | |
84 | unsigned long count) | |
85 | { | |
86 | struct digicolor_timer *dt = dc_timer(ce); | |
87 | writel(count, dt->base + COUNT(dt->timer_id)); | |
88 | } | |
89 | ||
e0d1ca33 VK |
90 | static int digicolor_clkevt_shutdown(struct clock_event_device *ce) |
91 | { | |
92 | dc_timer_disable(ce); | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int digicolor_clkevt_set_oneshot(struct clock_event_device *ce) | |
97 | { | |
98 | dc_timer_disable(ce); | |
99 | dc_timer_enable(ce, CONTROL_MODE_ONESHOT); | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static int digicolor_clkevt_set_periodic(struct clock_event_device *ce) | |
9b8bb773 BS |
104 | { |
105 | struct digicolor_timer *dt = dc_timer(ce); | |
106 | ||
e0d1ca33 VK |
107 | dc_timer_disable(ce); |
108 | dc_timer_set_count(ce, dt->ticks_per_jiffy); | |
109 | dc_timer_enable(ce, CONTROL_MODE_PERIODIC); | |
110 | return 0; | |
9b8bb773 BS |
111 | } |
112 | ||
113 | static int digicolor_clkevt_next_event(unsigned long evt, | |
114 | struct clock_event_device *ce) | |
115 | { | |
116 | dc_timer_disable(ce); | |
117 | dc_timer_set_count(ce, evt); | |
118 | dc_timer_enable(ce, CONTROL_MODE_ONESHOT); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | static struct digicolor_timer dc_timer_dev = { | |
124 | .ce = { | |
125 | .name = "digicolor_tick", | |
126 | .rating = 340, | |
127 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
e0d1ca33 VK |
128 | .set_state_shutdown = digicolor_clkevt_shutdown, |
129 | .set_state_periodic = digicolor_clkevt_set_periodic, | |
130 | .set_state_oneshot = digicolor_clkevt_set_oneshot, | |
131 | .tick_resume = digicolor_clkevt_shutdown, | |
9b8bb773 BS |
132 | .set_next_event = digicolor_clkevt_next_event, |
133 | }, | |
134 | .timer_id = TIMER_C, | |
135 | }; | |
136 | ||
137 | static irqreturn_t digicolor_timer_interrupt(int irq, void *dev_id) | |
138 | { | |
139 | struct clock_event_device *evt = dev_id; | |
140 | ||
141 | evt->event_handler(evt); | |
142 | ||
143 | return IRQ_HANDLED; | |
144 | } | |
145 | ||
76b1ba7f | 146 | static u64 notrace digicolor_timer_sched_read(void) |
9b8bb773 BS |
147 | { |
148 | return ~readl(dc_timer_dev.base + COUNT(TIMER_B)); | |
149 | } | |
150 | ||
c77b9d44 | 151 | static int __init digicolor_timer_init(struct device_node *node) |
9b8bb773 BS |
152 | { |
153 | unsigned long rate; | |
154 | struct clk *clk; | |
155 | int ret, irq; | |
156 | ||
157 | /* | |
158 | * timer registers are shared with the watchdog timer; | |
159 | * don't map exclusively | |
160 | */ | |
161 | dc_timer_dev.base = of_iomap(node, 0); | |
162 | if (!dc_timer_dev.base) { | |
163 | pr_err("Can't map registers"); | |
c77b9d44 | 164 | return -ENXIO; |
9b8bb773 BS |
165 | } |
166 | ||
167 | irq = irq_of_parse_and_map(node, dc_timer_dev.timer_id); | |
168 | if (irq <= 0) { | |
169 | pr_err("Can't parse IRQ"); | |
c77b9d44 | 170 | return -EINVAL; |
9b8bb773 BS |
171 | } |
172 | ||
173 | clk = of_clk_get(node, 0); | |
174 | if (IS_ERR(clk)) { | |
175 | pr_err("Can't get timer clock"); | |
c77b9d44 | 176 | return PTR_ERR(clk); |
9b8bb773 BS |
177 | } |
178 | clk_prepare_enable(clk); | |
179 | rate = clk_get_rate(clk); | |
180 | dc_timer_dev.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); | |
181 | ||
182 | writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); | |
183 | writel(UINT_MAX, dc_timer_dev.base + COUNT(TIMER_B)); | |
184 | writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); | |
185 | ||
186 | sched_clock_register(digicolor_timer_sched_read, 32, rate); | |
187 | clocksource_mmio_init(dc_timer_dev.base + COUNT(TIMER_B), node->name, | |
188 | rate, 340, 32, clocksource_mmio_readl_down); | |
189 | ||
190 | ret = request_irq(irq, digicolor_timer_interrupt, | |
191 | IRQF_TIMER | IRQF_IRQPOLL, "digicolor_timerC", | |
192 | &dc_timer_dev.ce); | |
c77b9d44 | 193 | if (ret) { |
9b8bb773 | 194 | pr_warn("request of timer irq %d failed (%d)\n", irq, ret); |
c77b9d44 DL |
195 | return ret; |
196 | } | |
9b8bb773 BS |
197 | |
198 | dc_timer_dev.ce.cpumask = cpu_possible_mask; | |
199 | dc_timer_dev.ce.irq = irq; | |
200 | ||
201 | clockevents_config_and_register(&dc_timer_dev.ce, rate, 0, 0xffffffff); | |
c77b9d44 DL |
202 | |
203 | return 0; | |
9b8bb773 | 204 | } |
177cf6e5 | 205 | CLOCKSOURCE_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer", |
9b8bb773 | 206 | digicolor_timer_init); |