[mirror_ubuntu-bionic-kernel.git] / drivers / clocksource / timer-fttmr010.c

/*
 * Faraday Technology FTTMR010 timer driver
 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
 *
 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
 * Copyright (C) 2001-2006 Storlink, Corp.
 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 */
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>
#include <linux/clk.h>
#include <linux/slab.h>

/*
 * Register definitions for the timers
 */
#define TIMER1_COUNT		(0x00)
#define TIMER1_LOAD		(0x04)
#define TIMER1_MATCH1		(0x08)
#define TIMER1_MATCH2		(0x0c)
#define TIMER2_COUNT		(0x10)
#define TIMER2_LOAD		(0x14)
#define TIMER2_MATCH1		(0x18)
#define TIMER2_MATCH2		(0x1c)
#define TIMER3_COUNT		(0x20)
#define TIMER3_LOAD		(0x24)
#define TIMER3_MATCH1		(0x28)
#define TIMER3_MATCH2		(0x2c)
#define TIMER_CR		(0x30)
#define TIMER_INTR_STATE	(0x34)
#define TIMER_INTR_MASK		(0x38)

#define TIMER_1_CR_ENABLE	(1 << 0)
#define TIMER_1_CR_CLOCK	(1 << 1)
#define TIMER_1_CR_INT		(1 << 2)
#define TIMER_2_CR_ENABLE	(1 << 3)
#define TIMER_2_CR_CLOCK	(1 << 4)
#define TIMER_2_CR_INT		(1 << 5)
#define TIMER_3_CR_ENABLE	(1 << 6)
#define TIMER_3_CR_CLOCK	(1 << 7)
#define TIMER_3_CR_INT		(1 << 8)
#define TIMER_1_CR_UPDOWN	(1 << 9)
#define TIMER_2_CR_UPDOWN	(1 << 10)
#define TIMER_3_CR_UPDOWN	(1 << 11)
#define TIMER_DEFAULT_FLAGS	(TIMER_1_CR_UPDOWN | \
				 TIMER_3_CR_ENABLE | \
				 TIMER_3_CR_UPDOWN)

#define TIMER_1_INT_MATCH1	(1 << 0)
#define TIMER_1_INT_MATCH2	(1 << 1)
#define TIMER_1_INT_OVERFLOW	(1 << 2)
#define TIMER_2_INT_MATCH1	(1 << 3)
#define TIMER_2_INT_MATCH2	(1 << 4)
#define TIMER_2_INT_OVERFLOW	(1 << 5)
#define TIMER_3_INT_MATCH1	(1 << 6)
#define TIMER_3_INT_MATCH2	(1 << 7)
#define TIMER_3_INT_OVERFLOW	(1 << 8)
#define TIMER_INT_ALL_MASK	0x1ff

struct fttmr010 {
	void __iomem *base;
	unsigned int tick_rate;
	struct clock_event_device clkevt;
};

/* A local singleton used by sched_clock, which is stateless */
static struct fttmr010 *local_fttmr;

static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
{
	return container_of(evt, struct fttmr010, clkevt);
}

static u64 notrace fttmr010_read_sched_clock(void)
{
	return readl(local_fttmr->base + TIMER3_COUNT);
}

static int fttmr010_timer_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Setup the match register */
	cr = readl(fttmr010->base + TIMER1_COUNT);
	writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	if (readl(fttmr010->base + TIMER1_COUNT) - cr > cycles)
		return -ETIME;

	return 0;
}

static int fttmr010_timer_shutdown(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop timer and interrupt. */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 cr;

	/* Stop timer and interrupt. */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
	writel(cr, fttmr010->base + TIMER_CR);

	/* Setup counter start from 0 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	writel(0, fttmr010->base + TIMER1_LOAD);

	/* Enable interrupt */
	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
	cr |= TIMER_1_INT_MATCH1;
	writel(cr, fttmr010->base + TIMER_INTR_MASK);

	/* Start the timer */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= TIMER_1_CR_ENABLE;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
{
	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
	u32 cr;

	/* Stop timer and interrupt */
	cr = readl(fttmr010->base + TIMER_CR);
	cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
	writel(cr, fttmr010->base + TIMER_CR);

	/* Setup timer to fire at 1/HT intervals. */
	cr = 0xffffffff - (period - 1);
	writel(cr, fttmr010->base + TIMER1_COUNT);
	writel(cr, fttmr010->base + TIMER1_LOAD);

	/* enable interrupt on overflow */
	cr = readl(fttmr010->base + TIMER_INTR_MASK);
	cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
	cr |= TIMER_1_INT_OVERFLOW;
	writel(cr, fttmr010->base + TIMER_INTR_MASK);

	/* Start the timer */
	cr = readl(fttmr010->base + TIMER_CR);
	cr |= TIMER_1_CR_ENABLE;
	cr |= TIMER_1_CR_INT;
	writel(cr, fttmr010->base + TIMER_CR);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int __init fttmr010_timer_init(struct device_node *np)
{
	struct fttmr010 *fttmr010;
	int irq;
	struct clk *clk;
	int ret;

	/*
	 * These implementations require a clock reference.
	 * FIXME: we currently only support clocking using PCLK
	 * and using EXTCLK is not supported in the driver.
	 */
	clk = of_clk_get_by_name(np, "PCLK");
	if (IS_ERR(clk)) {
		pr_err("could not get PCLK\n");
		return PTR_ERR(clk);
	}
	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("failed to enable PCLK\n");
		return ret;
	}

	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	if (!fttmr010) {
		ret = -ENOMEM;
		goto out_disable_clock;
	}
	fttmr010->tick_rate = clk_get_rate(clk);

	fttmr010->base = of_iomap(np, 0);
	if (!fttmr010->base) {
		pr_err("Can't remap registers");
		ret = -ENXIO;
		goto out_free;
	}
	/* IRQ for timer 1 */
	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0) {
		pr_err("Can't parse IRQ");
		ret = -EINVAL;
		goto out_unmap;
	}

	/*
	 * Reset the interrupt mask and status
	 */
	writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
	writel(0, fttmr010->base + TIMER_INTR_STATE);
	writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR);

	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled.)
	 */
	local_fttmr = fttmr010;
	writel(0, fttmr010->base + TIMER3_COUNT);
	writel(0, fttmr010->base + TIMER3_LOAD);
	writel(0, fttmr010->base + TIMER3_MATCH1);
	writel(0, fttmr010->base + TIMER3_MATCH2);
	clocksource_mmio_init(fttmr010->base + TIMER3_COUNT,
			      "FTTMR010-TIMER3",
			      fttmr010->tick_rate,
			      300, 32, clocksource_mmio_readl_up);
	sched_clock_register(fttmr010_read_sched_clock, 32,
			     fttmr010->tick_rate);

	/*
	 * Setup clockevent timer (interrupt-driven) on timer 1.
	 */
	writel(0, fttmr010->base + TIMER1_COUNT);
	writel(0, fttmr010->base + TIMER1_LOAD);
	writel(0, fttmr010->base + TIMER1_MATCH1);
	writel(0, fttmr010->base + TIMER1_MATCH2);
	ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
			  "FTTMR010-TIMER1", &fttmr010->clkevt);
	if (ret) {
		pr_err("FTTMR010-TIMER1 no IRQ\n");
		goto out_unmap;
	}

	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	/* Reasonably fast and accurate clock event */
	fttmr010->clkevt.rating = 300;
	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
		CLOCK_EVT_FEAT_ONESHOT;
	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
	fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
	fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
	fttmr010->clkevt.cpumask = cpumask_of(0);
	fttmr010->clkevt.irq = irq;
	clockevents_config_and_register(&fttmr010->clkevt,
					fttmr010->tick_rate,
					1, 0xffffffff);

	return 0;

out_unmap:
	iounmap(fttmr010->base);
out_free:
	kfree(fttmr010);
out_disable_clock:
	clk_disable_unprepare(clk);

	return ret;
}
CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
Commit	Line	Data
4750535b	1	/*
f5bf0ee4	2	* Faraday Technology FTTMR010 timer driver
4750535b LW	3	* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
	4	*
	5	* Based on a rewrite of arch/arm/mach-gemini/timer.c:
	6	* Copyright (C) 2001-2006 Storlink, Corp.
	7	* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	8	*/
	9	#include <linux/interrupt.h>
	10	#include <linux/io.h>
	11	#include <linux/of.h>
	12	#include <linux/of_address.h>
	13	#include <linux/of_irq.h>
4750535b LW	14	#include <linux/clockchips.h>
	15	#include <linux/clocksource.h>
	16	#include <linux/sched_clock.h>
28e71e2f	17	#include <linux/clk.h>
e7bad212	18	#include <linux/slab.h>
4750535b LW	19
	20	/*
	21	* Register definitions for the timers
	22	*/
	23	#define TIMER1_COUNT (0x00)
	24	#define TIMER1_LOAD (0x04)
	25	#define TIMER1_MATCH1 (0x08)
	26	#define TIMER1_MATCH2 (0x0c)
	27	#define TIMER2_COUNT (0x10)
	28	#define TIMER2_LOAD (0x14)
	29	#define TIMER2_MATCH1 (0x18)
	30	#define TIMER2_MATCH2 (0x1c)
	31	#define TIMER3_COUNT (0x20)
	32	#define TIMER3_LOAD (0x24)
	33	#define TIMER3_MATCH1 (0x28)
	34	#define TIMER3_MATCH2 (0x2c)
	35	#define TIMER_CR (0x30)
	36	#define TIMER_INTR_STATE (0x34)
	37	#define TIMER_INTR_MASK (0x38)
	38
	39	#define TIMER_1_CR_ENABLE (1 << 0)
	40	#define TIMER_1_CR_CLOCK (1 << 1)
	41	#define TIMER_1_CR_INT (1 << 2)
	42	#define TIMER_2_CR_ENABLE (1 << 3)
	43	#define TIMER_2_CR_CLOCK (1 << 4)
	44	#define TIMER_2_CR_INT (1 << 5)
	45	#define TIMER_3_CR_ENABLE (1 << 6)
	46	#define TIMER_3_CR_CLOCK (1 << 7)
	47	#define TIMER_3_CR_INT (1 << 8)
	48	#define TIMER_1_CR_UPDOWN (1 << 9)
	49	#define TIMER_2_CR_UPDOWN (1 << 10)
	50	#define TIMER_3_CR_UPDOWN (1 << 11)
	51	#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN \| \
	52	TIMER_3_CR_ENABLE \| \
	53	TIMER_3_CR_UPDOWN)
	54
	55	#define TIMER_1_INT_MATCH1 (1 << 0)
	56	#define TIMER_1_INT_MATCH2 (1 << 1)
	57	#define TIMER_1_INT_OVERFLOW (1 << 2)
	58	#define TIMER_2_INT_MATCH1 (1 << 3)
	59	#define TIMER_2_INT_MATCH2 (1 << 4)
	60	#define TIMER_2_INT_OVERFLOW (1 << 5)
	61	#define TIMER_3_INT_MATCH1 (1 << 6)
	62	#define TIMER_3_INT_MATCH2 (1 << 7)
	63	#define TIMER_3_INT_OVERFLOW (1 << 8)
	64	#define TIMER_INT_ALL_MASK 0x1ff
	65
e7bad212 LW	66	struct fttmr010 {
	67	void __iomem *base;
	68	unsigned int tick_rate;
	69	struct clock_event_device clkevt;
	70	};
	71
	72	/* A local singleton used by sched_clock, which is stateless */
	73	static struct fttmr010 *local_fttmr;
	74
	75	static inline struct fttmr010 to_fttmr010(struct clock_event_device evt)
	76	{
	77	return container_of(evt, struct fttmr010, clkevt);
	78	}
4750535b	79
f5bf0ee4	80	static u64 notrace fttmr010_read_sched_clock(void)
4750535b	81	{
e7bad212	82	return readl(local_fttmr->base + TIMER3_COUNT);
4750535b LW	83	}
4750535b LW	84
f5bf0ee4	85	static int fttmr010_timer_set_next_event(unsigned long cycles,
4750535b LW	86	struct clock_event_device *evt)
4750535b LW	87	{
e7bad212	88	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	89	u32 cr;
	90
	91	/* Setup the match register */
e7bad212 LW	92	cr = readl(fttmr010->base + TIMER1_COUNT);
	93	writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
	94	if (readl(fttmr010->base + TIMER1_COUNT) - cr > cycles)
4750535b LW	95	return -ETIME;
	96
	97	return 0;
	98	}
	99
f5bf0ee4	100	static int fttmr010_timer_shutdown(struct clock_event_device *evt)
4750535b	101	{
e7bad212 LW	102	struct fttmr010 *fttmr010 = to_fttmr010(evt);
	103	u32 cr;
	104
	105	/* Stop timer and interrupt. */
	106	cr = readl(fttmr010->base + TIMER_CR);
	107	cr &= ~(TIMER_1_CR_ENABLE \| TIMER_1_CR_INT);
	108	writel(cr, fttmr010->base + TIMER_CR);
	109
	110	return 0;
	111	}
	112
	113	static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
	114	{
	115	struct fttmr010 *fttmr010 = to_fttmr010(evt);
4750535b LW	116	u32 cr;
4750535b LW	117
4750535b	118	/* Stop timer and interrupt. */
e7bad212	119	cr = readl(fttmr010->base + TIMER_CR);
4750535b	120	cr &= ~(TIMER_1_CR_ENABLE \| TIMER_1_CR_INT);
e7bad212	121	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	122
4750535b LW	123	/* Setup counter start from 0 */
e7bad212 LW	124	writel(0, fttmr010->base + TIMER1_COUNT);
e7bad212 LW	125	writel(0, fttmr010->base + TIMER1_LOAD);
4750535b	126
e7bad212 LW	127	/* Enable interrupt */
e7bad212 LW	128	cr = readl(fttmr010->base + TIMER_INTR_MASK);
4750535b LW	129	cr &= ~(TIMER_1_INT_OVERFLOW \| TIMER_1_INT_MATCH2);
4750535b LW	130	cr \|= TIMER_1_INT_MATCH1;
e7bad212	131	writel(cr, fttmr010->base + TIMER_INTR_MASK);
4750535b	132
e7bad212 LW	133	/* Start the timer */
e7bad212 LW	134	cr = readl(fttmr010->base + TIMER_CR);
4750535b	135	cr \|= TIMER_1_CR_ENABLE;
e7bad212	136	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	137
	138	return 0;
	139	}
	140
f5bf0ee4	141	static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
4750535b	142	{
e7bad212 LW	143	struct fttmr010 *fttmr010 = to_fttmr010(evt);
e7bad212 LW	144	u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
4750535b LW	145	u32 cr;
	146
	147	/* Stop timer and interrupt */
e7bad212	148	cr = readl(fttmr010->base + TIMER_CR);
4750535b	149	cr &= ~(TIMER_1_CR_ENABLE \| TIMER_1_CR_INT);
e7bad212	150	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	151
	152	/* Setup timer to fire at 1/HT intervals. */
	153	cr = 0xffffffff - (period - 1);
e7bad212 LW	154	writel(cr, fttmr010->base + TIMER1_COUNT);
e7bad212 LW	155	writel(cr, fttmr010->base + TIMER1_LOAD);
4750535b LW	156
4750535b LW	157	/* enable interrupt on overflow */
e7bad212	158	cr = readl(fttmr010->base + TIMER_INTR_MASK);
4750535b LW	159	cr &= ~(TIMER_1_INT_MATCH1 \| TIMER_1_INT_MATCH2);
4750535b LW	160	cr \|= TIMER_1_INT_OVERFLOW;
e7bad212	161	writel(cr, fttmr010->base + TIMER_INTR_MASK);
4750535b LW	162
4750535b LW	163	/* Start the timer */
e7bad212	164	cr = readl(fttmr010->base + TIMER_CR);
4750535b LW	165	cr \|= TIMER_1_CR_ENABLE;
4750535b LW	166	cr \|= TIMER_1_CR_INT;
e7bad212	167	writel(cr, fttmr010->base + TIMER_CR);
4750535b LW	168
	169	return 0;
	170	}
	171
4750535b LW	172	/*
	173	* IRQ handler for the timer
	174	*/
f5bf0ee4	175	static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
4750535b	176	{
e7bad212	177	struct clock_event_device *evt = dev_id;
4750535b LW	178
	179	evt->event_handler(evt);
	180	return IRQ_HANDLED;
	181	}
	182
dd98442e	183	static int __init fttmr010_timer_init(struct device_node *np)
4750535b	184	{
e7bad212	185	struct fttmr010 *fttmr010;
4750535b	186	int irq;
dd98442e LW	187	struct clk *clk;
	188	int ret;
	189
	190	/*
	191	* These implementations require a clock reference.
	192	* FIXME: we currently only support clocking using PCLK
	193	* and using EXTCLK is not supported in the driver.
	194	*/
	195	clk = of_clk_get_by_name(np, "PCLK");
	196	if (IS_ERR(clk)) {
	197	pr_err("could not get PCLK\n");
	198	return PTR_ERR(clk);
	199	}
	200	ret = clk_prepare_enable(clk);
	201	if (ret) {
	202	pr_err("failed to enable PCLK\n");
	203	return ret;
	204	}
4750535b	205
e7bad212 LW	206	fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
	207	if (!fttmr010) {
	208	ret = -ENOMEM;
	209	goto out_disable_clock;
	210	}
	211	fttmr010->tick_rate = clk_get_rate(clk);
	212
	213	fttmr010->base = of_iomap(np, 0);
	214	if (!fttmr010->base) {
4750535b	215	pr_err("Can't remap registers");
e7bad212 LW	216	ret = -ENXIO;
e7bad212 LW	217	goto out_free;
4750535b LW	218	}
	219	/* IRQ for timer 1 */
	220	irq = irq_of_parse_and_map(np, 0);
	221	if (irq <= 0) {
	222	pr_err("Can't parse IRQ");
e7bad212 LW	223	ret = -EINVAL;
e7bad212 LW	224	goto out_unmap;
4750535b LW	225	}
4750535b LW	226
4750535b LW	227	/*
	228	* Reset the interrupt mask and status
	229	*/
e7bad212 LW	230	writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
	231	writel(0, fttmr010->base + TIMER_INTR_STATE);
	232	writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR);
4750535b LW	233
	234	/*
	235	* Setup free-running clocksource timer (interrupts
	236	* disabled.)
	237	*/
e7bad212 LW	238	local_fttmr = fttmr010;
	239	writel(0, fttmr010->base + TIMER3_COUNT);
	240	writel(0, fttmr010->base + TIMER3_LOAD);
	241	writel(0, fttmr010->base + TIMER3_MATCH1);
	242	writel(0, fttmr010->base + TIMER3_MATCH2);
	243	clocksource_mmio_init(fttmr010->base + TIMER3_COUNT,
	244	"FTTMR010-TIMER3",
	245	fttmr010->tick_rate,
4750535b	246	300, 32, clocksource_mmio_readl_up);
e7bad212 LW	247	sched_clock_register(fttmr010_read_sched_clock, 32,
e7bad212 LW	248	fttmr010->tick_rate);
4750535b LW	249
4750535b LW	250	/*
e7bad212	251	* Setup clockevent timer (interrupt-driven) on timer 1.
4750535b	252	*/
e7bad212 LW	253	writel(0, fttmr010->base + TIMER1_COUNT);
	254	writel(0, fttmr010->base + TIMER1_LOAD);
	255	writel(0, fttmr010->base + TIMER1_MATCH1);
	256	writel(0, fttmr010->base + TIMER1_MATCH2);
	257	ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
	258	"FTTMR010-TIMER1", &fttmr010->clkevt);
	259	if (ret) {
	260	pr_err("FTTMR010-TIMER1 no IRQ\n");
	261	goto out_unmap;
	262	}
	263
	264	fttmr010->clkevt.name = "FTTMR010-TIMER1";
	265	/* Reasonably fast and accurate clock event */
	266	fttmr010->clkevt.rating = 300;
	267	fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC \|
	268	CLOCK_EVT_FEAT_ONESHOT;
	269	fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
	270	fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
	271	fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
	272	fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
	273	fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
	274	fttmr010->clkevt.cpumask = cpumask_of(0);
	275	fttmr010->clkevt.irq = irq;
	276	clockevents_config_and_register(&fttmr010->clkevt,
	277	fttmr010->tick_rate,
4750535b LW	278	1, 0xffffffff);
	279
	280	return 0;
e7bad212 LW	281
	282	out_unmap:
	283	iounmap(fttmr010->base);
	284	out_free:
	285	kfree(fttmr010);
	286	out_disable_clock:
	287	clk_disable_unprepare(clk);
	288
	289	return ret;
4750535b	290	}
dd98442e LW	291	CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
dd98442e LW	292	CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);