[mirror_ubuntu-jammy-kernel.git] / drivers / clocksource / timer-integrator-ap.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Integrator/AP timer driver
 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
 * Copyright (c) 2014, Linaro Limited
 */

#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/sched_clock.h>

#include "timer-sp.h"

static void __iomem * sched_clk_base;

static u64 notrace integrator_read_sched_clock(void)
{
	return -readl(sched_clk_base + TIMER_VALUE);
}

static int __init integrator_clocksource_init(unsigned long inrate,
					      void __iomem *base)
{
	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
	unsigned long rate = inrate;
	int ret;

	if (rate >= 1500000) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}

	writel(0xffff, base + TIMER_LOAD);
	writel(ctrl, base + TIMER_CTRL);

	ret = clocksource_mmio_init(base + TIMER_VALUE, "timer2",
				    rate, 200, 16, clocksource_mmio_readl_down);
	if (ret)
		return ret;

	sched_clk_base = base;
	sched_clock_register(integrator_read_sched_clock, 16, rate);

	return 0;
}

static unsigned long timer_reload;
static void __iomem * clkevt_base;

/*
 * IRQ handler for the timer
 */
static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int clkevt_shutdown(struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int clkevt_set_oneshot(struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) &
		   ~(TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC);

	/* Leave the timer disabled, .set_next_event will enable it */
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int clkevt_set_periodic(struct clock_event_device *evt)
{
	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;

	/* Disable timer */
	writel(ctrl, clkevt_base + TIMER_CTRL);

	/* Enable the timer and start the periodic tick */
	writel(timer_reload, clkevt_base + TIMER_LOAD);
	ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device integrator_clockevent = {
	.name			= "timer1",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= clkevt_shutdown,
	.set_state_periodic	= clkevt_set_periodic,
	.set_state_oneshot	= clkevt_set_oneshot,
	.tick_resume		= clkevt_shutdown,
	.set_next_event		= clkevt_set_next_event,
	.rating			= 300,
};

static int integrator_clockevent_init(unsigned long inrate,
				      void __iomem *base, int irq)
{
	unsigned long rate = inrate;
	unsigned int ctrl = 0;
	int ret;

	clkevt_base = base;
	/* Calculate and program a divisor */
	if (rate > 0x100000 * HZ) {
		rate /= 256;
		ctrl |= TIMER_CTRL_DIV256;
	} else if (rate > 0x10000 * HZ) {
		rate /= 16;
		ctrl |= TIMER_CTRL_DIV16;
	}
	timer_reload = rate / HZ;
	writel(ctrl, clkevt_base + TIMER_CTRL);

	ret = request_irq(irq, integrator_timer_interrupt,
			  IRQF_TIMER | IRQF_IRQPOLL, "timer",
			  &integrator_clockevent);
	if (ret)
		return ret;

	clockevents_config_and_register(&integrator_clockevent,
					rate,
					1,
					0xffffU);
	return 0;
}

static int __init integrator_ap_timer_init_of(struct device_node *node)
{
	const char *path;
	void __iomem *base;
	int err;
	int irq;
	struct clk *clk;
	unsigned long rate;
	struct device_node *alias_node;

	base = of_io_request_and_map(node, 0, "integrator-timer");
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("No clock for %pOFn\n", node);
		return PTR_ERR(clk);
	}
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);
	writel(0, base + TIMER_CTRL);

	err = of_property_read_string(of_aliases,
				"arm,timer-primary", &path);
	if (err) {
		pr_warn("Failed to read property\n");
		return err;
	}

	alias_node = of_find_node_by_path(path);

	/*
	 * The pointer is used as an identifier not as a pointer, we
	 * can drop the refcount on the of__node immediately after
	 * getting it.
	 */
	of_node_put(alias_node);

	if (node == alias_node)
		/* The primary timer lacks IRQ, use as clocksource */
		return integrator_clocksource_init(rate, base);

	err = of_property_read_string(of_aliases,
				"arm,timer-secondary", &path);
	if (err) {
		pr_warn("Failed to read property\n");
		return err;
	}

	alias_node = of_find_node_by_path(path);

	of_node_put(alias_node);

	if (node == alias_node) {
		/* The secondary timer will drive the clock event */
		irq = irq_of_parse_and_map(node, 0);
		return integrator_clockevent_init(rate, base, irq);
	}

	pr_info("Timer @%p unused\n", base);
	clk_disable_unprepare(clk);

	return 0;
}

TIMER_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
		       integrator_ap_timer_init_of);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
beb5818b LW	2	/*
	3	* Integrator/AP timer driver
	4	* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
	5	* Copyright (c) 2014, Linaro Limited
beb5818b LW	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/clocksource.h>
	10	#include <linux/of_irq.h>
	11	#include <linux/of_address.h>
	12	#include <linux/of_platform.h>
	13	#include <linux/clockchips.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/sched_clock.h>
0b7402dc SH	16
0b7402dc SH	17	#include "timer-sp.h"
beb5818b LW	18
	19	static void __iomem * sched_clk_base;
	20
	21	static u64 notrace integrator_read_sched_clock(void)
	22	{
	23	return -readl(sched_clk_base + TIMER_VALUE);
	24	}
	25
8fce3dc5 AB	26	static int __init integrator_clocksource_init(unsigned long inrate,
8fce3dc5 AB	27	void __iomem *base)
beb5818b LW	28	{
	29	u32 ctrl = TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC;
	30	unsigned long rate = inrate;
76804d05	31	int ret;
beb5818b LW	32
	33	if (rate >= 1500000) {
	34	rate /= 16;
	35	ctrl \|= TIMER_CTRL_DIV16;
	36	}
	37
	38	writel(0xffff, base + TIMER_LOAD);
	39	writel(ctrl, base + TIMER_CTRL);
	40
76804d05 DL	41	ret = clocksource_mmio_init(base + TIMER_VALUE, "timer2",
	42	rate, 200, 16, clocksource_mmio_readl_down);
	43	if (ret)
	44	return ret;
beb5818b LW	45
	46	sched_clk_base = base;
	47	sched_clock_register(integrator_read_sched_clock, 16, rate);
76804d05 DL	48
76804d05 DL	49	return 0;
beb5818b LW	50	}
	51
	52	static unsigned long timer_reload;
	53	static void __iomem * clkevt_base;
	54
	55	/*
	56	* IRQ handler for the timer
	57	*/
	58	static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
	59	{
	60	struct clock_event_device *evt = dev_id;
	61
	62	/* clear the interrupt */
	63	writel(1, clkevt_base + TIMER_INTCLR);
	64
	65	evt->event_handler(evt);
	66
	67	return IRQ_HANDLED;
	68	}
	69
f710bdee	70	static int clkevt_shutdown(struct clock_event_device *evt)
beb5818b LW	71	{
	72	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	73
	74	/* Disable timer */
	75	writel(ctrl, clkevt_base + TIMER_CTRL);
f710bdee VK	76	return 0;
f710bdee VK	77	}
beb5818b	78
f710bdee VK	79	static int clkevt_set_oneshot(struct clock_event_device *evt)
	80	{
	81	u32 ctrl = readl(clkevt_base + TIMER_CTRL) &
	82	~(TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC);
	83
	84	/* Leave the timer disabled, .set_next_event will enable it */
	85	writel(ctrl, clkevt_base + TIMER_CTRL);
	86	return 0;
	87	}
beb5818b	88
f710bdee VK	89	static int clkevt_set_periodic(struct clock_event_device *evt)
	90	{
	91	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
	92
	93	/* Disable timer */
	94	writel(ctrl, clkevt_base + TIMER_CTRL);
	95
	96	/* Enable the timer and start the periodic tick */
	97	writel(timer_reload, clkevt_base + TIMER_LOAD);
	98	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
	99	writel(ctrl, clkevt_base + TIMER_CTRL);
	100	return 0;
beb5818b LW	101	}
	102
	103	static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
	104	{
	105	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	106
	107	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	108	writel(next, clkevt_base + TIMER_LOAD);
	109	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	110
	111	return 0;
	112	}
	113
	114	static struct clock_event_device integrator_clockevent = {
f710bdee VK	115	.name = "timer1",
	116	.features = CLOCK_EVT_FEAT_PERIODIC \|
	117	CLOCK_EVT_FEAT_ONESHOT,
	118	.set_state_shutdown = clkevt_shutdown,
	119	.set_state_periodic = clkevt_set_periodic,
	120	.set_state_oneshot = clkevt_set_oneshot,
	121	.tick_resume = clkevt_shutdown,
	122	.set_next_event = clkevt_set_next_event,
	123	.rating = 300,
beb5818b LW	124	};
beb5818b LW	125
76804d05 DL	126	static int integrator_clockevent_init(unsigned long inrate,
76804d05 DL	127	void __iomem *base, int irq)
beb5818b LW	128	{
	129	unsigned long rate = inrate;
	130	unsigned int ctrl = 0;
76804d05	131	int ret;
beb5818b LW	132
	133	clkevt_base = base;
	134	/* Calculate and program a divisor */
	135	if (rate > 0x100000 * HZ) {
	136	rate /= 256;
	137	ctrl \|= TIMER_CTRL_DIV256;
	138	} else if (rate > 0x10000 * HZ) {
	139	rate /= 16;
	140	ctrl \|= TIMER_CTRL_DIV16;
	141	}
	142	timer_reload = rate / HZ;
	143	writel(ctrl, clkevt_base + TIMER_CTRL);
	144
cc2550b4	145	ret = request_irq(irq, integrator_timer_interrupt,
	146	IRQF_TIMER \| IRQF_IRQPOLL, "timer",
	147	&integrator_clockevent);
76804d05 DL	148	if (ret)
	149	return ret;
	150
beb5818b LW	151	clockevents_config_and_register(&integrator_clockevent,
	152	rate,
	153	1,
	154	0xffffU);
76804d05	155	return 0;
beb5818b LW	156	}
beb5818b LW	157
76804d05	158	static int __init integrator_ap_timer_init_of(struct device_node *node)
beb5818b LW	159	{
	160	const char *path;
	161	void __iomem *base;
	162	int err;
	163	int irq;
	164	struct clk *clk;
	165	unsigned long rate;
5eb73c83	166	struct device_node *alias_node;
beb5818b LW	167
beb5818b LW	168	base = of_io_request_and_map(node, 0, "integrator-timer");
bd580e7e	169	if (IS_ERR(base))
76804d05	170	return PTR_ERR(base);
beb5818b LW	171
	172	clk = of_clk_get(node, 0);
	173	if (IS_ERR(clk)) {
2a4849d2	174	pr_err("No clock for %pOFn\n", node);
76804d05	175	return PTR_ERR(clk);
beb5818b LW	176	}
	177	clk_prepare_enable(clk);
	178	rate = clk_get_rate(clk);
	179	writel(0, base + TIMER_CTRL);
	180
	181	err = of_property_read_string(of_aliases,
	182	"arm,timer-primary", &path);
76804d05	183	if (err) {
ac9ce6d1	184	pr_warn("Failed to read property\n");
76804d05 DL	185	return err;
	186	}
	187
5eb73c83 YL	188	alias_node = of_find_node_by_path(path);
	189
	190	/*
	191	* The pointer is used as an identifier not as a pointer, we
	192	* can drop the refcount on the of__node immediately after
	193	* getting it.
	194	*/
	195	of_node_put(alias_node);
	196
	197	if (node == alias_node)
	198	/* The primary timer lacks IRQ, use as clocksource */
	199	return integrator_clocksource_init(rate, base);
76804d05	200
beb5818b LW	201	err = of_property_read_string(of_aliases,
beb5818b LW	202	"arm,timer-secondary", &path);
76804d05	203	if (err) {
ac9ce6d1	204	pr_warn("Failed to read property\n");
76804d05 DL	205	return err;
	206	}
	207
5eb73c83	208	alias_node = of_find_node_by_path(path);
76804d05	209
5eb73c83	210	of_node_put(alias_node);
beb5818b	211
5eb73c83	212	if (node == alias_node) {
beb5818b LW	213	/* The secondary timer will drive the clock event */
beb5818b LW	214	irq = irq_of_parse_and_map(node, 0);
76804d05	215	return integrator_clockevent_init(rate, base, irq);
beb5818b LW	216	}
	217
	218	pr_info("Timer @%p unused\n", base);
	219	clk_disable_unprepare(clk);
76804d05 DL	220
76804d05 DL	221	return 0;
beb5818b LW	222	}
beb5818b LW	223
17273395	224	TIMER_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
beb5818b	225	integrator_ap_timer_init_of);