[mirror_ubuntu-hirsute-kernel.git] / drivers / clocksource / timer-keystone.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Keystone broadcast clock-event
 *
 * Copyright 2013 Texas Instruments, Inc.
 *
 * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_NAME			"timer-keystone"

/* Timer register offsets */
#define TIM12				0x10
#define TIM34				0x14
#define PRD12				0x18
#define PRD34				0x1c
#define TCR				0x20
#define TGCR				0x24
#define INTCTLSTAT			0x44

/* Timer register bitfields */
#define TCR_ENAMODE_MASK		0xC0
#define TCR_ENAMODE_ONESHOT_MASK	0x40
#define TCR_ENAMODE_PERIODIC_MASK	0x80

#define TGCR_TIM_UNRESET_MASK		0x03
#define INTCTLSTAT_ENINT_MASK		0x01

/**
 * struct keystone_timer: holds timer's data
 * @base: timer memory base address
 * @hz_period: cycles per HZ period
 * @event_dev: event device based on timer
 */
static struct keystone_timer {
	void __iomem *base;
	unsigned long hz_period;
	struct clock_event_device event_dev;
} timer;

static inline u32 keystone_timer_readl(unsigned long rg)
{
	return readl_relaxed(timer.base + rg);
}

static inline void keystone_timer_writel(u32 val, unsigned long rg)
{
	writel_relaxed(val, timer.base + rg);
}

/**
 * keystone_timer_barrier: write memory barrier
 * use explicit barrier to avoid using readl/writel non relaxed function
 * variants, because in our case non relaxed variants hide the true places
 * where barrier is needed.
 */
static inline void keystone_timer_barrier(void)
{
	__iowmb();
}

/**
 * keystone_timer_config: configures timer to work in oneshot/periodic modes.
 * @ mask: mask of the mode to configure
 * @ period: cycles number to configure for
 */
static int keystone_timer_config(u64 period, int mask)
{
	u32 tcr;
	u32 off;

	tcr = keystone_timer_readl(TCR);
	off = tcr & ~(TCR_ENAMODE_MASK);

	/* set enable mode */
	tcr |= mask;

	/* disable timer */
	keystone_timer_writel(off, TCR);
	/* here we have to be sure the timer has been disabled */
	keystone_timer_barrier();

	/* reset counter to zero, set new period */
	keystone_timer_writel(0, TIM12);
	keystone_timer_writel(0, TIM34);
	keystone_timer_writel(period & 0xffffffff, PRD12);
	keystone_timer_writel(period >> 32, PRD34);

	/*
	 * enable timer
	 * here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
	 * have been written.
	 */
	keystone_timer_barrier();
	keystone_timer_writel(tcr, TCR);
	return 0;
}

static void keystone_timer_disable(void)
{
	u32 tcr;

	tcr = keystone_timer_readl(TCR);

	/* disable timer */
	tcr &= ~(TCR_ENAMODE_MASK);
	keystone_timer_writel(tcr, TCR);
}

static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int keystone_set_next_event(unsigned long cycles,
				  struct clock_event_device *evt)
{
	return keystone_timer_config(cycles, TCR_ENAMODE_ONESHOT_MASK);
}

static int keystone_shutdown(struct clock_event_device *evt)
{
	keystone_timer_disable();
	return 0;
}

static int keystone_set_periodic(struct clock_event_device *evt)
{
	keystone_timer_config(timer.hz_period, TCR_ENAMODE_PERIODIC_MASK);
	return 0;
}

static int __init keystone_timer_init(struct device_node *np)
{
	struct clock_event_device *event_dev = &timer.event_dev;
	unsigned long rate;
	struct clk *clk;
	int irq, error;

	irq  = irq_of_parse_and_map(np, 0);
	if (!irq) {
		pr_err("%s: failed to map interrupts\n", __func__);
		return -EINVAL;
	}

	timer.base = of_iomap(np, 0);
	if (!timer.base) {
		pr_err("%s: failed to map registers\n", __func__);
		return -ENXIO;
	}

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("%s: failed to get clock\n", __func__);
		iounmap(timer.base);
		return PTR_ERR(clk);
	}

	error = clk_prepare_enable(clk);
	if (error) {
		pr_err("%s: failed to enable clock\n", __func__);
		goto err;
	}

	rate = clk_get_rate(clk);

	/* disable, use internal clock source */
	keystone_timer_writel(0, TCR);
	/* here we have to be sure the timer has been disabled */
	keystone_timer_barrier();

	/* reset timer as 64-bit, no pre-scaler, plus features are disabled */
	keystone_timer_writel(0, TGCR);

	/* unreset timer */
	keystone_timer_writel(TGCR_TIM_UNRESET_MASK, TGCR);

	/* init counter to zero */
	keystone_timer_writel(0, TIM12);
	keystone_timer_writel(0, TIM34);

	timer.hz_period = DIV_ROUND_UP(rate, HZ);

	/* enable timer interrupts */
	keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT);

	error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER,
			    TIMER_NAME, event_dev);
	if (error) {
		pr_err("%s: failed to setup irq\n", __func__);
		goto err;
	}

	/* setup clockevent */
	event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	event_dev->set_next_event = keystone_set_next_event;
	event_dev->set_state_shutdown = keystone_shutdown;
	event_dev->set_state_periodic = keystone_set_periodic;
	event_dev->set_state_oneshot = keystone_shutdown;
	event_dev->cpumask = cpu_possible_mask;
	event_dev->owner = THIS_MODULE;
	event_dev->name = TIMER_NAME;
	event_dev->irq = irq;

	clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX);

	pr_info("keystone timer clock @%lu Hz\n", rate);
	return 0;
err:
	clk_put(clk);
	iounmap(timer.base);
	return error;
}

TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer",
			   keystone_timer_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
e6b7f580 IK	2	/*
	3	* Keystone broadcast clock-event
	4	*
	5	* Copyright 2013 Texas Instruments, Inc.
	6	*
	7	* Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
e6b7f580 IK	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/clocksource.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/of_address.h>
	15	#include <linux/of_irq.h>
	16
	17	#define TIMER_NAME "timer-keystone"
	18
	19	/* Timer register offsets */
	20	#define TIM12 0x10
	21	#define TIM34 0x14
	22	#define PRD12 0x18
	23	#define PRD34 0x1c
	24	#define TCR 0x20
	25	#define TGCR 0x24
	26	#define INTCTLSTAT 0x44
	27
	28	/* Timer register bitfields */
	29	#define TCR_ENAMODE_MASK 0xC0
	30	#define TCR_ENAMODE_ONESHOT_MASK 0x40
	31	#define TCR_ENAMODE_PERIODIC_MASK 0x80
	32
	33	#define TGCR_TIM_UNRESET_MASK 0x03
	34	#define INTCTLSTAT_ENINT_MASK 0x01
	35
	36	/**
	37	* struct keystone_timer: holds timer's data
	38	* @base: timer memory base address
	39	* @hz_period: cycles per HZ period
	40	* @event_dev: event device based on timer
	41	*/
	42	static struct keystone_timer {
	43	void __iomem *base;
	44	unsigned long hz_period;
	45	struct clock_event_device event_dev;
	46	} timer;
	47
	48	static inline u32 keystone_timer_readl(unsigned long rg)
	49	{
	50	return readl_relaxed(timer.base + rg);
	51	}
	52
	53	static inline void keystone_timer_writel(u32 val, unsigned long rg)
	54	{
	55	writel_relaxed(val, timer.base + rg);
	56	}
	57
	58	/**
	59	* keystone_timer_barrier: write memory barrier
	60	* use explicit barrier to avoid using readl/writel non relaxed function
	61	* variants, because in our case non relaxed variants hide the true places
	62	* where barrier is needed.
	63	*/
	64	static inline void keystone_timer_barrier(void)
	65	{
	66	__iowmb();
	67	}
	68
	69	/**
	70	* keystone_timer_config: configures timer to work in oneshot/periodic modes.
634eb0ec	71	* @ mask: mask of the mode to configure
e6b7f580 IK	72	* @ period: cycles number to configure for
e6b7f580 IK	73	*/
634eb0ec	74	static int keystone_timer_config(u64 period, int mask)
e6b7f580 IK	75	{
	76	u32 tcr;
	77	u32 off;
	78
	79	tcr = keystone_timer_readl(TCR);
	80	off = tcr & ~(TCR_ENAMODE_MASK);
	81
	82	/* set enable mode */
634eb0ec	83	tcr \|= mask;
e6b7f580 IK	84
	85	/* disable timer */
	86	keystone_timer_writel(off, TCR);
	87	/* here we have to be sure the timer has been disabled */
	88	keystone_timer_barrier();
	89
	90	/* reset counter to zero, set new period */
	91	keystone_timer_writel(0, TIM12);
	92	keystone_timer_writel(0, TIM34);
	93	keystone_timer_writel(period & 0xffffffff, PRD12);
	94	keystone_timer_writel(period >> 32, PRD34);
	95
	96	/*
	97	* enable timer
	98	* here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
	99	* have been written.
	100	*/
	101	keystone_timer_barrier();
	102	keystone_timer_writel(tcr, TCR);
	103	return 0;
	104	}
	105
	106	static void keystone_timer_disable(void)
	107	{
	108	u32 tcr;
	109
	110	tcr = keystone_timer_readl(TCR);
	111
	112	/* disable timer */
	113	tcr &= ~(TCR_ENAMODE_MASK);
	114	keystone_timer_writel(tcr, TCR);
	115	}
	116
	117	static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id)
	118	{
	119	struct clock_event_device *evt = dev_id;
	120
	121	evt->event_handler(evt);
	122	return IRQ_HANDLED;
	123	}
	124
	125	static int keystone_set_next_event(unsigned long cycles,
	126	struct clock_event_device *evt)
	127	{
634eb0ec	128	return keystone_timer_config(cycles, TCR_ENAMODE_ONESHOT_MASK);
e6b7f580 IK	129	}
e6b7f580 IK	130
634eb0ec	131	static int keystone_shutdown(struct clock_event_device *evt)
e6b7f580	132	{
634eb0ec VK	133	keystone_timer_disable();
	134	return 0;
	135	}
	136
	137	static int keystone_set_periodic(struct clock_event_device *evt)
	138	{
	139	keystone_timer_config(timer.hz_period, TCR_ENAMODE_PERIODIC_MASK);
	140	return 0;
e6b7f580 IK	141	}
e6b7f580 IK	142
53186505	143	static int __init keystone_timer_init(struct device_node *np)
e6b7f580 IK	144	{
	145	struct clock_event_device *event_dev = &timer.event_dev;
	146	unsigned long rate;
	147	struct clk *clk;
	148	int irq, error;
e6b7f580 IK	149
e6b7f580 IK	150	irq = irq_of_parse_and_map(np, 0);
bdf7344e	151	if (!irq) {
e6b7f580	152	pr_err("%s: failed to map interrupts\n", __func__);
53186505	153	return -EINVAL;
e6b7f580 IK	154	}
	155
	156	timer.base = of_iomap(np, 0);
	157	if (!timer.base) {
	158	pr_err("%s: failed to map registers\n", __func__);
53186505	159	return -ENXIO;
e6b7f580 IK	160	}
	161
	162	clk = of_clk_get(np, 0);
	163	if (IS_ERR(clk)) {
	164	pr_err("%s: failed to get clock\n", __func__);
	165	iounmap(timer.base);
53186505	166	return PTR_ERR(clk);
e6b7f580 IK	167	}
	168
	169	error = clk_prepare_enable(clk);
	170	if (error) {
	171	pr_err("%s: failed to enable clock\n", __func__);
	172	goto err;
	173	}
	174
	175	rate = clk_get_rate(clk);
	176
	177	/* disable, use internal clock source */
	178	keystone_timer_writel(0, TCR);
	179	/* here we have to be sure the timer has been disabled */
	180	keystone_timer_barrier();
	181
	182	/* reset timer as 64-bit, no pre-scaler, plus features are disabled */
e6b7f580 IK	183	keystone_timer_writel(0, TGCR);
	184
	185	/* unreset timer */
e099d01e	186	keystone_timer_writel(TGCR_TIM_UNRESET_MASK, TGCR);
e6b7f580 IK	187
	188	/* init counter to zero */
	189	keystone_timer_writel(0, TIM12);
	190	keystone_timer_writel(0, TIM34);
	191
	192	timer.hz_period = DIV_ROUND_UP(rate, HZ);
	193
	194	/* enable timer interrupts */
	195	keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT);
	196
	197	error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER,
	198	TIMER_NAME, event_dev);
	199	if (error) {
	200	pr_err("%s: failed to setup irq\n", __func__);
	201	goto err;
	202	}
	203
	204	/* setup clockevent */
	205	event_dev->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	206	event_dev->set_next_event = keystone_set_next_event;
634eb0ec VK	207	event_dev->set_state_shutdown = keystone_shutdown;
	208	event_dev->set_state_periodic = keystone_set_periodic;
	209	event_dev->set_state_oneshot = keystone_shutdown;
f8f5fe86	210	event_dev->cpumask = cpu_possible_mask;
e6b7f580 IK	211	event_dev->owner = THIS_MODULE;
	212	event_dev->name = TIMER_NAME;
	213	event_dev->irq = irq;
	214
	215	clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX);
	216
	217	pr_info("keystone timer clock @%lu Hz\n", rate);
53186505	218	return 0;
e6b7f580 IK	219	err:
	220	clk_put(clk);
	221	iounmap(timer.base);
53186505	222	return error;
e6b7f580 IK	223	}
e6b7f580 IK	224
17273395	225	TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer",
53186505	226	keystone_timer_init);