[mirror_ubuntu-jammy-kernel.git] / drivers / clocksource / timer-microchip-pit64b.c

// SPDX-License-Identifier: GPL-2.0
/*
 * 64-bit Periodic Interval Timer driver
 *
 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>

#define MCHP_PIT64B_CR			0x00	/* Control Register */
#define MCHP_PIT64B_CR_START		BIT(0)
#define MCHP_PIT64B_CR_SWRST		BIT(8)

#define MCHP_PIT64B_MR			0x04	/* Mode Register */
#define MCHP_PIT64B_MR_CONT		BIT(0)
#define MCHP_PIT64B_MR_ONE_SHOT		(0)
#define MCHP_PIT64B_MR_SGCLK		BIT(3)
#define MCHP_PIT64B_MR_PRES		GENMASK(11, 8)

#define MCHP_PIT64B_LSB_PR		0x08	/* LSB Period Register */

#define MCHP_PIT64B_MSB_PR		0x0C	/* MSB Period Register */

#define MCHP_PIT64B_IER			0x10	/* Interrupt Enable Register */
#define MCHP_PIT64B_IER_PERIOD		BIT(0)

#define MCHP_PIT64B_ISR			0x1C	/* Interrupt Status Register */

#define MCHP_PIT64B_TLSBR		0x20	/* Timer LSB Register */

#define MCHP_PIT64B_TMSBR		0x24	/* Timer MSB Register */

#define MCHP_PIT64B_PRES_MAX		0x10
#define MCHP_PIT64B_LSBMASK		GENMASK_ULL(31, 0)
#define MCHP_PIT64B_PRES_TO_MODE(p)	(MCHP_PIT64B_MR_PRES & ((p) << 8))
#define MCHP_PIT64B_MODE_TO_PRES(m)	((MCHP_PIT64B_MR_PRES & (m)) >> 8)
#define MCHP_PIT64B_DEF_CS_FREQ		5000000UL	/* 5 MHz */
#define MCHP_PIT64B_DEF_CE_FREQ		32768		/* 32 KHz */

#define MCHP_PIT64B_NAME		"pit64b"

/**
 * struct mchp_pit64b_timer - PIT64B timer data structure
 * @base: base address of PIT64B hardware block
 * @pclk: PIT64B's peripheral clock
 * @gclk: PIT64B's generic clock
 * @mode: precomputed value for mode register
 */
struct mchp_pit64b_timer {
	void __iomem	*base;
	struct clk	*pclk;
	struct clk	*gclk;
	u32		mode;
};

/**
 * mchp_pit64b_clkevt - PIT64B clockevent data structure
 * @timer: PIT64B timer
 * @clkevt: clockevent
 */
struct mchp_pit64b_clkevt {
	struct mchp_pit64b_timer	timer;
	struct clock_event_device	clkevt;
};

#define clkevt_to_mchp_pit64b_timer(x) \
	((struct mchp_pit64b_timer *)container_of(x,\
		struct mchp_pit64b_clkevt, clkevt))

/**
 * mchp_pit64b_clksrc - PIT64B clocksource data structure
 * @timer: PIT64B timer
 * @clksrc: clocksource
 */
struct mchp_pit64b_clksrc {
	struct mchp_pit64b_timer	timer;
	struct clocksource		clksrc;
};

#define clksrc_to_mchp_pit64b_timer(x) \
	((struct mchp_pit64b_timer *)container_of(x,\
		struct mchp_pit64b_clksrc, clksrc))

/* Base address for clocksource timer. */
static void __iomem *mchp_pit64b_cs_base;
/* Default cycles for clockevent timer. */
static u64 mchp_pit64b_ce_cycles;

static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
{
	unsigned long	flags;
	u32		low, high;

	raw_local_irq_save(flags);

	/*
	 * When using a 64 bit period TLSB must be read first, followed by the
	 * read of TMSB. This sequence generates an atomic read of the 64 bit
	 * timer value whatever the lapse of time between the accesses.
	 */
	low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
	high = readl_relaxed(base + MCHP_PIT64B_TMSBR);

	raw_local_irq_restore(flags);

	return (((u64)high << 32) | low);
}

static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
				     u64 cycles, u32 mode, u32 irqs)
{
	u32 low, high;

	low = cycles & MCHP_PIT64B_LSBMASK;
	high = cycles >> 32;

	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
}

static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
{
	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
		clk_disable_unprepare(timer->gclk);
	clk_disable_unprepare(timer->pclk);
}

static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
{
	clk_prepare_enable(timer->pclk);
	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
		clk_prepare_enable(timer->gclk);
}

static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
{
	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);

	mchp_pit64b_suspend(timer);
}

static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
{
	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);

	mchp_pit64b_resume(timer);
	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
}

static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
{
	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
}

static u64 mchp_pit64b_sched_read_clk(void)
{
	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
}

static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);

	return 0;
}

static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
			  MCHP_PIT64B_IER_PERIOD);

	return 0;
}

static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
					     struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
			  MCHP_PIT64B_IER_PERIOD);

	return 0;
}

static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	mchp_pit64b_suspend(timer);
}

static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);

	mchp_pit64b_resume(timer);
}

static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
{
	struct mchp_pit64b_clkevt *irq_data = dev_id;

	/* Need to clear the interrupt. */
	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);

	irq_data->clkevt.event_handler(&irq_data->clkevt);

	return IRQ_HANDLED;
}

static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
					    u32 max_rate)
{
	u32 tmp;

	for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
		tmp = clk_rate / (*pres + 1);
		if (tmp <= max_rate)
			break;
	}

	/* Use the biggest prescaler if we didn't match one. */
	if (*pres == MCHP_PIT64B_PRES_MAX)
		*pres = MCHP_PIT64B_PRES_MAX - 1;
}

/**
 * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at
 *			   runtime; this includes prescaler and SGCLK bit
 *
 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
 * divided by the internal PIT64B's divider.
 *
 * This function, first tries to use GCLK by requesting the desired rate from
 * PMC and then using the internal PIT64B prescaler, if any, to reach the
 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
 * then the function falls back on using PCLK as clock source for PIT64B timer
 * choosing the highest prescaler in case it doesn't locate one to match the
 * requested frequency.
 *
 * Below is presented the PIT64B block in relation with PMC:
 *
 *                                PIT64B
 *  PMC             +------------------------------------+
 * +----+           |   +-----+                          |
 * |    |-->gclk -->|-->|     |    +---------+  +-----+  |
 * |    |           |   | MUX |--->| Divider |->|timer|  |
 * |    |-->pclk -->|-->|     |    +---------+  +-----+  |
 * +----+           |   +-----+                          |
 *                  |      ^                             |
 *                  |     sel                            |
 *                  +------------------------------------+
 *
 * Where:
 *	- gclk rate <= pclk rate/3
 *	- gclk rate could be requested from PMC
 *	- pclk rate is fixed (cannot be requested from PMC)
 */
static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
					unsigned long max_rate)
{
	unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
	long gclk_round = 0;
	u32 pres, best_pres = 0;

	pclk_rate = clk_get_rate(timer->pclk);
	if (!pclk_rate)
		return -EINVAL;

	timer->mode = 0;

	/* Try using GCLK. */
	gclk_round = clk_round_rate(timer->gclk, max_rate);
	if (gclk_round < 0)
		goto pclk;

	if (pclk_rate / gclk_round < 3)
		goto pclk;

	mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
	best_diff = abs(gclk_round / (pres + 1) - max_rate);
	best_pres = pres;

	if (!best_diff) {
		timer->mode |= MCHP_PIT64B_MR_SGCLK;
		clk_set_rate(timer->gclk, gclk_round);
		goto done;
	}

pclk:
	/* Check if requested rate could be obtained using PCLK. */
	mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
	diff = abs(pclk_rate / (pres + 1) - max_rate);

	if (best_diff > diff) {
		/* Use PCLK. */
		best_pres = pres;
	} else {
		/* Use GCLK. */
		timer->mode |= MCHP_PIT64B_MR_SGCLK;
		clk_set_rate(timer->gclk, gclk_round);
	}

done:
	timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);

	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
		timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
		timer->mode & MCHP_PIT64B_MR_SGCLK ?
		gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));

	return 0;
}

static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
					  u32 clk_rate)
{
	struct mchp_pit64b_clksrc *cs;
	int ret;

	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
	if (!cs)
		return -ENOMEM;

	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);

	mchp_pit64b_cs_base = timer->base;

	cs->timer.base = timer->base;
	cs->timer.pclk = timer->pclk;
	cs->timer.gclk = timer->gclk;
	cs->timer.mode = timer->mode;
	cs->clksrc.name = MCHP_PIT64B_NAME;
	cs->clksrc.mask = CLOCKSOURCE_MASK(64);
	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	cs->clksrc.rating = 210;
	cs->clksrc.read = mchp_pit64b_clksrc_read;
	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
	cs->clksrc.resume = mchp_pit64b_clksrc_resume;

	ret = clocksource_register_hz(&cs->clksrc, clk_rate);
	if (ret) {
		pr_debug("clksrc: Failed to register PIT64B clocksource!\n");

		/* Stop timer. */
		writel_relaxed(MCHP_PIT64B_CR_SWRST,
			       timer->base + MCHP_PIT64B_CR);
		kfree(cs);

		return ret;
	}

	sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);

	return 0;
}

static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
					  u32 clk_rate, u32 irq)
{
	struct mchp_pit64b_clkevt *ce;
	int ret;

	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
	if (!ce)
		return -ENOMEM;

	mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);

	ce->timer.base = timer->base;
	ce->timer.pclk = timer->pclk;
	ce->timer.gclk = timer->gclk;
	ce->timer.mode = timer->mode;
	ce->clkevt.name = MCHP_PIT64B_NAME;
	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
	ce->clkevt.rating = 150;
	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
	ce->clkevt.suspend = mchp_pit64b_clkevt_suspend;
	ce->clkevt.resume = mchp_pit64b_clkevt_resume;
	ce->clkevt.cpumask = cpumask_of(0);
	ce->clkevt.irq = irq;

	ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
			  "pit64b_tick", ce);
	if (ret) {
		pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
		kfree(ce);
		return ret;
	}

	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);

	return 0;
}

static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
					    bool clkevt)
{
	u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ;
	struct mchp_pit64b_timer timer;
	unsigned long clk_rate;
	u32 irq = 0;
	int ret;

	/* Parse DT node. */
	timer.pclk = of_clk_get_by_name(node, "pclk");
	if (IS_ERR(timer.pclk))
		return PTR_ERR(timer.pclk);

	timer.gclk = of_clk_get_by_name(node, "gclk");
	if (IS_ERR(timer.gclk))
		return PTR_ERR(timer.gclk);

	timer.base = of_iomap(node, 0);
	if (!timer.base)
		return -ENXIO;

	if (clkevt) {
		irq = irq_of_parse_and_map(node, 0);
		if (!irq) {
			ret = -ENODEV;
			goto io_unmap;
		}
	}

	/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
	ret = mchp_pit64b_init_mode(&timer, freq);
	if (ret)
		goto irq_unmap;

	ret = clk_prepare_enable(timer.pclk);
	if (ret)
		goto irq_unmap;

	if (timer.mode & MCHP_PIT64B_MR_SGCLK) {
		ret = clk_prepare_enable(timer.gclk);
		if (ret)
			goto pclk_unprepare;

		clk_rate = clk_get_rate(timer.gclk);
	} else {
		clk_rate = clk_get_rate(timer.pclk);
	}
	clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);

	if (clkevt)
		ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
	else
		ret = mchp_pit64b_init_clksrc(&timer, clk_rate);

	if (ret)
		goto gclk_unprepare;

	return 0;

gclk_unprepare:
	if (timer.mode & MCHP_PIT64B_MR_SGCLK)
		clk_disable_unprepare(timer.gclk);
pclk_unprepare:
	clk_disable_unprepare(timer.pclk);
irq_unmap:
	irq_dispose_mapping(irq);
io_unmap:
	iounmap(timer.base);

	return ret;
}

static int __init mchp_pit64b_dt_init(struct device_node *node)
{
	static int inits;

	switch (inits++) {
	case 0:
		/* 1st request, register clockevent. */
		return mchp_pit64b_dt_init_timer(node, true);
	case 1:
		/* 2nd request, register clocksource. */
		return mchp_pit64b_dt_init_timer(node, false);
	}

	/* The rest, don't care. */
	return -EINVAL;
}

TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);
Commit	Line	Data
625022a5 CB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* 64-bit Periodic Interval Timer driver
	4	*
	5	* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
	6	*
	7	* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/sched_clock.h>
	16	#include <linux/slab.h>
	17
	18	#define MCHP_PIT64B_CR 0x00 /* Control Register */
	19	#define MCHP_PIT64B_CR_START BIT(0)
	20	#define MCHP_PIT64B_CR_SWRST BIT(8)
	21
	22	#define MCHP_PIT64B_MR 0x04 /* Mode Register */
	23	#define MCHP_PIT64B_MR_CONT BIT(0)
	24	#define MCHP_PIT64B_MR_ONE_SHOT (0)
	25	#define MCHP_PIT64B_MR_SGCLK BIT(3)
	26	#define MCHP_PIT64B_MR_PRES GENMASK(11, 8)
	27
	28	#define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */
	29
	30	#define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */
	31
	32	#define MCHP_PIT64B_IER 0x10 /* Interrupt Enable Register */
	33	#define MCHP_PIT64B_IER_PERIOD BIT(0)
	34
	35	#define MCHP_PIT64B_ISR 0x1C /* Interrupt Status Register */
	36
	37	#define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */
	38
	39	#define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */
	40
	41	#define MCHP_PIT64B_PRES_MAX 0x10
	42	#define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0)
	43	#define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8))
	44	#define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8)
	45	#define MCHP_PIT64B_DEF_CS_FREQ 5000000UL /* 5 MHz */
	46	#define MCHP_PIT64B_DEF_CE_FREQ 32768 /* 32 KHz */
	47
	48	#define MCHP_PIT64B_NAME "pit64b"
	49
	50	/**
	51	* struct mchp_pit64b_timer - PIT64B timer data structure
	52	* @base: base address of PIT64B hardware block
	53	* @pclk: PIT64B's peripheral clock
	54	* @gclk: PIT64B's generic clock
	55	* @mode: precomputed value for mode register
	56	*/
	57	struct mchp_pit64b_timer {
	58	void __iomem *base;
	59	struct clk *pclk;
	60	struct clk *gclk;
	61	u32 mode;
	62	};
	63
	64	/**
65	* mchp_pit64b_clkevt - PIT64B clockevent data structure
66	* @timer: PIT64B timer
67	* @clkevt: clockevent
68	*/
69	struct mchp_pit64b_clkevt {
70	struct mchp_pit64b_timer timer;
71	struct clock_event_device clkevt;
72	};
73
e85c1d21	74	#define clkevt_to_mchp_pit64b_timer(x) \
625022a5 CB	75	((struct mchp_pit64b_timer *)container_of(x,\
	76	struct mchp_pit64b_clkevt, clkevt))
	77
e85c1d21 CB	78	/**
	79	* mchp_pit64b_clksrc - PIT64B clocksource data structure
	80	* @timer: PIT64B timer
	81	* @clksrc: clocksource
	82	*/
	83	struct mchp_pit64b_clksrc {
	84	struct mchp_pit64b_timer timer;
	85	struct clocksource clksrc;
	86	};
	87
	88	#define clksrc_to_mchp_pit64b_timer(x) \
	89	((struct mchp_pit64b_timer *)container_of(x,\
	90	struct mchp_pit64b_clksrc, clksrc))
	91
625022a5 CB	92	/* Base address for clocksource timer. */
	93	static void __iomem *mchp_pit64b_cs_base;
	94	/* Default cycles for clockevent timer. */
	95	static u64 mchp_pit64b_ce_cycles;
	96
	97	static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
	98	{
	99	unsigned long flags;
	100	u32 low, high;
	101
	102	raw_local_irq_save(flags);
	103
	104	/*
	105	* When using a 64 bit period TLSB must be read first, followed by the
	106	* read of TMSB. This sequence generates an atomic read of the 64 bit
	107	* timer value whatever the lapse of time between the accesses.
	108	*/
	109	low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
	110	high = readl_relaxed(base + MCHP_PIT64B_TMSBR);
	111
	112	raw_local_irq_restore(flags);
	113
	114	return (((u64)high << 32) \| low);
	115	}
	116
	117	static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
	118	u64 cycles, u32 mode, u32 irqs)
	119	{
	120	u32 low, high;
	121
	122	low = cycles & MCHP_PIT64B_LSBMASK;
	123	high = cycles >> 32;
	124
	125	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	126	writel_relaxed(mode \| timer->mode, timer->base + MCHP_PIT64B_MR);
	127	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
	128	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
	129	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
	130	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
	131	}
	132
e85c1d21 CB	133	static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
	134	{
	135	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	136	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
	137	clk_disable_unprepare(timer->gclk);
	138	clk_disable_unprepare(timer->pclk);
	139	}
	140
	141	static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
	142	{
	143	clk_prepare_enable(timer->pclk);
	144	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
	145	clk_prepare_enable(timer->gclk);
	146	}
	147
	148	static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
	149	{
	150	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
	151
	152	mchp_pit64b_suspend(timer);
	153	}
	154
	155	static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
	156	{
	157	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
	158
	159	mchp_pit64b_resume(timer);
	160	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
	161	}
	162
625022a5 CB	163	static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
	164	{
	165	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
	166	}
	167
	168	static u64 mchp_pit64b_sched_read_clk(void)
	169	{
	170	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
	171	}
	172
	173	static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
	174	{
e85c1d21	175	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5 CB	176
	177	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	178
	179	return 0;
	180	}
	181
	182	static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
	183	{
e85c1d21	184	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5 CB	185
	186	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
	187	MCHP_PIT64B_IER_PERIOD);
	188
	189	return 0;
	190	}
	191
	192	static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
	193	struct clock_event_device *cedev)
	194	{
e85c1d21	195	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5 CB	196
	197	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
	198	MCHP_PIT64B_IER_PERIOD);
	199
	200	return 0;
	201	}
	202
	203	static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
	204	{
e85c1d21	205	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5	206
e85c1d21	207	mchp_pit64b_suspend(timer);
625022a5 CB	208	}
	209
	210	static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
	211	{
e85c1d21	212	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
625022a5	213
e85c1d21	214	mchp_pit64b_resume(timer);
625022a5 CB	215	}
	216
	217	static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
	218	{
	219	struct mchp_pit64b_clkevt *irq_data = dev_id;
	220
	221	/* Need to clear the interrupt. */
	222	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);
	223
	224	irq_data->clkevt.event_handler(&irq_data->clkevt);
	225
	226	return IRQ_HANDLED;
	227	}
	228
	229	static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
	230	u32 max_rate)
	231	{
	232	u32 tmp;
	233
	234	for (pres = 0; pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
	235	tmp = clk_rate / (*pres + 1);
	236	if (tmp <= max_rate)
	237	break;
	238	}
	239
4bf07f65	240	/* Use the biggest prescaler if we didn't match one. */
625022a5 CB	241	if (*pres == MCHP_PIT64B_PRES_MAX)
	242	*pres = MCHP_PIT64B_PRES_MAX - 1;
	243	}
	244
	245	/**
	246	* mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at
	247	* runtime; this includes prescaler and SGCLK bit
	248	*
	249	* PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
	250	* be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
	251	* could be changed via clock APIs. The chosen clock (pclk or gclk) could be
	252	* divided by the internal PIT64B's divider.
	253	*
	254	* This function, first tries to use GCLK by requesting the desired rate from
	255	* PMC and then using the internal PIT64B prescaler, if any, to reach the
	256	* requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
	257	* then the function falls back on using PCLK as clock source for PIT64B timer
	258	* choosing the highest prescaler in case it doesn't locate one to match the
	259	* requested frequency.
	260	*
	261	* Below is presented the PIT64B block in relation with PMC:
	262	*
	263	* PIT64B
	264	* PMC +------------------------------------+
	265	* +----+ \| +-----+ \|
	266	* \| \|-->gclk -->\|-->\| \| +---------+ +-----+ \|
	267	* \| \| \| \| MUX \|--->\| Divider \|->\|timer\| \|
	268	* \| \|-->pclk -->\|-->\| \| +---------+ +-----+ \|
	269	* +----+ \| +-----+ \|
	270	* \| ^ \|
	271	* \| sel \|
	272	* +------------------------------------+
	273	*
	274	* Where:
	275	* - gclk rate <= pclk rate/3
	276	* - gclk rate could be requested from PMC
	277	* - pclk rate is fixed (cannot be requested from PMC)
	278	*/
	279	static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
	280	unsigned long max_rate)
	281	{
	282	unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
	283	long gclk_round = 0;
	284	u32 pres, best_pres = 0;
	285
	286	pclk_rate = clk_get_rate(timer->pclk);
	287	if (!pclk_rate)
	288	return -EINVAL;
	289
b9c60a74 CB	290	timer->mode = 0;
b9c60a74 CB	291
625022a5 CB	292	/* Try using GCLK. */
	293	gclk_round = clk_round_rate(timer->gclk, max_rate);
	294	if (gclk_round < 0)
	295	goto pclk;
	296
	297	if (pclk_rate / gclk_round < 3)
	298	goto pclk;
	299
	300	mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
	301	best_diff = abs(gclk_round / (pres + 1) - max_rate);
	302	best_pres = pres;
	303
	304	if (!best_diff) {
	305	timer->mode \|= MCHP_PIT64B_MR_SGCLK;
05852445	306	clk_set_rate(timer->gclk, gclk_round);
625022a5 CB	307	goto done;
	308	}
	309
	310	pclk:
	311	/* Check if requested rate could be obtained using PCLK. */
	312	mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
	313	diff = abs(pclk_rate / (pres + 1) - max_rate);
	314
	315	if (best_diff > diff) {
	316	/* Use PCLK. */
	317	best_pres = pres;
	318	} else {
	319	/* Use GCLK. */
	320	timer->mode \|= MCHP_PIT64B_MR_SGCLK;
	321	clk_set_rate(timer->gclk, gclk_round);
	322	}
	323
	324	done:
	325	timer->mode \|= MCHP_PIT64B_PRES_TO_MODE(best_pres);
	326
	327	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
	328	timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
	329	timer->mode & MCHP_PIT64B_MR_SGCLK ?
	330	gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));
	331
	332	return 0;
	333	}
	334
	335	static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
	336	u32 clk_rate)
	337	{
e85c1d21	338	struct mchp_pit64b_clksrc *cs;
625022a5 CB	339	int ret;
625022a5 CB	340
e85c1d21 CB	341	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
	342	if (!cs)
	343	return -ENOMEM;
	344
625022a5 CB	345	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
	346
	347	mchp_pit64b_cs_base = timer->base;
	348
e85c1d21 CB	349	cs->timer.base = timer->base;
	350	cs->timer.pclk = timer->pclk;
	351	cs->timer.gclk = timer->gclk;
	352	cs->timer.mode = timer->mode;
	353	cs->clksrc.name = MCHP_PIT64B_NAME;
	354	cs->clksrc.mask = CLOCKSOURCE_MASK(64);
	355	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	356	cs->clksrc.rating = 210;
	357	cs->clksrc.read = mchp_pit64b_clksrc_read;
	358	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
	359	cs->clksrc.resume = mchp_pit64b_clksrc_resume;
	360
	361	ret = clocksource_register_hz(&cs->clksrc, clk_rate);
625022a5 CB	362	if (ret) {
	363	pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
	364
	365	/* Stop timer. */
	366	writel_relaxed(MCHP_PIT64B_CR_SWRST,
	367	timer->base + MCHP_PIT64B_CR);
e85c1d21	368	kfree(cs);
625022a5 CB	369
	370	return ret;
	371	}
	372
	373	sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);
	374
	375	return 0;
	376	}
	377
	378	static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
	379	u32 clk_rate, u32 irq)
	380	{
	381	struct mchp_pit64b_clkevt *ce;
	382	int ret;
	383
	384	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
	385	if (!ce)
	386	return -ENOMEM;
	387
	388	mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);
	389
	390	ce->timer.base = timer->base;
	391	ce->timer.pclk = timer->pclk;
	392	ce->timer.gclk = timer->gclk;
	393	ce->timer.mode = timer->mode;
	394	ce->clkevt.name = MCHP_PIT64B_NAME;
	395	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC;
	396	ce->clkevt.rating = 150;
	397	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
	398	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
	399	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
	400	ce->clkevt.suspend = mchp_pit64b_clkevt_suspend;
	401	ce->clkevt.resume = mchp_pit64b_clkevt_resume;
	402	ce->clkevt.cpumask = cpumask_of(0);
	403	ce->clkevt.irq = irq;
	404
	405	ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
	406	"pit64b_tick", ce);
	407	if (ret) {
	408	pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
	409	kfree(ce);
	410	return ret;
	411	}
	412
	413	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);
	414
	415	return 0;
	416	}
	417
	418	static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
	419	bool clkevt)
	420	{
	421	u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ;
b9c60a74	422	struct mchp_pit64b_timer timer;
625022a5 CB	423	unsigned long clk_rate;
	424	u32 irq = 0;
	425	int ret;
	426
	427	/* Parse DT node. */
	428	timer.pclk = of_clk_get_by_name(node, "pclk");
	429	if (IS_ERR(timer.pclk))
	430	return PTR_ERR(timer.pclk);
	431
	432	timer.gclk = of_clk_get_by_name(node, "gclk");
	433	if (IS_ERR(timer.gclk))
	434	return PTR_ERR(timer.gclk);
	435
	436	timer.base = of_iomap(node, 0);
	437	if (!timer.base)
	438	return -ENXIO;
	439
	440	if (clkevt) {
	441	irq = irq_of_parse_and_map(node, 0);
	442	if (!irq) {
	443	ret = -ENODEV;
	444	goto io_unmap;
	445	}
	446	}
	447
	448	/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
	449	ret = mchp_pit64b_init_mode(&timer, freq);
	450	if (ret)
	451	goto irq_unmap;
	452
	453	ret = clk_prepare_enable(timer.pclk);
	454	if (ret)
	455	goto irq_unmap;
	456
	457	if (timer.mode & MCHP_PIT64B_MR_SGCLK) {
	458	ret = clk_prepare_enable(timer.gclk);
	459	if (ret)
	460	goto pclk_unprepare;
	461
	462	clk_rate = clk_get_rate(timer.gclk);
	463	} else {
	464	clk_rate = clk_get_rate(timer.pclk);
	465	}
	466	clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);
	467
	468	if (clkevt)
	469	ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
	470	else
	471	ret = mchp_pit64b_init_clksrc(&timer, clk_rate);
	472
	473	if (ret)
	474	goto gclk_unprepare;
	475
	476	return 0;
	477
	478	gclk_unprepare:
	479	if (timer.mode & MCHP_PIT64B_MR_SGCLK)
	480	clk_disable_unprepare(timer.gclk);
	481	pclk_unprepare:
	482	clk_disable_unprepare(timer.pclk);
	483	irq_unmap:
	484	irq_dispose_mapping(irq);
	485	io_unmap:
	486	iounmap(timer.base);
487
488	return ret;
489	}
490
491	static int __init mchp_pit64b_dt_init(struct device_node *node)
492	{
493	static int inits;
494
495	switch (inits++) {
496	case 0:
497	/* 1st request, register clockevent. */
498	return mchp_pit64b_dt_init_timer(node, true);
499	case 1:
500	/* 2nd request, register clocksource. */
501	return mchp_pit64b_dt_init_timer(node, false);
502	}
503
504	/* The rest, don't care. */
505	return -EINVAL;
506	}
507
508	TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);