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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * 64-bit Periodic Interval Timer driver | |
4 | * | |
5 | * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries | |
6 | * | |
7 | * Author: Claudiu Beznea <claudiu.beznea@microchip.com> | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/clockchips.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/of_irq.h> | |
15 | #include <linux/sched_clock.h> | |
16 | #include <linux/slab.h> | |
17 | ||
18 | #define MCHP_PIT64B_CR 0x00 /* Control Register */ | |
19 | #define MCHP_PIT64B_CR_START BIT(0) | |
20 | #define MCHP_PIT64B_CR_SWRST BIT(8) | |
21 | ||
22 | #define MCHP_PIT64B_MR 0x04 /* Mode Register */ | |
23 | #define MCHP_PIT64B_MR_CONT BIT(0) | |
24 | #define MCHP_PIT64B_MR_ONE_SHOT (0) | |
25 | #define MCHP_PIT64B_MR_SGCLK BIT(3) | |
26 | #define MCHP_PIT64B_MR_PRES GENMASK(11, 8) | |
27 | ||
28 | #define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */ | |
29 | ||
30 | #define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */ | |
31 | ||
32 | #define MCHP_PIT64B_IER 0x10 /* Interrupt Enable Register */ | |
33 | #define MCHP_PIT64B_IER_PERIOD BIT(0) | |
34 | ||
35 | #define MCHP_PIT64B_ISR 0x1C /* Interrupt Status Register */ | |
36 | ||
37 | #define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */ | |
38 | ||
39 | #define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */ | |
40 | ||
41 | #define MCHP_PIT64B_PRES_MAX 0x10 | |
42 | #define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0) | |
43 | #define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8)) | |
44 | #define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8) | |
45 | #define MCHP_PIT64B_DEF_CS_FREQ 5000000UL /* 5 MHz */ | |
46 | #define MCHP_PIT64B_DEF_CE_FREQ 32768 /* 32 KHz */ | |
47 | ||
48 | #define MCHP_PIT64B_NAME "pit64b" | |
49 | ||
50 | /** | |
51 | * struct mchp_pit64b_timer - PIT64B timer data structure | |
52 | * @base: base address of PIT64B hardware block | |
53 | * @pclk: PIT64B's peripheral clock | |
54 | * @gclk: PIT64B's generic clock | |
55 | * @mode: precomputed value for mode register | |
56 | */ | |
57 | struct mchp_pit64b_timer { | |
58 | void __iomem *base; | |
59 | struct clk *pclk; | |
60 | struct clk *gclk; | |
61 | u32 mode; | |
62 | }; | |
63 | ||
64 | /** | |
65 | * mchp_pit64b_clkevt - PIT64B clockevent data structure | |
66 | * @timer: PIT64B timer | |
67 | * @clkevt: clockevent | |
68 | */ | |
69 | struct mchp_pit64b_clkevt { | |
70 | struct mchp_pit64b_timer timer; | |
71 | struct clock_event_device clkevt; | |
72 | }; | |
73 | ||
74 | #define to_mchp_pit64b_timer(x) \ | |
75 | ((struct mchp_pit64b_timer *)container_of(x,\ | |
76 | struct mchp_pit64b_clkevt, clkevt)) | |
77 | ||
78 | /* Base address for clocksource timer. */ | |
79 | static void __iomem *mchp_pit64b_cs_base; | |
80 | /* Default cycles for clockevent timer. */ | |
81 | static u64 mchp_pit64b_ce_cycles; | |
82 | ||
83 | static inline u64 mchp_pit64b_cnt_read(void __iomem *base) | |
84 | { | |
85 | unsigned long flags; | |
86 | u32 low, high; | |
87 | ||
88 | raw_local_irq_save(flags); | |
89 | ||
90 | /* | |
91 | * When using a 64 bit period TLSB must be read first, followed by the | |
92 | * read of TMSB. This sequence generates an atomic read of the 64 bit | |
93 | * timer value whatever the lapse of time between the accesses. | |
94 | */ | |
95 | low = readl_relaxed(base + MCHP_PIT64B_TLSBR); | |
96 | high = readl_relaxed(base + MCHP_PIT64B_TMSBR); | |
97 | ||
98 | raw_local_irq_restore(flags); | |
99 | ||
100 | return (((u64)high << 32) | low); | |
101 | } | |
102 | ||
103 | static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer, | |
104 | u64 cycles, u32 mode, u32 irqs) | |
105 | { | |
106 | u32 low, high; | |
107 | ||
108 | low = cycles & MCHP_PIT64B_LSBMASK; | |
109 | high = cycles >> 32; | |
110 | ||
111 | writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); | |
112 | writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR); | |
113 | writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR); | |
114 | writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR); | |
115 | writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER); | |
116 | writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR); | |
117 | } | |
118 | ||
119 | static u64 mchp_pit64b_clksrc_read(struct clocksource *cs) | |
120 | { | |
121 | return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); | |
122 | } | |
123 | ||
124 | static u64 mchp_pit64b_sched_read_clk(void) | |
125 | { | |
126 | return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); | |
127 | } | |
128 | ||
129 | static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) | |
130 | { | |
131 | struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); | |
132 | ||
133 | writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) | |
139 | { | |
140 | struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); | |
141 | ||
142 | mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, | |
143 | MCHP_PIT64B_IER_PERIOD); | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, | |
149 | struct clock_event_device *cedev) | |
150 | { | |
151 | struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); | |
152 | ||
153 | mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, | |
154 | MCHP_PIT64B_IER_PERIOD); | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) | |
160 | { | |
161 | struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); | |
162 | ||
163 | writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); | |
164 | if (timer->mode & MCHP_PIT64B_MR_SGCLK) | |
165 | clk_disable_unprepare(timer->gclk); | |
166 | clk_disable_unprepare(timer->pclk); | |
167 | } | |
168 | ||
169 | static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) | |
170 | { | |
171 | struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); | |
172 | ||
173 | clk_prepare_enable(timer->pclk); | |
174 | if (timer->mode & MCHP_PIT64B_MR_SGCLK) | |
175 | clk_prepare_enable(timer->gclk); | |
176 | } | |
177 | ||
178 | static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) | |
179 | { | |
180 | struct mchp_pit64b_clkevt *irq_data = dev_id; | |
181 | ||
182 | /* Need to clear the interrupt. */ | |
183 | readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR); | |
184 | ||
185 | irq_data->clkevt.event_handler(&irq_data->clkevt); | |
186 | ||
187 | return IRQ_HANDLED; | |
188 | } | |
189 | ||
190 | static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, | |
191 | u32 max_rate) | |
192 | { | |
193 | u32 tmp; | |
194 | ||
195 | for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) { | |
196 | tmp = clk_rate / (*pres + 1); | |
197 | if (tmp <= max_rate) | |
198 | break; | |
199 | } | |
200 | ||
201 | /* Use the bigest prescaler if we didn't match one. */ | |
202 | if (*pres == MCHP_PIT64B_PRES_MAX) | |
203 | *pres = MCHP_PIT64B_PRES_MAX - 1; | |
204 | } | |
205 | ||
206 | /** | |
207 | * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at | |
208 | * runtime; this includes prescaler and SGCLK bit | |
209 | * | |
210 | * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to | |
211 | * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate | |
212 | * could be changed via clock APIs. The chosen clock (pclk or gclk) could be | |
213 | * divided by the internal PIT64B's divider. | |
214 | * | |
215 | * This function, first tries to use GCLK by requesting the desired rate from | |
216 | * PMC and then using the internal PIT64B prescaler, if any, to reach the | |
217 | * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware) | |
218 | * then the function falls back on using PCLK as clock source for PIT64B timer | |
219 | * choosing the highest prescaler in case it doesn't locate one to match the | |
220 | * requested frequency. | |
221 | * | |
222 | * Below is presented the PIT64B block in relation with PMC: | |
223 | * | |
224 | * PIT64B | |
225 | * PMC +------------------------------------+ | |
226 | * +----+ | +-----+ | | |
227 | * | |-->gclk -->|-->| | +---------+ +-----+ | | |
228 | * | | | | MUX |--->| Divider |->|timer| | | |
229 | * | |-->pclk -->|-->| | +---------+ +-----+ | | |
230 | * +----+ | +-----+ | | |
231 | * | ^ | | |
232 | * | sel | | |
233 | * +------------------------------------+ | |
234 | * | |
235 | * Where: | |
236 | * - gclk rate <= pclk rate/3 | |
237 | * - gclk rate could be requested from PMC | |
238 | * - pclk rate is fixed (cannot be requested from PMC) | |
239 | */ | |
240 | static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer, | |
241 | unsigned long max_rate) | |
242 | { | |
243 | unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX; | |
244 | long gclk_round = 0; | |
245 | u32 pres, best_pres = 0; | |
246 | ||
247 | pclk_rate = clk_get_rate(timer->pclk); | |
248 | if (!pclk_rate) | |
249 | return -EINVAL; | |
250 | ||
b9c60a74 CB |
251 | timer->mode = 0; |
252 | ||
625022a5 CB |
253 | /* Try using GCLK. */ |
254 | gclk_round = clk_round_rate(timer->gclk, max_rate); | |
255 | if (gclk_round < 0) | |
256 | goto pclk; | |
257 | ||
258 | if (pclk_rate / gclk_round < 3) | |
259 | goto pclk; | |
260 | ||
261 | mchp_pit64b_pres_compute(&pres, gclk_round, max_rate); | |
262 | best_diff = abs(gclk_round / (pres + 1) - max_rate); | |
263 | best_pres = pres; | |
264 | ||
265 | if (!best_diff) { | |
266 | timer->mode |= MCHP_PIT64B_MR_SGCLK; | |
267 | goto done; | |
268 | } | |
269 | ||
270 | pclk: | |
271 | /* Check if requested rate could be obtained using PCLK. */ | |
272 | mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate); | |
273 | diff = abs(pclk_rate / (pres + 1) - max_rate); | |
274 | ||
275 | if (best_diff > diff) { | |
276 | /* Use PCLK. */ | |
277 | best_pres = pres; | |
278 | } else { | |
279 | /* Use GCLK. */ | |
280 | timer->mode |= MCHP_PIT64B_MR_SGCLK; | |
281 | clk_set_rate(timer->gclk, gclk_round); | |
282 | } | |
283 | ||
284 | done: | |
285 | timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres); | |
286 | ||
287 | pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n", | |
288 | timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres, | |
289 | timer->mode & MCHP_PIT64B_MR_SGCLK ? | |
290 | gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1)); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, | |
296 | u32 clk_rate) | |
297 | { | |
298 | int ret; | |
299 | ||
300 | mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); | |
301 | ||
302 | mchp_pit64b_cs_base = timer->base; | |
303 | ||
304 | ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate, | |
305 | 210, 64, mchp_pit64b_clksrc_read); | |
306 | if (ret) { | |
307 | pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); | |
308 | ||
309 | /* Stop timer. */ | |
310 | writel_relaxed(MCHP_PIT64B_CR_SWRST, | |
311 | timer->base + MCHP_PIT64B_CR); | |
312 | ||
313 | return ret; | |
314 | } | |
315 | ||
316 | sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, | |
322 | u32 clk_rate, u32 irq) | |
323 | { | |
324 | struct mchp_pit64b_clkevt *ce; | |
325 | int ret; | |
326 | ||
327 | ce = kzalloc(sizeof(*ce), GFP_KERNEL); | |
328 | if (!ce) | |
329 | return -ENOMEM; | |
330 | ||
331 | mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ); | |
332 | ||
333 | ce->timer.base = timer->base; | |
334 | ce->timer.pclk = timer->pclk; | |
335 | ce->timer.gclk = timer->gclk; | |
336 | ce->timer.mode = timer->mode; | |
337 | ce->clkevt.name = MCHP_PIT64B_NAME; | |
338 | ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; | |
339 | ce->clkevt.rating = 150; | |
340 | ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown; | |
341 | ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic; | |
342 | ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event; | |
343 | ce->clkevt.suspend = mchp_pit64b_clkevt_suspend; | |
344 | ce->clkevt.resume = mchp_pit64b_clkevt_resume; | |
345 | ce->clkevt.cpumask = cpumask_of(0); | |
346 | ce->clkevt.irq = irq; | |
347 | ||
348 | ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER, | |
349 | "pit64b_tick", ce); | |
350 | if (ret) { | |
351 | pr_debug("clkevt: Failed to setup PIT64B IRQ\n"); | |
352 | kfree(ce); | |
353 | return ret; | |
354 | } | |
355 | ||
356 | clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static int __init mchp_pit64b_dt_init_timer(struct device_node *node, | |
362 | bool clkevt) | |
363 | { | |
364 | u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ; | |
b9c60a74 | 365 | struct mchp_pit64b_timer timer; |
625022a5 CB |
366 | unsigned long clk_rate; |
367 | u32 irq = 0; | |
368 | int ret; | |
369 | ||
370 | /* Parse DT node. */ | |
371 | timer.pclk = of_clk_get_by_name(node, "pclk"); | |
372 | if (IS_ERR(timer.pclk)) | |
373 | return PTR_ERR(timer.pclk); | |
374 | ||
375 | timer.gclk = of_clk_get_by_name(node, "gclk"); | |
376 | if (IS_ERR(timer.gclk)) | |
377 | return PTR_ERR(timer.gclk); | |
378 | ||
379 | timer.base = of_iomap(node, 0); | |
380 | if (!timer.base) | |
381 | return -ENXIO; | |
382 | ||
383 | if (clkevt) { | |
384 | irq = irq_of_parse_and_map(node, 0); | |
385 | if (!irq) { | |
386 | ret = -ENODEV; | |
387 | goto io_unmap; | |
388 | } | |
389 | } | |
390 | ||
391 | /* Initialize mode (prescaler + SGCK bit). To be used at runtime. */ | |
392 | ret = mchp_pit64b_init_mode(&timer, freq); | |
393 | if (ret) | |
394 | goto irq_unmap; | |
395 | ||
396 | ret = clk_prepare_enable(timer.pclk); | |
397 | if (ret) | |
398 | goto irq_unmap; | |
399 | ||
400 | if (timer.mode & MCHP_PIT64B_MR_SGCLK) { | |
401 | ret = clk_prepare_enable(timer.gclk); | |
402 | if (ret) | |
403 | goto pclk_unprepare; | |
404 | ||
405 | clk_rate = clk_get_rate(timer.gclk); | |
406 | } else { | |
407 | clk_rate = clk_get_rate(timer.pclk); | |
408 | } | |
409 | clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); | |
410 | ||
411 | if (clkevt) | |
412 | ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq); | |
413 | else | |
414 | ret = mchp_pit64b_init_clksrc(&timer, clk_rate); | |
415 | ||
416 | if (ret) | |
417 | goto gclk_unprepare; | |
418 | ||
419 | return 0; | |
420 | ||
421 | gclk_unprepare: | |
422 | if (timer.mode & MCHP_PIT64B_MR_SGCLK) | |
423 | clk_disable_unprepare(timer.gclk); | |
424 | pclk_unprepare: | |
425 | clk_disable_unprepare(timer.pclk); | |
426 | irq_unmap: | |
427 | irq_dispose_mapping(irq); | |
428 | io_unmap: | |
429 | iounmap(timer.base); | |
430 | ||
431 | return ret; | |
432 | } | |
433 | ||
434 | static int __init mchp_pit64b_dt_init(struct device_node *node) | |
435 | { | |
436 | static int inits; | |
437 | ||
438 | switch (inits++) { | |
439 | case 0: | |
440 | /* 1st request, register clockevent. */ | |
441 | return mchp_pit64b_dt_init_timer(node, true); | |
442 | case 1: | |
443 | /* 2nd request, register clocksource. */ | |
444 | return mchp_pit64b_dt_init_timer(node, false); | |
445 | } | |
446 | ||
447 | /* The rest, don't care. */ | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init); |