[mirror_ubuntu-jammy-kernel.git] / drivers / clocksource / timer-microchip-pit64b.c

// SPDX-License-Identifier: GPL-2.0
/*
 * 64-bit Periodic Interval Timer driver
 *
 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>

#define MCHP_PIT64B_CR			0x00	/* Control Register */
#define MCHP_PIT64B_CR_START		BIT(0)
#define MCHP_PIT64B_CR_SWRST		BIT(8)

#define MCHP_PIT64B_MR			0x04	/* Mode Register */
#define MCHP_PIT64B_MR_CONT		BIT(0)
#define MCHP_PIT64B_MR_ONE_SHOT		(0)
#define MCHP_PIT64B_MR_SGCLK		BIT(3)
#define MCHP_PIT64B_MR_PRES		GENMASK(11, 8)

#define MCHP_PIT64B_LSB_PR		0x08	/* LSB Period Register */

#define MCHP_PIT64B_MSB_PR		0x0C	/* MSB Period Register */

#define MCHP_PIT64B_IER			0x10	/* Interrupt Enable Register */
#define MCHP_PIT64B_IER_PERIOD		BIT(0)

#define MCHP_PIT64B_ISR			0x1C	/* Interrupt Status Register */

#define MCHP_PIT64B_TLSBR		0x20	/* Timer LSB Register */

#define MCHP_PIT64B_TMSBR		0x24	/* Timer MSB Register */

#define MCHP_PIT64B_PRES_MAX		0x10
#define MCHP_PIT64B_LSBMASK		GENMASK_ULL(31, 0)
#define MCHP_PIT64B_PRES_TO_MODE(p)	(MCHP_PIT64B_MR_PRES & ((p) << 8))
#define MCHP_PIT64B_MODE_TO_PRES(m)	((MCHP_PIT64B_MR_PRES & (m)) >> 8)
#define MCHP_PIT64B_DEF_CS_FREQ		5000000UL	/* 5 MHz */
#define MCHP_PIT64B_DEF_CE_FREQ		32768		/* 32 KHz */

#define MCHP_PIT64B_NAME		"pit64b"

/**
 * struct mchp_pit64b_timer - PIT64B timer data structure
 * @base: base address of PIT64B hardware block
 * @pclk: PIT64B's peripheral clock
 * @gclk: PIT64B's generic clock
 * @mode: precomputed value for mode register
 */
struct mchp_pit64b_timer {
	void __iomem	*base;
	struct clk	*pclk;
	struct clk	*gclk;
	u32		mode;
};

/**
 * mchp_pit64b_clkevt - PIT64B clockevent data structure
 * @timer: PIT64B timer
 * @clkevt: clockevent
 */
struct mchp_pit64b_clkevt {
	struct mchp_pit64b_timer	timer;
	struct clock_event_device	clkevt;
};

#define to_mchp_pit64b_timer(x) \
	((struct mchp_pit64b_timer *)container_of(x,\
		struct mchp_pit64b_clkevt, clkevt))

/* Base address for clocksource timer. */
static void __iomem *mchp_pit64b_cs_base;
/* Default cycles for clockevent timer. */
static u64 mchp_pit64b_ce_cycles;

static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
{
	unsigned long	flags;
	u32		low, high;

	raw_local_irq_save(flags);

	/*
	 * When using a 64 bit period TLSB must be read first, followed by the
	 * read of TMSB. This sequence generates an atomic read of the 64 bit
	 * timer value whatever the lapse of time between the accesses.
	 */
	low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
	high = readl_relaxed(base + MCHP_PIT64B_TMSBR);

	raw_local_irq_restore(flags);

	return (((u64)high << 32) | low);
}

static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
				     u64 cycles, u32 mode, u32 irqs)
{
	u32 low, high;

	low = cycles & MCHP_PIT64B_LSBMASK;
	high = cycles >> 32;

	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
}

static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
{
	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
}

static u64 mchp_pit64b_sched_read_clk(void)
{
	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
}

static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);

	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);

	return 0;
}

static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);

	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
			  MCHP_PIT64B_IER_PERIOD);

	return 0;
}

static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
					     struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);

	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
			  MCHP_PIT64B_IER_PERIOD);

	return 0;
}

static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);

	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
		clk_disable_unprepare(timer->gclk);
	clk_disable_unprepare(timer->pclk);
}

static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
{
	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);

	clk_prepare_enable(timer->pclk);
	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
		clk_prepare_enable(timer->gclk);
}

static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
{
	struct mchp_pit64b_clkevt *irq_data = dev_id;

	/* Need to clear the interrupt. */
	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);

	irq_data->clkevt.event_handler(&irq_data->clkevt);

	return IRQ_HANDLED;
}

static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
					    u32 max_rate)
{
	u32 tmp;

	for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
		tmp = clk_rate / (*pres + 1);
		if (tmp <= max_rate)
			break;
	}

	/* Use the bigest prescaler if we didn't match one. */
	if (*pres == MCHP_PIT64B_PRES_MAX)
		*pres = MCHP_PIT64B_PRES_MAX - 1;
}

/**
 * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at
 *			   runtime; this includes prescaler and SGCLK bit
 *
 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
 * divided by the internal PIT64B's divider.
 *
 * This function, first tries to use GCLK by requesting the desired rate from
 * PMC and then using the internal PIT64B prescaler, if any, to reach the
 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
 * then the function falls back on using PCLK as clock source for PIT64B timer
 * choosing the highest prescaler in case it doesn't locate one to match the
 * requested frequency.
 *
 * Below is presented the PIT64B block in relation with PMC:
 *
 *                                PIT64B
 *  PMC             +------------------------------------+
 * +----+           |   +-----+                          |
 * |    |-->gclk -->|-->|     |    +---------+  +-----+  |
 * |    |           |   | MUX |--->| Divider |->|timer|  |
 * |    |-->pclk -->|-->|     |    +---------+  +-----+  |
 * +----+           |   +-----+                          |
 *                  |      ^                             |
 *                  |     sel                            |
 *                  +------------------------------------+
 *
 * Where:
 *	- gclk rate <= pclk rate/3
 *	- gclk rate could be requested from PMC
 *	- pclk rate is fixed (cannot be requested from PMC)
 */
static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
					unsigned long max_rate)
{
	unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
	long gclk_round = 0;
	u32 pres, best_pres = 0;

	pclk_rate = clk_get_rate(timer->pclk);
	if (!pclk_rate)
		return -EINVAL;

	/* Try using GCLK. */
	gclk_round = clk_round_rate(timer->gclk, max_rate);
	if (gclk_round < 0)
		goto pclk;

	if (pclk_rate / gclk_round < 3)
		goto pclk;

	mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
	best_diff = abs(gclk_round / (pres + 1) - max_rate);
	best_pres = pres;

	if (!best_diff) {
		timer->mode |= MCHP_PIT64B_MR_SGCLK;
		goto done;
	}

pclk:
	/* Check if requested rate could be obtained using PCLK. */
	mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
	diff = abs(pclk_rate / (pres + 1) - max_rate);

	if (best_diff > diff) {
		/* Use PCLK. */
		best_pres = pres;
	} else {
		/* Use GCLK. */
		timer->mode |= MCHP_PIT64B_MR_SGCLK;
		clk_set_rate(timer->gclk, gclk_round);
	}

done:
	timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);

	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
		timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
		timer->mode & MCHP_PIT64B_MR_SGCLK ?
		gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));

	return 0;
}

static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
					  u32 clk_rate)
{
	int ret;

	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);

	mchp_pit64b_cs_base = timer->base;

	ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
				    210, 64, mchp_pit64b_clksrc_read);
	if (ret) {
		pr_debug("clksrc: Failed to register PIT64B clocksource!\n");

		/* Stop timer. */
		writel_relaxed(MCHP_PIT64B_CR_SWRST,
			       timer->base + MCHP_PIT64B_CR);

		return ret;
	}

	sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);

	return 0;
}

static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
					  u32 clk_rate, u32 irq)
{
	struct mchp_pit64b_clkevt *ce;
	int ret;

	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
	if (!ce)
		return -ENOMEM;

	mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);

	ce->timer.base = timer->base;
	ce->timer.pclk = timer->pclk;
	ce->timer.gclk = timer->gclk;
	ce->timer.mode = timer->mode;
	ce->clkevt.name = MCHP_PIT64B_NAME;
	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
	ce->clkevt.rating = 150;
	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
	ce->clkevt.suspend = mchp_pit64b_clkevt_suspend;
	ce->clkevt.resume = mchp_pit64b_clkevt_resume;
	ce->clkevt.cpumask = cpumask_of(0);
	ce->clkevt.irq = irq;

	ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
			  "pit64b_tick", ce);
	if (ret) {
		pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
		kfree(ce);
		return ret;
	}

	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);

	return 0;
}

static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
					    bool clkevt)
{
	u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ;
	struct mchp_pit64b_timer timer = { 0 };
	unsigned long clk_rate;
	u32 irq = 0;
	int ret;

	/* Parse DT node. */
	timer.pclk = of_clk_get_by_name(node, "pclk");
	if (IS_ERR(timer.pclk))
		return PTR_ERR(timer.pclk);

	timer.gclk = of_clk_get_by_name(node, "gclk");
	if (IS_ERR(timer.gclk))
		return PTR_ERR(timer.gclk);

	timer.base = of_iomap(node, 0);
	if (!timer.base)
		return -ENXIO;

	if (clkevt) {
		irq = irq_of_parse_and_map(node, 0);
		if (!irq) {
			ret = -ENODEV;
			goto io_unmap;
		}
	}

	/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
	ret = mchp_pit64b_init_mode(&timer, freq);
	if (ret)
		goto irq_unmap;

	ret = clk_prepare_enable(timer.pclk);
	if (ret)
		goto irq_unmap;

	if (timer.mode & MCHP_PIT64B_MR_SGCLK) {
		ret = clk_prepare_enable(timer.gclk);
		if (ret)
			goto pclk_unprepare;

		clk_rate = clk_get_rate(timer.gclk);
	} else {
		clk_rate = clk_get_rate(timer.pclk);
	}
	clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);

	if (clkevt)
		ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
	else
		ret = mchp_pit64b_init_clksrc(&timer, clk_rate);

	if (ret)
		goto gclk_unprepare;

	return 0;

gclk_unprepare:
	if (timer.mode & MCHP_PIT64B_MR_SGCLK)
		clk_disable_unprepare(timer.gclk);
pclk_unprepare:
	clk_disable_unprepare(timer.pclk);
irq_unmap:
	irq_dispose_mapping(irq);
io_unmap:
	iounmap(timer.base);

	return ret;
}

static int __init mchp_pit64b_dt_init(struct device_node *node)
{
	static int inits;

	switch (inits++) {
	case 0:
		/* 1st request, register clockevent. */
		return mchp_pit64b_dt_init_timer(node, true);
	case 1:
		/* 2nd request, register clocksource. */
		return mchp_pit64b_dt_init_timer(node, false);
	}

	/* The rest, don't care. */
	return -EINVAL;
}

TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);
Commit	Line	Data
625022a5 CB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* 64-bit Periodic Interval Timer driver
	4	*
	5	* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
	6	*
	7	* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/sched_clock.h>
	16	#include <linux/slab.h>
	17
	18	#define MCHP_PIT64B_CR 0x00 /* Control Register */
	19	#define MCHP_PIT64B_CR_START BIT(0)
	20	#define MCHP_PIT64B_CR_SWRST BIT(8)
	21
	22	#define MCHP_PIT64B_MR 0x04 /* Mode Register */
	23	#define MCHP_PIT64B_MR_CONT BIT(0)
	24	#define MCHP_PIT64B_MR_ONE_SHOT (0)
	25	#define MCHP_PIT64B_MR_SGCLK BIT(3)
	26	#define MCHP_PIT64B_MR_PRES GENMASK(11, 8)
	27
	28	#define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */
	29
	30	#define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */
	31
	32	#define MCHP_PIT64B_IER 0x10 /* Interrupt Enable Register */
	33	#define MCHP_PIT64B_IER_PERIOD BIT(0)
	34
	35	#define MCHP_PIT64B_ISR 0x1C /* Interrupt Status Register */
	36
	37	#define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */
	38
	39	#define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */
	40
	41	#define MCHP_PIT64B_PRES_MAX 0x10
	42	#define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0)
	43	#define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8))
	44	#define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8)
	45	#define MCHP_PIT64B_DEF_CS_FREQ 5000000UL /* 5 MHz */
	46	#define MCHP_PIT64B_DEF_CE_FREQ 32768 /* 32 KHz */
	47
	48	#define MCHP_PIT64B_NAME "pit64b"
	49
	50	/**
	51	* struct mchp_pit64b_timer - PIT64B timer data structure
	52	* @base: base address of PIT64B hardware block
	53	* @pclk: PIT64B's peripheral clock
	54	* @gclk: PIT64B's generic clock
	55	* @mode: precomputed value for mode register
	56	*/
	57	struct mchp_pit64b_timer {
	58	void __iomem *base;
	59	struct clk *pclk;
	60	struct clk *gclk;
	61	u32 mode;
	62	};
	63
	64	/**
65	* mchp_pit64b_clkevt - PIT64B clockevent data structure
66	* @timer: PIT64B timer
67	* @clkevt: clockevent
68	*/
69	struct mchp_pit64b_clkevt {
70	struct mchp_pit64b_timer timer;
71	struct clock_event_device clkevt;
72	};
73
74	#define to_mchp_pit64b_timer(x) \
75	((struct mchp_pit64b_timer *)container_of(x,\
76	struct mchp_pit64b_clkevt, clkevt))
77
78	/* Base address for clocksource timer. */
79	static void __iomem *mchp_pit64b_cs_base;
80	/* Default cycles for clockevent timer. */
81	static u64 mchp_pit64b_ce_cycles;
82
83	static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
84	{
85	unsigned long flags;
86	u32 low, high;
87
88	raw_local_irq_save(flags);
89
90	/*
91	* When using a 64 bit period TLSB must be read first, followed by the
92	* read of TMSB. This sequence generates an atomic read of the 64 bit
93	* timer value whatever the lapse of time between the accesses.
94	*/
95	low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
96	high = readl_relaxed(base + MCHP_PIT64B_TMSBR);
97
98	raw_local_irq_restore(flags);
99
100	return (((u64)high << 32) \| low);
101	}
102
103	static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
104	u64 cycles, u32 mode, u32 irqs)
105	{
106	u32 low, high;
107
108	low = cycles & MCHP_PIT64B_LSBMASK;
109	high = cycles >> 32;
110
111	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
112	writel_relaxed(mode \| timer->mode, timer->base + MCHP_PIT64B_MR);
113	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
114	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
115	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
116	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
117	}
118
119	static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
120	{
121	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
122	}
123
124	static u64 mchp_pit64b_sched_read_clk(void)
125	{
126	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
127	}
128
129	static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
130	{
131	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
132
133	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
134
135	return 0;
136	}
137
138	static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
139	{
140	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
141
142	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
143	MCHP_PIT64B_IER_PERIOD);
144
145	return 0;
146	}
147
148	static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
149	struct clock_event_device *cedev)
150	{
151	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
152
153	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
154	MCHP_PIT64B_IER_PERIOD);
155
156	return 0;
157	}
158
159	static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
160	{
161	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
162
163	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
164	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
165	clk_disable_unprepare(timer->gclk);
166	clk_disable_unprepare(timer->pclk);
167	}
168
169	static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
170	{
171	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
172
173	clk_prepare_enable(timer->pclk);
174	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
175	clk_prepare_enable(timer->gclk);
176	}
177
178	static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
179	{
180	struct mchp_pit64b_clkevt *irq_data = dev_id;
181
182	/* Need to clear the interrupt. */
183	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);
184
185	irq_data->clkevt.event_handler(&irq_data->clkevt);
186
187	return IRQ_HANDLED;
188	}
189
190	static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
191	u32 max_rate)
192	{
193	u32 tmp;
194
195	for (pres = 0; pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
196	tmp = clk_rate / (*pres + 1);
197	if (tmp <= max_rate)
198	break;
199	}
200
201	/* Use the bigest prescaler if we didn't match one. */
202	if (*pres == MCHP_PIT64B_PRES_MAX)
203	*pres = MCHP_PIT64B_PRES_MAX - 1;
204	}
205
206	/**
207	* mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at
208	* runtime; this includes prescaler and SGCLK bit
209	*
210	* PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
211	* be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
212	* could be changed via clock APIs. The chosen clock (pclk or gclk) could be
213	* divided by the internal PIT64B's divider.
214	*
215	* This function, first tries to use GCLK by requesting the desired rate from
216	* PMC and then using the internal PIT64B prescaler, if any, to reach the
217	* requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
218	* then the function falls back on using PCLK as clock source for PIT64B timer
219	* choosing the highest prescaler in case it doesn't locate one to match the
220	* requested frequency.
221	*
222	* Below is presented the PIT64B block in relation with PMC:
223	*
224	* PIT64B
225	* PMC +------------------------------------+
226	* +----+ \| +-----+ \|
227	* \| \|-->gclk -->\|-->\| \| +---------+ +-----+ \|
228	* \| \| \| \| MUX \|--->\| Divider \|->\|timer\| \|
229	* \| \|-->pclk -->\|-->\| \| +---------+ +-----+ \|
230	* +----+ \| +-----+ \|
231	* \| ^ \|
232	* \| sel \|
233	* +------------------------------------+
234	*
235	* Where:
236	* - gclk rate <= pclk rate/3
237	* - gclk rate could be requested from PMC
238	* - pclk rate is fixed (cannot be requested from PMC)
239	*/
240	static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
241	unsigned long max_rate)
242	{
243	unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
244	long gclk_round = 0;
245	u32 pres, best_pres = 0;
246
247	pclk_rate = clk_get_rate(timer->pclk);
248	if (!pclk_rate)
249	return -EINVAL;
250
251	/* Try using GCLK. */
252	gclk_round = clk_round_rate(timer->gclk, max_rate);
253	if (gclk_round < 0)
254	goto pclk;
255
256	if (pclk_rate / gclk_round < 3)
257	goto pclk;
258
259	mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
260	best_diff = abs(gclk_round / (pres + 1) - max_rate);
261	best_pres = pres;
262
263	if (!best_diff) {
264	timer->mode \|= MCHP_PIT64B_MR_SGCLK;
265	goto done;
266	}
267
268	pclk:
269	/* Check if requested rate could be obtained using PCLK. */
270	mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
271	diff = abs(pclk_rate / (pres + 1) - max_rate);
272
273	if (best_diff > diff) {
274	/* Use PCLK. */
275	best_pres = pres;
276	} else {
277	/* Use GCLK. */
278	timer->mode \|= MCHP_PIT64B_MR_SGCLK;
279	clk_set_rate(timer->gclk, gclk_round);
280	}
281
282	done:
283	timer->mode \|= MCHP_PIT64B_PRES_TO_MODE(best_pres);
284
285	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
286	timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
287	timer->mode & MCHP_PIT64B_MR_SGCLK ?
288	gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));
289
290	return 0;
291	}
292
293	static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
294	u32 clk_rate)
295	{
296	int ret;
297
298	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
299
300	mchp_pit64b_cs_base = timer->base;
301
302	ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
303	210, 64, mchp_pit64b_clksrc_read);
304	if (ret) {
305	pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
306
307	/* Stop timer. */
308	writel_relaxed(MCHP_PIT64B_CR_SWRST,
309	timer->base + MCHP_PIT64B_CR);
310
311	return ret;
312	}
313
314	sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);
315
316	return 0;
317	}
318
319	static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
320	u32 clk_rate, u32 irq)
321	{
322	struct mchp_pit64b_clkevt *ce;
323	int ret;
324
325	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
326	if (!ce)
327	return -ENOMEM;
328
329	mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);
330
331	ce->timer.base = timer->base;
332	ce->timer.pclk = timer->pclk;
333	ce->timer.gclk = timer->gclk;
334	ce->timer.mode = timer->mode;
335	ce->clkevt.name = MCHP_PIT64B_NAME;
336	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC;
337	ce->clkevt.rating = 150;
338	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
339	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
340	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
341	ce->clkevt.suspend = mchp_pit64b_clkevt_suspend;
342	ce->clkevt.resume = mchp_pit64b_clkevt_resume;
343	ce->clkevt.cpumask = cpumask_of(0);
344	ce->clkevt.irq = irq;
345
346	ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
347	"pit64b_tick", ce);
348	if (ret) {
349	pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
350	kfree(ce);
351	return ret;
352	}
353
354	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);
355
356	return 0;
357	}
358
359	static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
360	bool clkevt)
361	{
362	u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ;
363	struct mchp_pit64b_timer timer = { 0 };
364	unsigned long clk_rate;
365	u32 irq = 0;
366	int ret;
367
368	/* Parse DT node. */
369	timer.pclk = of_clk_get_by_name(node, "pclk");
370	if (IS_ERR(timer.pclk))
371	return PTR_ERR(timer.pclk);
372
373	timer.gclk = of_clk_get_by_name(node, "gclk");
374	if (IS_ERR(timer.gclk))
375	return PTR_ERR(timer.gclk);
376
377	timer.base = of_iomap(node, 0);
378	if (!timer.base)
379	return -ENXIO;
380
381	if (clkevt) {
382	irq = irq_of_parse_and_map(node, 0);
383	if (!irq) {
384	ret = -ENODEV;
385	goto io_unmap;
386	}
387	}
388
389	/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
390	ret = mchp_pit64b_init_mode(&timer, freq);
391	if (ret)
392	goto irq_unmap;
393
394	ret = clk_prepare_enable(timer.pclk);
395	if (ret)
396	goto irq_unmap;
397
398	if (timer.mode & MCHP_PIT64B_MR_SGCLK) {
399	ret = clk_prepare_enable(timer.gclk);
400	if (ret)
401	goto pclk_unprepare;
402
403	clk_rate = clk_get_rate(timer.gclk);
404	} else {
405	clk_rate = clk_get_rate(timer.pclk);
406	}
407	clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);
408
409	if (clkevt)
410	ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
411	else
412	ret = mchp_pit64b_init_clksrc(&timer, clk_rate);
413
414	if (ret)
415	goto gclk_unprepare;
416
417	return 0;
418
419	gclk_unprepare:
420	if (timer.mode & MCHP_PIT64B_MR_SGCLK)
421	clk_disable_unprepare(timer.gclk);
422	pclk_unprepare:
423	clk_disable_unprepare(timer.pclk);
424	irq_unmap:
425	irq_dispose_mapping(irq);
426	io_unmap:
427	iounmap(timer.base);
428
429	return ret;
430	}
431
432	static int __init mchp_pit64b_dt_init(struct device_node *node)
433	{
434	static int inits;
435
436	switch (inits++) {
437	case 0:
438	/* 1st request, register clockevent. */
439	return mchp_pit64b_dt_init_timer(node, true);
440	case 1:
441	/* 2nd request, register clocksource. */
442	return mchp_pit64b_dt_init_timer(node, false);
443	}
444
445	/* The rest, don't care. */
446	return -EINVAL;
447	}
448
449	TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);